JP4304760B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

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Publication number
JP4304760B2
JP4304760B2 JP13227999A JP13227999A JP4304760B2 JP 4304760 B2 JP4304760 B2 JP 4304760B2 JP 13227999 A JP13227999 A JP 13227999A JP 13227999 A JP13227999 A JP 13227999A JP 4304760 B2 JP4304760 B2 JP 4304760B2
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Japan
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semiconductor light
light emitting
electrodes
lead frame
emitting device
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JP2000323755A (en
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誠 野添
俊秀 前田
祐二 小林
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、フリップチップ型の半導体発光素子を備える半導体発光装置に係り、特に半導体発光素子の小型化に対応できるリードフレームとのアセンブリを可能とした半導体発光装置に関する。
【０００２】
【従来の技術】
ＧａＮ，ＧａＡｌＮ，ＩｎＧａＮ及びＩｎＡｌＧａＮ等のＧａＮ系化合物半導体を利用した青色発光の発光素子は、結晶成長のための基板として現在ではサファイアが最も一般的なものとして利用されている。この絶縁性のサファイアを基板とする発光素子では、ｐ側及びｎ側の両方の電極は基板と反対側の面であって半導体の積層膜の表面に形成される。このようにｐ側及びｎ側の電極が同一面にあることを利用して、これらの電極のそれぞれにバンプ電極を形成し、基板側が発光方向を向く姿勢としたフリップチップ型のアセンブリとするものが従来から知られている。
【０００３】
図５はＧａＮ系化合物半導体を利用した半導体発光素子をフリップチップ型としてリードフレームに搭載したＬＥＤランプの概略図であって、同図の（ａ）は縦断面図、同図の（ｂ）は横断面図である。
【０００４】
図５において、プリント配線基板（図示せず）に導通固定されるリードフレーム５１の一対のリード５１ａ，５１ｂのそれぞれの上端にマウント部５１ｃ，５１ｄが形成され、これらのマウント部５１ｃ，５１ｄに半導体発光素子１を跨がせて搭載するとともに、全体をエポキシ樹脂を用いた樹脂ヘッド５２によって封止している。
【０００５】
半導体発光素子１は、図６に示すように、絶縁性であって光透過性のサファイアを利用した基板１ａにＧａＮのｎ型層１ｂ及びｐ型層１ｃを順に積層してこれらの層の間を活性層とし、ｎ型層１ｂの表面にはｎ側電極パッド１ｄ及びｐ型層１ｃの表面にはｐ側電極パッド１ｅを金属蒸着法によって形成したものである。そして、ｎ側及びｐ側の電極パッド１ｄ，１ｅにはバンプ電極２ａ，２ｂがそれぞれ形成されている。
【０００６】
半導体発光素子１は、バンプ電極２ａ，２ｂをマウント部５１ｄ，５１ｃの上に載せて超音波圧着と加熱圧着を加えることで接合され、リード５１ｂ，５１ａにそれぞれ導通固定される。そして、活性層からの光は基板１ａを抜けて図６において上向きに発光され、この基板１ａの上端面を主光取出し面とする。
【０００７】
【発明が解決しようとする課題】
図示の例の半導体発光素子１も含めて、素子の一般的な製造は、基板材料にＧａＮのｎ型層やｐ型層をウエハー状態で積層するとともにｎ側及びｐ側の電極パッドを蒸着形成し、ダイサーによってダイシングすることでチップ状の発光素子を得るというものである。そして、近来ではダイシング技術の進歩や電極形成のためのパターニングの精度の向上等によって、発光素子のより一層の小型化が可能となった。このような発光素子の小型化は、小型で薄型化が最も重要な設計課題となっている電子機器への対応の面で非常に有効とされている。
【０００８】
一方、半導体発光素子１を搭載するためのリードフレーム５１の製造では、ｐ側とｎ側との導通のためにマウント部５１ｃ，５１ｄを分断する加工が必要である。すなわちリードフレーム５１の先端側すなわちマウント部５１ｃ，５１ｄが最終的に形成される部分を一体にしてリード５１ａ，５１ｂが延びた二股状の部品として製作しておき、一体となっている部分の中央を切開してマウント部５１ｃ，５１ｄに分離する工程によって加工される。
【０００９】
ところが、切り開かれたマウント部５１ｃ，５１ｄとの間のギャップ５１ｅの切開幅は、リードフレーム５１の肉厚にも関係するが、従来では最小で０．４ｍｍ程度である。そして、加工誤差等を含むと０．４ｍｍ以上となってしまうことが殆どである。
【００１０】
このようにリードフレーム５１の加工の面から、マウント部５１ｃ，５１ｄとの間のギャップ５１ｅの幅には下限がある。その一方で半導体発光素子１は小型化が更に進み、バンプ電極２ａ，２ｂどうしの間隔もより短くなる傾向にある。したがって、バンプ電極２ａ，２ｂの間隔がギャップ５１ｅの幅よりも短くなると、これらのバンプ電極２ａ，２ｂのいずれか一方しかマウント部５１ｃ，５１ｄに接合できず、アセンブリできないことになる。
【００１１】
以上のように、半導体発光素子１は小型化が進んでいる一方で、リードフレーム５１についてはその製造上の制約からマウント部５１ｃ，５１ｄの間のギャップ５１ｅを狭めることができない状況にある。このため、二つに分離されたマウント部５１ｃ，５１ｄに搭載してＬＥＤランプ型とする場合では、半導体発光素子１とリードフレーム５１とのマッチングが採れず、装置の小型化の大きな障害となっている。
【００１２】
本発明において解決すべき課題は、半導体発光素子の小型化に対応できるリードフレームへの導通搭載のためのアセンブリ構造を提供することにある。
【００１３】
【課題を解決するための手段】
本発明は、光透過性の基板の上に半導体薄膜層を積層するとともにこの積層膜の表面側にｐ側及びｎ側の電極をそれぞれ形成し且つ前記基板側を主光取出し面とする半導体発光素子と、前記ｐ側及びｎ側の電極にそれぞれ導通する一対の電極のパターンを一体に形成するとともに前記半導体発光素子を搭載する合成樹脂製のマウントカップと、一対のリードのそれぞれの先端に前記マウントカップを搭載し且つ前記一対の電極パターンにそれぞれ導通するステーを形成したリードフレームとを含み、前記マウントカップに形成する一対の電極の間の間隔を前記リードフレームのステーどうしの間隔より短くしたことを特徴とする。
【００１４】
この構成では、ステーどうしの間の距離がリードフレームの製造上から或る値以上としなければならなくても、合成樹脂製のマウントカップに備える電極どうしの間の間隔を狭くすることによって、小型化されてｐ側及びｎ側の電極間の距離が短い半導体発光素子でも導通搭載が可能となる。
【００１５】
【発明の実施の形態】
請求項１に記載の発明は、光透過性の基板の上に半導体薄膜層を積層するとともにこの積層膜の表面側にｐ側及びｎ側の電極をそれぞれ形成し且つ前記基板側を主光取出し面とする半導体発光素子と、前記ｐ側及びｎ側の電極にそれぞれ導通する一対の電極のパターンを一体に形成するとともに前記半導体発光素子を搭載する合成樹脂製のマウントカップと、一対のリードのそれぞれの先端に前記マウントカップを搭載し且つ前記一対の電極パターンにそれぞれ導通するステーを形成したリードフレームとを含み、前記マウントカップに形成する一対の電極の間の間隔を前記リードフレームのステーどうしの間隔より短くしたことを特徴とする半導体発光装置であり、リードフレームの形状や大きさの態様に関係なくｐ側及びｎ側の電極間の距離が短い半導体発光素子でも導通搭載できるという作用を有する。
【００１６】
請求項２の発明は、前記マウントカップは、その素材の合成樹脂の中に光反射性のフィラーを混入したことを特徴とする請求項１記載の半導体発光装置であり、樹脂製のマウントカップであってもフィラーによる光反射が利用できるという作用を有する。
【００１７】
以下に、本発明の実施の形態の具体例を図面を参照しながら説明する。
【００１８】
図１は本発明の一実施の形態による半導体発光装置の要部を示す縦断面図、図２及び図３は図１の平面図及び底面図である。なお、半導体発光素子は図６に示したものと同様であり、同じ構成部材については共通の符号で指示する。
【００１９】
図１において、プリント配線基板（図示せず）等に基端を導通固定されるリードフレーム３の一対のリード３ａ，３ｂのそれぞれの上端には直角に曲げたステー３ａ−１，３ｂ−１をそれぞれ形成し、これらのステー３ａ−１，３ｂ−１の上面に半導体発光素子１を導通固定したマウントカップ４を固定している。
【００２０】
リードフレーム３は従来例と同様に先端側すなわちステー３ａ−１，３ｂ−１部分を一体として二股状に形成していき、この一体部分を分断してステー３ａ−１，３ｂ−１に分離してその間をギャップ３ｃとしたものである。そして、このギャップ３ｃの開口幅Ｗは、現在の製造技術では０．４ｍｍ程度である。
【００２１】
マウントカップ４はたとえば白色系の液晶ポリマー（ＬＣＰ）を素材とし、半導発光素子１の周りを囲むすり鉢状に型製作されたものである。そして、半導体発光素子１から下方及び側方から抜ける光を発光方向に反射させるために、光反射性のたとえばＴｉＯ2等の化合物をフィラーとして混入している。
【００２２】
マウントカップ４の底部４ａには半導体発光素子１とリードフレーム３とを導通させるための一対の電極５，６を設ける。これらの電極５，６は、フィラーを混入したマウントカップ４とともに型製作するときに一体に封止されるもので、図２及び図３に示すように、長方形の平面形状を持つ。すなわち、電極５，６は底部４ａの中心部分にこの底部４ａよりも上に突き出る素子側導通部５ａ，６ａを形成するとともに、底部４ａの下面と同じ面内で露出するリード側導通部５ｂ，６ｂを備えている。
【００２３】
ここで、電極５，６はマウントカップ４を樹脂によって型成形するときに一体に封止するので、製造用の型に対するこれらの電極５，６の位置を正しく設定することで、互いの間の距離を小さくできる。すなわち、図１に示すように、電極５，６の素子側導通部５ａ，６ａどうしの間の間隔をリードフレーム３のギャップ３ｃの開口幅Ｗよりも短くした成形が可能である。したがって、半導体発光素子１のｎ側及びｐ側のバンプ電極２ａ，２ｂどうしの距離がたとえばギャップ３ｃの開口幅Ｗより短くても、素子側導通部５ａ，６ａにマウントできる。
【００２４】
電極５，６を一体に備えたマウントカップ４は、リード３ａ，３ｂのステー３ａ−１，３ｂ−１に図１及び図３の位置関係となるように搭載する。そして、ステー３ａ−１，３ｂ−１よりもリード側導通部５ｂ，６ｂの平面形状を大きくしておくことによって、図３に示すようにこれらのステー３ａ−１，３ｂ−１とリード側導通部５ｂ，６ｂとを半田７付けでき、これによってリードフレーム３にマウントカップ４が固定されると同時に、電極５，６とリード３ａ，３ｂとの導通が得られる。
【００２５】
このようにマウントカップ４をリードフレーム３に一体とすることで、マウントカップ４に予め設けた電極５，６はリード３ａ，３ｂに導通する。したがって、素子側導通部５ａ，６ａの上にバンプ電極２ａ，２ｂを載せて超音波圧着及び加熱圧着すれば、これらが接合して半導体発光素子１が実装される。この実装に際しては、先に述べたように素子側導通部５ａ，６ａの間の間隔がリードフレーム３のギャップ３ｃよりも短いので、半導体発光素子１が小型であってバンプ電極２ａ，２ｂの間隔が狭いものでも対応できる。
【００２６】
また、マウントカップ４にはＴｉＯ2等の光反射性の高いフィラーを混入しているので、半導体発光素子１から底部４ａ及び内周面４ｂ側に抜ける光を図１において基板１ａの上面の主光取出し面からの発光方向へ反射させて回収できる。したがって、マウントカップ４を合成樹脂製としていても、反射光による発光輝度の向上も可能となる。
【００２７】
図４はマウントカップ４に設ける電極５，６の形成パターンの別の例を示す要部の平面図である。
【００２８】
図示の例では、ｎ側及びｐ側の電極パッド１ｄ，１ｅは半導体発光素子１の平面外郭の中で対角線方向に離れて位置しているので、電極５，６の素子側導通部５ａ，６ａにはこれらの電極パッド１ｄ，１ｅに接合するバンプ電極２ａ，２ｂを含めるように展開させた形状を持たせている。このように、半導体発光素子１のｐ側及びｎ側の電極の配置や位置関係が変わっても、電極５，６のマウントカップ４内でのパターンを変更するだけの対応で済み、各種の半導体発光素子の搭載にも対応できる。
【００２９】
【発明の効果】
請求項１の発明では、合成樹脂製のマウントカップに電極を形成するときにはそのパターン形成が自在なので電極どうしの間の間隔を短くでき、ｐ側及びｎ側の電極の間の距離が短い小型の半導体発光素子でも支障なくアセンブリでき、装置の小型化が更に促進される。
【００３０】
請求項２の発明では、マウントカップに光反射性のフィラーを混入することで、光反射機能を持たせることができるので、マウントカップを合成樹脂製としていても発光輝度の低下を招くことがない。
【図面の簡単な説明】
【図１】本発明の一実施の形態による半導体発光装置の要部の縦断面図
【図２】マウントカップに設ける電極のパターンと半導体発光素子との位置関係を示すための概略平面図
【図３】マウントカップに設ける電極のリード側導通部とリードとの位置関係を示す概略底面図
【図４】マウントカップに設ける電極パターンの別の例を示す概略平面図
【図５】従来のフリップチップ型の半導体発光素子を備えたＬＥＤランプの例であって、
（ａ）はその縦断面図
（ｂ）はその横断面図
【図６】従来例における半導体発光素子のリードフレームへの導通搭載構造を示す要部の縦断面図
【符号の説明】
１ 半導体発光素子
１ａ 基板
１ｂ ｎ型層
１ｃ ｐ型層
１ｄ ｎ側電極パッド
１ｅ ｐ側電極パッド
２ａ，２ｂ バンプ電極
３ リードフレーム
３ａ，３ｂ リード
３ａ−１，３ｂ−１ ステー
３ｃ ギャップ
４ マウントカップ
４ａ 底部
４ｂ 内周面
５，６ 電極
５ａ，６ａ 素子側導通部
５ｂ，６ｂ リード側導通部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor light-emitting device including a flip-chip type semiconductor light-emitting element, and more particularly to a semiconductor light-emitting device capable of being assembled with a lead frame that can cope with downsizing of the semiconductor light-emitting element.
[0002]
[Prior art]
In blue light emitting devices using GaN-based compound semiconductors such as GaN, GaAlN, InGaN, and InAlGaN, sapphire is currently the most commonly used substrate for crystal growth. In this light-emitting element using insulating sapphire as a substrate, both the p-side and n-side electrodes are formed on the surface opposite to the substrate and on the surface of the semiconductor laminated film. In this way, using the fact that the p-side and n-side electrodes are on the same plane, a bump electrode is formed on each of these electrodes, and a flip-chip type assembly in which the substrate side faces the light emitting direction is formed. Is conventionally known.
[0003]
FIG. 5 is a schematic view of an LED lamp in which a semiconductor light emitting element using a GaN-based compound semiconductor is mounted on a lead frame as a flip chip type, in which (a) is a longitudinal sectional view, and (b) is the same figure. It is a cross-sectional view.
[0004]
In FIG. 5, mount portions 51c and 51d are formed at the upper ends of a pair of leads 51a and 51b of a lead frame 51 that is conductively fixed to a printed wiring board (not shown), and a semiconductor is formed on these mount portions 51c and 51d. The light-emitting element 1 is mounted across the board, and the whole is sealed by a resin head 52 using an epoxy resin.
[0005]
As shown in FIG. 6, the semiconductor light emitting device 1 is formed by sequentially laminating a GaN n-type layer 1 b and a p-type layer 1 c on an insulating and light-transmitting sapphire substrate 1 a. Is an active layer, and an n-side electrode pad 1d is formed on the surface of the n-type layer 1b and a p-side electrode pad 1e is formed on the surface of the p-type layer 1c by a metal vapor deposition method. Bump electrodes 2a and 2b are formed on the n-side and p-side electrode pads 1d and 1e, respectively.
[0006]
The semiconductor light emitting device 1 is bonded by placing the bump electrodes 2a and 2b on the mount portions 51d and 51c and applying ultrasonic pressure bonding and heat pressure bonding, and is electrically conductively fixed to the leads 51b and 51a, respectively. Then, light from the active layer passes through the substrate 1a and is emitted upward in FIG. 6, and the upper end surface of the substrate 1a is used as a main light extraction surface.
[0007]
[Problems to be solved by the invention]
In general manufacturing of the device including the semiconductor light emitting device 1 of the illustrated example, an n-type layer and a p-type layer of GaN are laminated on a substrate material in a wafer state, and n-side and p-side electrode pads are formed by vapor deposition. The chip-shaped light emitting device is obtained by dicing with a dicer. Recently, the light emitting device can be further reduced in size due to the progress of dicing technology and the improvement of patterning accuracy for electrode formation. Such downsizing of the light emitting element is considered to be very effective in terms of dealing with an electronic device in which miniaturization and thinning are the most important design issues.
[0008]
On the other hand, in manufacturing the lead frame 51 for mounting the semiconductor light emitting element 1, it is necessary to divide the mount parts 51 c and 51 d for conduction between the p side and the n side. That is, the tip end side of the lead frame 51, that is, the part where the mount parts 51c and 51d are finally formed is integrated and manufactured as a bifurcated part in which the leads 51a and 51b extend, and the center of the integrated part Is cut out and separated into mount parts 51c and 51d.
[0009]
However, the incision width of the gap 51e between the cut-off mount portions 51c and 51d is related to the thickness of the lead frame 51, but is conventionally about 0.4 mm at the minimum. And it is almost 0.4mm or more including a processing error.
[0010]
Thus, from the processing surface of the lead frame 51, there is a lower limit on the width of the gap 51e between the mount portions 51c and 51d. On the other hand, the semiconductor light emitting device 1 is further miniaturized, and the distance between the bump electrodes 2a and 2b tends to be shorter. Therefore, when the interval between the bump electrodes 2a and 2b is shorter than the width of the gap 51e, only one of the bump electrodes 2a and 2b can be bonded to the mount portions 51c and 51d, and assembly is impossible.
[0011]
As described above, while the semiconductor light emitting device 1 is being reduced in size, the lead frame 51 is in a situation where the gap 51e between the mount portions 51c and 51d cannot be narrowed due to manufacturing restrictions. For this reason, in the case where the LED lamp type is mounted on the two mount parts 51c and 51d separated from each other, the matching between the semiconductor light emitting element 1 and the lead frame 51 cannot be achieved, which is a major obstacle to downsizing the apparatus. ing.
[0012]
The problem to be solved in the present invention is to provide an assembly structure for conductive mounting on a lead frame that can cope with the miniaturization of a semiconductor light emitting element.
[0013]
[Means for Solving the Problems]
The present invention provides a semiconductor light emitting device in which a semiconductor thin film layer is laminated on a light-transmitting substrate, p-side and n-side electrodes are formed on the surface side of the laminated film, and the substrate side is the main light extraction surface. An element, a pair of electrode patterns that are electrically connected to the p-side electrode and the n-side electrode, respectively, and a synthetic resin mount cup on which the semiconductor light-emitting element is mounted, and a tip of each of a pair of leads A lead frame on which a mount cup is mounted and a stay that is electrically connected to the pair of electrode patterns is formed, and the distance between the pair of electrodes formed on the mount cup is made shorter than the distance between the stays of the lead frame. It is characterized by that.
[0014]
In this configuration, even if the distance between the stays has to be a certain value or more from the manufacturing of the lead frame, the distance between the electrodes provided in the synthetic resin mount cup is reduced, thereby reducing the size. Therefore, even a semiconductor light emitting device having a short distance between the p-side and n-side electrodes can be mounted on the conductive side.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
According to the first aspect of the present invention, a semiconductor thin film layer is laminated on a light-transmitting substrate, and p-side and n-side electrodes are formed on the surface side of the laminated film, respectively, and the substrate side is taken out of the main light. A semiconductor light-emitting element as a surface, a pair of electrode patterns respectively conducting to the p-side and n-side electrodes, and a synthetic resin mount cup on which the semiconductor light-emitting element is mounted, and a pair of leads A lead frame on which the mount cup is mounted at each tip and a stay that is electrically connected to the pair of electrode patterns is formed, and a distance between the pair of electrodes formed on the mount cup is defined between the stays of the lead frame. The semiconductor light emitting device is characterized in that it is shorter than the distance between the electrodes on the p side and n side regardless of the shape and size of the lead frame. It has the effect that release can conduct also equipped with a short semiconductor light-emitting device.
[0016]
The invention according to claim 2 is the semiconductor light emitting device according to claim 1, wherein the mount cup is obtained by mixing a light-reflective filler in a synthetic resin of the material. Even if it exists, it has the effect | action that the light reflection by a filler can be utilized.
[0017]
Specific examples of embodiments of the present invention will be described below with reference to the drawings.
[0018]
FIG. 1 is a longitudinal sectional view showing a main part of a semiconductor light emitting device according to an embodiment of the present invention, and FIGS. 2 and 3 are a plan view and a bottom view of FIG. The semiconductor light emitting device is the same as that shown in FIG. 6, and the same constituent members are indicated by common reference numerals.
[0019]
In FIG. 1, stays 3a-1 and 3b-1 bent at right angles are provided at upper ends of a pair of leads 3a and 3b of a lead frame 3 whose base ends are conductively fixed to a printed wiring board (not shown) or the like. The mount cup 4 is formed and fixed to the upper surface of the stays 3a-1 and 3b-1, respectively.
[0020]
The lead frame 3 is formed in a bifurcated shape by integrating the tip side, that is, the stays 3a-1 and 3b-1 portions as in the conventional example, and the integrated portion is divided into the stays 3a-1 and 3b-1. The gap between them is the gap 3c. The opening width W of the gap 3c is about 0.4 mm in the current manufacturing technique.
[0021]
The mount cup 4 is made of, for example, a white liquid crystal polymer (LCP) and is formed into a mortar shape surrounding the semiconductor light emitting element 1. And in order to reflect the light which escapes from the semiconductor light emitting element 1 from the lower side and the side in the light emitting direction, a compound such as a light reflective compound such as TiO 2 is mixed as a filler.
[0022]
A pair of electrodes 5 and 6 for conducting the semiconductor light emitting element 1 and the lead frame 3 are provided on the bottom 4 a of the mount cup 4. These electrodes 5 and 6 are integrally sealed when the mold is manufactured together with the mount cup 4 mixed with the filler, and have a rectangular planar shape as shown in FIGS. That is, the electrodes 5 and 6 form element-side conductive portions 5a and 6a protruding above the bottom portion 4a at the central portion of the bottom portion 4a, and are exposed in the same plane as the lower surface of the bottom portion 4a. 6b.
[0023]
Here, since the electrodes 5 and 6 are integrally sealed when the mount cup 4 is molded with resin, by properly setting the positions of these electrodes 5 and 6 with respect to the mold for manufacturing, the electrodes 5 and 6 are placed between each other. The distance can be reduced. That is, as shown in FIG. 1, it is possible to mold the electrodes 5 and 6 so that the distance between the element-side conducting portions 5 a and 6 a is shorter than the opening width W of the gap 3 c of the lead frame 3. Therefore, even if the distance between the n-side and p-side bump electrodes 2a, 2b of the semiconductor light emitting element 1 is shorter than the opening width W of the gap 3c, for example, it can be mounted on the element-side conducting portions 5a, 6a.
[0024]
The mount cup 4 integrally including the electrodes 5 and 6 is mounted on the stays 3a-1 and 3b-1 of the leads 3a and 3b so as to have the positional relationship shown in FIGS. Then, by making the lead-side conductive portions 5b and 6b larger in plan shape than the stays 3a-1 and 3b-1, the stays 3a-1 and 3b-1 are connected to the lead-side conductive portions as shown in FIG. The parts 5 b and 6 b can be soldered 7, whereby the mount cup 4 is fixed to the lead frame 3 and at the same time conduction between the electrodes 5 and 6 and the leads 3 a and 3 b is obtained.
[0025]
By integrating the mount cup 4 with the lead frame 3 in this way, the electrodes 5 and 6 previously provided on the mount cup 4 are electrically connected to the leads 3a and 3b. Therefore, if the bump electrodes 2a and 2b are placed on the element-side conductive portions 5a and 6a and are subjected to ultrasonic pressure bonding and thermocompression bonding, they are bonded to mount the semiconductor light emitting element 1. In this mounting, the distance between the element-side conducting portions 5a and 6a is shorter than the gap 3c of the lead frame 3 as described above, so that the semiconductor light-emitting element 1 is small and the distance between the bump electrodes 2a and 2b. Can handle even narrower objects.
[0026]
Further, since the mount cup 4 is mixed with a highly light-reflective filler such as TiO 2, the light that passes from the semiconductor light emitting element 1 to the bottom 4a and the inner peripheral surface 4b side in FIG. The light can be collected by being reflected in the light emission direction from the light extraction surface. Therefore, even if the mount cup 4 is made of a synthetic resin, it is possible to improve the light emission luminance due to the reflected light.
[0027]
FIG. 4 is a plan view of the main part showing another example of the formation pattern of the electrodes 5 and 6 provided on the mount cup 4.
[0028]
In the illustrated example, the n-side and p-side electrode pads 1d and 1e are located in the diagonal direction within the plane outline of the semiconductor light emitting element 1, and therefore, the element-side conducting portions 5a and 6a of the electrodes 5 and 6 are used. Has a developed shape so as to include the bump electrodes 2a and 2b bonded to the electrode pads 1d and 1e. Thus, even if the arrangement and positional relationship of the p-side and n-side electrodes of the semiconductor light emitting device 1 are changed, it is only necessary to change the pattern in the mount cup 4 of the electrodes 5 and 6. It can also accommodate mounting of light emitting elements.
[0029]
【The invention's effect】
According to the first aspect of the present invention, when the electrodes are formed on the synthetic resin mount cup, the pattern can be freely formed, so the distance between the electrodes can be shortened, and the distance between the p-side and n-side electrodes is short. Even a semiconductor light emitting element can be assembled without any trouble, and further downsizing of the apparatus is further promoted.
[0030]
In the invention of claim 2, since a light reflecting function can be provided by mixing a light reflective filler in the mount cup, the light emission luminance is not lowered even if the mount cup is made of synthetic resin. .
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of a main part of a semiconductor light emitting device according to an embodiment of the present invention. FIG. 2 is a schematic plan view showing a positional relationship between an electrode pattern provided on a mount cup and a semiconductor light emitting element. 3] Schematic bottom view showing the positional relationship between the lead-side conductive portion of the electrode provided on the mount cup and the lead. [FIG. 4] Schematic plan view showing another example of the electrode pattern provided on the mount cup. [Fig. An example of an LED lamp provided with a semiconductor light emitting element of a type,
(A) is a longitudinal sectional view thereof (b) is a transverse sectional view thereof [FIG. 6] FIG. 6 is a longitudinal sectional view of a main part showing a structure for mounting a semiconductor light emitting element on a lead frame in a conventional example.
DESCRIPTION OF SYMBOLS 1 Semiconductor light emitting element 1a Substrate 1b N type layer 1c P type layer 1d N side electrode pad 1e P side electrode pad 2a, 2b Bump electrode 3 Lead frame 3a, 3b Lead 3a-1, 3b-1 Stay 3c Gap 4 Mount cup 4a Bottom part 4b Inner peripheral surface 5, 6 Electrodes 5a, 6a Element-side conduction parts 5b, 6b Lead-side conduction parts

Claims (2)

光透過性の基板の上に半導体薄膜層を積層するとともに、この積層膜の表面側にｐ側及びｎ側の電極をそれぞれ形成し、且つ前記基板側を主光取出し面とする半導体発光素子と、
前記ｐ側及びｎ側の電極にそれぞれ導通する一対の電極のパターンを一体に形成するとともに、前記半導体発光素子を搭載する合成樹脂製のマウントカップと、
一対のリードのそれぞれの先端に前記マウントカップを搭載し且つ前記一対の電極パターンにそれぞれ導通するステーを形成したリードフレームとを含み、
前記マウントカップに形成する一対の電極の間の間隔を前記リードフレームのステーどうしの間隔より短くしたことを特徴とする半導体発光装置。A semiconductor light-emitting element in which a semiconductor thin film layer is laminated on a light-transmitting substrate, p-side and n-side electrodes are formed on the surface side of the laminated film, and the substrate side is a main light extraction surface; ,
A synthetic resin mount cup on which the semiconductor light emitting element is mounted, and a pattern of a pair of electrodes respectively conducting to the p-side and n-side electrodes are integrally formed;
A lead frame on which the mount cup is mounted at each tip of a pair of leads and a stay that is electrically connected to each of the pair of electrode patterns is formed;
A semiconductor light emitting device characterized in that an interval between a pair of electrodes formed on the mount cup is shorter than an interval between stays of the lead frame. 前記マウントカップは、その素材の合成樹脂の中に光反射性のフィラーを混入したことを特徴とする請求項１記載の半導体発光装置。2. The semiconductor light emitting device according to claim 1, wherein a light reflective filler is mixed in the synthetic resin of the mount cup.
JP13227999A 1999-05-13 1999-05-13 Semiconductor light emitting device Expired - Fee Related JP4304760B2 (en)

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JP2002246650A (en) 2001-02-13 2002-08-30 Agilent Technologies Japan Ltd Light-emitting diode and its manufacturing method
US6874910B2 (en) 2001-04-12 2005-04-05 Matsushita Electric Works, Ltd. Light source device using LED, and method of producing same
JP4757477B2 (en) * 2004-11-04 2011-08-24 株式会社 日立ディスプレイズ Light source unit, illumination device using the same, and display device using the same
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