JP4300316B2 - Multilayer integrated circuit device - Google Patents

Multilayer integrated circuit device Download PDF

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JP4300316B2
JP4300316B2 JP2005038296A JP2005038296A JP4300316B2 JP 4300316 B2 JP4300316 B2 JP 4300316B2 JP 2005038296 A JP2005038296 A JP 2005038296A JP 2005038296 A JP2005038296 A JP 2005038296A JP 4300316 B2 JP4300316 B2 JP 4300316B2
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integrated circuit
heat flow
fine wiring
flow path
interposer
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JP2006228834A (en
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克弥 菊地
昌宏 青柳
博 仲川
和彦 所
義邦 岡田
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National Institute of Advanced Industrial Science and Technology AIST
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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Description

本願発明は、ＬＳＩ等の集積回路チップとインターポーザとを積層させた半導体装置である積層型集積回路装置に関するものである。   The present invention relates to a stacked integrated circuit device which is a semiconductor device in which an integrated circuit chip such as an LSI and an interposer are stacked.

上記の半導体装置に関して、本願発明の発明者等は既に、貫通電極を持つＬＳＩと微細配線構造を持つインターポーザとを交互に積層し、各ＬＳＩの間をインターポーザを介して配線するという３次元実装技術を提案しており（非特許文献１参照）、この実装技術に好適な高密度の微細配線インターポーザの作製方法も提案している（非特許文献２参照）。高密度微細配線構造は、第一のグランドプレーン、第一の絶縁層、信号線、第二の絶縁層、および第二のグランドプレーンを順に積層させたストリップライン構造により実現され、これにおいて第一絶縁層および第二絶縁層を感光性ポリイミドを用いて形成している。   With respect to the semiconductor device described above, the inventors of the present invention already have a three-dimensional mounting technique in which LSIs having through electrodes and interposers having a fine wiring structure are alternately stacked, and wiring between the LSIs is performed via the interposer. (See Non-Patent Document 1), and a method for manufacturing a high-density fine wiring interposer suitable for this mounting technique is also proposed (see Non-Patent Document 2). The high-density fine wiring structure is realized by a strip line structure in which a first ground plane, a first insulating layer, a signal line, a second insulating layer, and a second ground plane are sequentially stacked. The insulating layer and the second insulating layer are formed using photosensitive polyimide.

従来、図２に例示した、ＣＰＵやメモリなど個々のチップが挿入されたパッケージをプリント基板上に搭載してプリント配線でシステムを構築するＳｏＢ(System on Board)や、図３に例示した、ワンチップ上にシステムを構成する要素回路を全て集積するＳｏＣ(System on Chip)、図４に例示した、一つのパッケージの中に平面的あるいは立体的にＬＳＩチップを挿入してシステムを構築し、ワイヤーボンディングにより外部との接続を得るようにしたＳｉＰ(System in Package)が知られているが、上記本願発明の発明者等による実装技術は、集積回路チップを３次元に接続して実質的に１チップ程度の平面サイズに集積でき、これにより配線経路が縮小されて駆動電力が小さくなり、更に一層の小型化、低消費電力化、高機能化（高速、大容量）、低価格化を実現することのできる高密度実装技術として研究開発されたものである。   Conventionally, the SoB (System on Board) illustrated in FIG. 2 that builds a system with printed wiring by mounting a package in which individual chips such as a CPU and a memory are inserted on a printed circuit board, and the one illustrated in FIG. SoC (System on Chip) that integrates all the component circuits that make up the system on the chip, the system is constructed by inserting the LSI chip planarly or three-dimensionally into one package illustrated in FIG. A SiP (System in Package) is known in which connection to the outside is obtained by bonding. However, the mounting technique by the inventors of the present invention described above is substantially 1 by connecting integrated circuit chips in three dimensions. It can be integrated in a chip-like plane size, thereby reducing the wiring path and driving power, further miniaturization, low power consumption, high functionality (high speed, large capacity), and low price. It was researched and developed as a high-density packaging technology that can realize the above.

もちろん、本願発明の発明者等だけでなく、インターポーザや貫通電極を用いた積層型の半導体装置に関しては様々な研究開発が盛んに進められている（たとえば特許文献１〜４参照）。
”LSIの３次元実装を実現する超高速高密度インターポーザの開発に成功”，AIST Today，独立行政法人産業技術総合研究所，2003，Vol.3，No.12，pp.12-14(http://www.aist.go.jp/aist_j/aistinfo/aist_today/vol03_12/vol03_12_main.html) Katsuya Kikuchi et al., "Fabrication of High-Density WiringInterposer for 10 GHz 3D Packaging Using a Photosensitive MultiblockCopolymerized Polyimide", Japanese Journal of Applied Physics, 2004,Vol.43, No.7A, pp.4141-4145 特開２００４−２２８３９３号公報 特開２００４−２２６１０号公報 特開２００４−２１４２８６号公報 特開平１１−１４５３８１号公報 Of course, not only the inventors of the present invention, but also various research and developments are actively conducted on stacked semiconductor devices using interposers and through electrodes (for example, see Patent Documents 1 to 4).
“Succeeded in developing an ultra-high-speed and high-density interposer that realizes three-dimensional LSI mounting”, AIST Today, National Institute of Advanced Industrial Science and Technology, 2003, Vol. 3, No. 12, pp. 12-14 (http: //www.aist.go.jp/aist_j/aistinfo/aist_today/vol03_12/vol03_12_main.html) Katsuya Kikuchi et al., "Fabrication of High-Density WiringInterposer for 10 GHz 3D Packaging Using a Photosensitive Multiblock Copolymerized Polyimide", Japanese Journal of Applied Physics, 2004, Vol.43, No.7A, pp.4141-4145 JP 2004-228393 A JP 2004-22610 A JP 2004-214286 A JP-A-11-145381

ところで、上記実装技術においては、小さな立体スペースに多くの素子を集積することになるため、各素子で生じる発熱の対策を従来に増して考慮する必要がある。   By the way, in the above mounting technology, since many elements are integrated in a small three-dimensional space, it is necessary to consider countermeasures against heat generated in each element more than ever.

たとえば、上記特許文献２では、インターポーザを構成する電気絶縁材の素材を適当なものに選択することで、その熱伝導率を高くして、半導体や電子部品から発生する熱を電気絶縁材そのものによって放熱することが開示されている。   For example, in the above-mentioned Patent Document 2, by selecting an appropriate material for the electrical insulating material constituting the interposer, the thermal conductivity is increased, and the heat generated from the semiconductor or electronic component is caused by the electrical insulating material itself. Dissipating heat is disclosed.

上記特許文献３では、インターポーザに、ベタパターンやメッシュ状パターンの放熱用導体パターンと、これに接続させた放熱用スルーホールとを形成し、ＬＳＩチップで発生した熱を放熱用スルーホールを介して放熱用導体パターンへ伝達させて、放熱を促すことが開示されている。また、電源供給経路および電気信号経路である導体パターンに接続させてインターポーザに形成した導電用スルーホールを、放熱用スルーホールと同様に、放熱用導体パターンに接続させて、放熱経路としても機能させることが開示されている。   In Patent Document 3, a solid pattern or a mesh-shaped heat radiation conductor pattern and a heat radiation through hole connected to the interposer are formed, and heat generated in the LSI chip is transmitted through the heat radiation through hole. It is disclosed that the heat radiation is promoted by transmitting the heat radiation to the conductive pattern. In addition, the conductive through hole formed in the interposer connected to the conductor pattern that is the power supply path and the electric signal path is connected to the heat radiating conductor pattern in the same manner as the heat radiating through hole so as to function as a heat radiating path. It is disclosed.

上記特許文献４では、インターポーザに、その内部若しくは表裏面に形成された金属薄膜層およびこれに接続させたサーマルビアからなる放熱経路と、これにインターポーザの端面にて接続させたヒートシンクとを設け、半導体チップからの発熱を放熱経路を通じて逃がし、逃がした熱をヒートシンクを介して放熱することが開示されている。   In the above Patent Document 4, the interposer is provided with a heat radiation path composed of a metal thin film layer formed inside or on the front and back surfaces thereof and a thermal via connected thereto, and a heat sink connected to the end face of the interposer. It is disclosed that heat generated from a semiconductor chip is released through a heat dissipation path, and the released heat is dissipated through a heat sink.

上記特許文献１には、熱対策に関する開示は全くない。   The above-mentioned Patent Document 1 has no disclosure regarding heat countermeasures.

以上のとおりの事情に鑑み、本願発明は、これら従来の熱対策とは全く技術思想を異にした、集積回路チップをストリップライン構造を持つ微細配線インターポーザを介して互いに配線して積層させることで１チップサイズの立体集積構造を実現するとともに、この立体集積構造におけるより一層効果的な熱対策を実現することのできる積層型集積回路装置を提供することを課題としている。   In view of the circumstances as described above, the invention of the present application differs from these conventional thermal countermeasures in that the technical idea is completely different from each other by wiring and stacking integrated circuit chips via a fine wiring interposer having a stripline structure. It is an object of the present invention to provide a stacked integrated circuit device capable of realizing a one-chip size three-dimensionally integrated structure and realizing a more effective heat countermeasure in this three-dimensionally integrated structure.

本願発明は、上記の課題を解決するものとして、第１には、集積回路チップをストリップライン構造の微細配線インターポーザを介して積層させた積層型集積回路装置であって、集積回路チップおよび微細配線インターポーザは、積層時に互いに接続されて電源経路を形成するとともに集積回路チップにて発生した熱を装置内縦方向に流す縦方向熱流路を形成する電源経路・縦方向熱流路兼用の貫通電極を有しており、微細配線インターポーザはさらに、そのストリップライン構造を構成するグランドプレーンとして、前記電源経路・縦方向熱流路兼用の貫通電極に接続されて電気的アースを形成するとともに集積回路チップにて発生した熱を装置内横方向に流して前記縦方向熱流路に導く横方向熱流路を形成する電気的アース・横方向熱流路兼用のグランドプレーンを有していることを特徴とする。   In order to solve the above-described problems, the present invention provides a stacked integrated circuit device in which integrated circuit chips are stacked via a micro wiring interposer having a stripline structure. The interposer is connected to each other at the time of stacking to form a power supply path, and has a through-hole electrode that also serves as a power supply path / vertical heat flow path that forms a vertical heat flow path for flowing heat generated in the integrated circuit chip in the vertical direction in the device. Furthermore, the fine wiring interposer is connected to the power supply path / longitudinal heat passage through electrode as a ground plane constituting the strip line structure to form an electrical ground and is generated in the integrated circuit chip. Electrical grounding / transverse heat flow that forms a transverse heat flow path that guides the generated heat to the longitudinal heat flow path in the transverse direction in the apparatus Characterized in that it has a shared ground plane.

また、本願発明は、第２には、前記第１の積層型集積回路装置であって、冷却装置を備え、この冷却装置に集積回路チップまたは微細配線インターポーザの前記電源経路・縦方向熱流路兼用の貫通電極が接続されていることを特徴とする。   The second aspect of the present invention is the first stacked integrated circuit device according to the first aspect of the present invention, which includes a cooling device, and the cooling device also serves as the power supply path / vertical heat flow path of the integrated circuit chip or the fine wiring interposer. These through electrodes are connected.

また、本願発明は、第３には、前記第１の積層型集積回路装置であって、前記貫通電極を有する一枚若しくは複数枚の集積回路チップと前記貫通電極および前記グランドプレーンを有する一枚若しくは複数枚の微細配線インターポーザとを予め積層させてなる積層型集積回路モジュールを、複数個積み上げて構成されていることを特徴とする。   The third aspect of the present invention is the first multilayer integrated circuit device, wherein one or a plurality of integrated circuit chips having the through electrode, the through electrode, and the ground plane are provided. Alternatively, a plurality of stacked integrated circuit modules in which a plurality of fine wiring interposers are stacked in advance are stacked.

上記第１の発明によれば、集積回路チップおよび微細配線インターポーザに設けた上記貫通電極によって電源経路と縦方向熱流路が形成され、且つ、微細配線インターポーザのストリップライン構造を構成する上記グランドプレーンによって電気的アースと横方向熱流路が形成され、これにより、微細配線インターポーザを介した集積回路チップの１チップサイズでの３次元実装はそのままに、電気の流れと熱の流れを同時に実現した、つまり高速信号伝送と排熱を両立した積層型集積回路装置を提供することができる。しかも、熱の流れについては、装置内にて横方向から縦方向へと流れる経路を実現しており、より優れた排熱効果を実現している。   According to the first invention, a power path and a vertical heat flow path are formed by the through electrodes provided in the integrated circuit chip and the fine wiring interposer, and the ground plane constituting the strip line structure of the fine wiring interposer is used. An electrical ground and a lateral heat flow path are formed, which realizes a flow of electricity and a heat flow at the same time without changing the three-dimensional mounting of the integrated circuit chip through the fine wiring interposer. It is possible to provide a stacked integrated circuit device that achieves both high-speed signal transmission and exhaust heat. In addition, as for the heat flow, a path that flows from the horizontal direction to the vertical direction in the apparatus is realized, and a more excellent exhaust heat effect is realized.

上記第２の発明によれば、上記第１の発明と同様な効果が得られ、また、上記冷却装置によって上記貫通電極による縦方向熱流路を伝わってくる熱を外部に効果的に排出することができ、より一層の排熱効果且つ冷却効果を実現している。   According to the second invention, the same effect as the first invention can be obtained, and the heat transmitted through the vertical heat flow path by the through electrode can be effectively discharged to the outside by the cooling device. It is possible to achieve a further exhaust heat effect and cooling effect.

上記第３の発明によれば、上記第１の発明と同様な効果が得られ、また、予め集積回路チップ２と微細配線インターポーザ３を積層させてモジュール化した積層型集積回路モジュールを用意しておき、これを必要に応じて複数個積み上げていくことで、モジュール単位での積層型集積回路装置の構築が可能になる。これは、スタッカブルチップによるシステム集積技術（ＳＩＳＣ：System Integration by Stackable Chips）と呼ぶことができる。   According to the third aspect of the invention, the same effect as the first aspect of the invention can be obtained, and a laminated integrated circuit module in which the integrated circuit chip 2 and the fine wiring interposer 3 are laminated in advance to prepare a module is prepared. In addition, by stacking a plurality of these as necessary, it becomes possible to construct a stacked integrated circuit device in units of modules. This can be called system integration technology (SISSC: System Integration by Stackable Chips) using stackable chips.

［第一の実施形態］
図１は、上記のとおりの特徴を有する本願発明の一実施形態を示したものである。 [First embodiment]
FIG. 1 shows an embodiment of the present invention having the features as described above.

本実施形態の積層型集積回路装置１において、まず、ＬＳＩ等の集積回路チップ２は、電源経路・縦方向熱流路兼用の貫通電極２０と、信号配線用の貫通電極２１とを有している。   In the stacked integrated circuit device 1 of the present embodiment, first, an integrated circuit chip 2 such as an LSI has a through electrode 20 that also serves as a power supply path / vertical heat flow path and a through electrode 21 for signal wiring. .

電源経路・縦方向熱流路兼用の貫通電極２０は、導電性および伝熱性に優れた物質（たとえば銅や銀などの金属）で形成されて、集積回路チップ２を上下に貫通して設けられている。信号配線用の貫通電極２１は、従来と同様のものが用いられる。   The power supply path / longitudinal heat flow path penetration electrode 20 is formed of a material having excellent conductivity and heat conductivity (for example, a metal such as copper or silver), and is provided through the integrated circuit chip 2 in the vertical direction. Yes. As the through electrode 21 for signal wiring, the same one as the conventional one is used.

次に、ストリップライン構造を持つ微細配線インターポーザ３は、電源経路・縦方向熱流路兼用の貫通電極３０と、この貫通電極３０に接続された電気的アース・横方向熱流路兼用の第一、第二のグランドプレーン３１、３５とを有している。   Next, the fine wiring interposer 3 having a stripline structure includes a through electrode 30 serving both as a power supply path and a vertical heat flow path, and first and second electrical earth / transverse heat flow paths connected to the through electrode 30. And two ground planes 31 and 35.

電源経路・縦方向熱流路兼用の貫通電極３０は、導電性および伝熱性に優れた物質（たとえば銅や銀などの金属）で形成されて、微細配線インターポーザ３を上下に貫通して設けられている。また、上記集積回路チップ２の貫通電極２０とは貫通位置が揃っており、積層時に集積回路チップ２および微細配線インターポー３とを縦に貫く一本の貫通電極を構成するようになっている。これら貫通電極２０、３０は外部の電源アースＥに接続される。   The power supply path / longitudinal heat flow path penetrating electrode 30 is formed of a material having excellent conductivity and heat conductivity (for example, a metal such as copper or silver), and is provided through the fine wiring interposer 3 vertically. Yes. Further, the through-electrode 20 of the integrated circuit chip 2 is aligned with the through-hole 20 so as to constitute a single through-electrode that vertically penetrates the integrated circuit chip 2 and the fine wiring interposer 3 when stacked. . These through electrodes 20 and 30 are connected to an external power source ground E.

第一、第二のグランドプレーン３１、３５は、平板状またはメッシュ状（図１はメッシュ状）の導電性および伝熱性に優れた物質（たとえば銅や銀などの金属）で形成されて、第一の絶縁層３２と信号線３３と第二の絶縁層３４とによりストリップライン構造を形成している。また、このストリップライン構造を貫通している上記貫通電極３０とは電器および熱が伝わるように接触して接続されている。   The first and second ground planes 31 and 35 are formed of a plate-like or mesh-like material (FIG. 1 is a mesh-like) having excellent conductivity and heat conductivity (for example, a metal such as copper or silver). A strip line structure is formed by the one insulating layer 32, the signal line 33, and the second insulating layer 34. In addition, the through electrode 30 penetrating through the strip line structure is connected in contact with the electric and heat so as to be transmitted.

そして、これら集積回路チップ２と微細配線インターポーザ３が積層される際には、集積回路チップ２の信号配線用の貫通電極２１と微細配線インターポーザ３のストリップライン構造を構成する信号線３３とが接続されるとともに、集積回路チップ２の電源経路・縦方向熱流路兼用の貫通電極２０と微細配線インターポーザ３の電源経路・縦方向熱流路兼用の貫通電極３０とが接続される。   When the integrated circuit chip 2 and the fine wiring interposer 3 are stacked, the signal wiring through electrode 21 of the integrated circuit chip 2 and the signal line 33 constituting the strip line structure of the fine wiring interposer 3 are connected. In addition, the power supply path / vertical heat flow path through electrode 20 of the integrated circuit chip 2 is connected to the fine wiring interposer 3 power supply path / vertical heat flow path penetration electrode 30.

この貫通電極２１および信号線３３の接続によって、集積回路チップ２および微細配線インターポーザ３間の信号伝送路Ｓが形成され、その一方で、貫通電極２０および貫通電極３０の接続によって、微細配線インターポーザの第一、第二のグランドプレーン３１、３５から集積回路チップ２および微細配線インターポーザ３両方の貫通電極２０、３０を介して電源アースＥに延びる電源アース経路が形成されるとともに、貫通電極２０、３０による縦方向に延びる熱流路（「熱排出経路」とも呼べる）Ｖと、第一、第二のグランドプレーン３１、３５によるこの縦方向熱流路Ｖに連通した横方向に延びる熱流路Ｌとが形成される。なお、図１の実施形態では、集積回路チップ２は基板上に各素子が搭載されて構成されており、各素子からの熱はその上方に位置する微細配線インターポーザ３の第二のグランドプレーン３５により集熱されることとなるため、この第二のグランドプレーン３５が主に横方向熱流路Ｌを形成している。   The signal transmission path S between the integrated circuit chip 2 and the fine wiring interposer 3 is formed by the connection of the through electrode 21 and the signal line 33, while the connection of the through electrode 20 and the through electrode 30 of the fine wiring interposer is formed. A power supply ground path extending from the first and second ground planes 31 and 35 to the power supply ground E through the through electrodes 20 and 30 of both the integrated circuit chip 2 and the fine wiring interposer 3 is formed. A heat flow path V (which can also be referred to as a “heat exhaust path”) V and a heat flow path L extending in the horizontal direction connected to the vertical heat flow path V by the first and second ground planes 31 and 35 are formed. Is done. In the embodiment of FIG. 1, the integrated circuit chip 2 is configured by mounting each element on a substrate, and the heat from each element is the second ground plane 35 of the fine wiring interposer 3 located above the element. Therefore, the second ground plane 35 mainly forms the lateral heat flow path L.

これにより、従来と同様に微細配線インターポーザ３を介在させて信号配線且つ電源配線して積層させた集積回路チップ２の１チップサイズでの３次元実装はそのままに、それら集積回路チップ２および微細配線インターポーザ３を縦に貫く貫通電極２０、３０と微細配線インターザー３を横に走る第一、第二のグランドプレーン３１、３５とによる縦方向熱流路Ｖ、横方向熱流路Ｌが実現されることとなる。   As a result, the integrated circuit chip 2 and the fine wiring are arranged in the same one-chip size as the conventional integrated circuit chip 2 laminated with the signal wiring and the power supply wiring through the fine wiring interposer 3 as in the prior art. The vertical heat flow path V and the horizontal heat flow path L are realized by the through electrodes 20 and 30 penetrating the interposer 3 vertically and the first and second ground planes 31 and 35 running horizontally through the fine wiring interser 3. It becomes.

すなわち、各層の集積回路チップ２で発生した熱をその上層の微細配線インターポーザ３の第一、第二のグランドプレーン３１、３５により集熱して積層型集積回路装置１内を横方向に流して貫通電極２０、３０に集め（横方向熱流路Ｌ）、さらにその熱を各層を貫く貫通電極２０、３０により積層型集積回路装置１内を縦方向に流すことができ（縦方向熱流路Ｖ）、熱が各層間に溜まらずにスムーズに積層型集積回路装置１内を横方向から縦方向に排出されて、極めて優れた排熱効果を高速信号伝送と同時に実現できるのである。   That is, the heat generated in the integrated circuit chip 2 in each layer is collected by the first and second ground planes 31 and 35 of the fine wiring interposer 3 in the upper layer, and flows through the laminated integrated circuit device 1 in the lateral direction. The heat can be collected in the electrodes 20 and 30 (lateral heat flow path L), and the heat can be passed through the stacked integrated circuit device 1 in the vertical direction by the through electrodes 20 and 30 penetrating each layer (vertical heat flow path V). The heat is smoothly accumulated in the stacked integrated circuit device 1 from the horizontal direction to the vertical direction without accumulating between the layers, and an extremely excellent heat removal effect can be realized simultaneously with the high-speed signal transmission.

このときさらに、ヒートシンクや冷却フィンなどといった冷却装置４を設けて、冷却装置４に集積回路チップ２または微細配線インターポーザ３の電源経路・縦方向熱流路兼用の貫通電極２０、３０を接続させておくことで、これら貫通電極２０、３０の縦方向熱流路Ｖを伝わってくる熱をより効果的に外部に排出して、積層型集積回路装置１全体の冷却効果をさらに向上させることができる。図１の実施形態では、この冷却装置４としての冷却フィンが最上層の微細配線インターポーザ３上に設置され、貫通電極３０が接続されている。   At this time, a cooling device 4 such as a heat sink or a cooling fin is further provided, and the through-electrodes 20 and 30 that also serve as the power supply path / vertical heat flow path of the integrated circuit chip 2 or the fine wiring interposer 3 are connected to the cooling device 4. As a result, the heat transmitted through the vertical heat flow paths V of the through electrodes 20 and 30 can be more effectively discharged to the outside, and the cooling effect of the entire multilayer integrated circuit device 1 can be further improved. In the embodiment of FIG. 1, the cooling fins as the cooling device 4 are installed on the uppermost fine wiring interposer 3 and the through electrode 30 is connected.

［第二の実施形態］
以上の積層型集積回路装置１については、一枚もしくは複数枚の集積回路チップ２と一枚もしくは複数枚の微細配線インターポーザ３とを予め交互に積層させてモジュール化しておき、この積層型集積回路モジュール（「スタッカブルチップ」とも呼べる）を必要に応じて複数個積み上げることで幾層もの積層型集積回路装置１を構築する実施形態も可能である。 [Second Embodiment]
With respect to the stacked integrated circuit device 1 described above, one or a plurality of integrated circuit chips 2 and one or a plurality of fine wiring interposers 3 are alternately stacked in advance to form a module. An embodiment in which a plurality of stacked integrated circuit devices 1 are constructed by stacking a plurality of modules (also called “stackable chips”) as necessary is also possible.

この場合、各積層型集積回路モジュールの最上層を集積回路チップ２および最下層を微細配線インターポーザ３としておき、またはその逆としておき、積み上げ時に集積回路チップ２および微細配線インターポーザ３が交互に位置して、上記のとおりの高速信号伝送と排熱との両立が実現できるようにする。   In this case, the uppermost layer of each stacked type integrated circuit module is set as the integrated circuit chip 2 and the lowermost layer as the fine wiring interposer 3, or vice versa, and the integrated circuit chips 2 and the fine wiring interposer 3 are alternately positioned at the time of stacking. Thus, it is possible to realize both high-speed signal transmission and exhaust heat as described above.

本願発明の一実施形態について説明するための斜視図。The perspective view for demonstrating one Embodiment of this invention. 従来のＳｏＢについて説明するための図。The figure for demonstrating conventional SoB. 従来のＳｏＣについて説明するための図。The figure for demonstrating the conventional SoC. 従来のＳｉＰについて説明するための図。The figure for demonstrating the conventional SiP.

符号の説明Explanation of symbols

１ 積層型集積回路装置
２ 集積回路チップ
２０ 貫通電極
２１ 貫通電極
３ 微細配線インターポーザ
３０ 貫通電極
３１ 第一のグランドプレーン
３２ 第一の絶縁層
３３ 信号線
３４ 第二の絶縁層
３５ 第二のグランドプレーン
４ 冷却装置
Ｖ 縦方向熱流路
Ｌ 横方向熱流路
Ｓ 信号伝送路
Ｅ 電源アース

DESCRIPTION OF SYMBOLS 1 Stacked type integrated circuit device 2 Integrated circuit chip 20 Through electrode 21 Through electrode 3 Fine wiring interposer 30 Through electrode 31 First ground plane 32 First insulating layer 33 Signal line 34 Second insulating layer 35 Second ground plane 4 Cooling device V Longitudinal heat flow path L Horizontal heat flow path S Signal transmission line E Power supply ground

Claims (2)

集積回路チップをストリップライン構造の微細配線インターポーザを介して積層させた積層型集積回路装置であって、
集積回路チップおよび微細配線インターポーザは、積層時に互いに接続されて電源経路を形成するとともに集積回路チップにて発生した熱を装置内縦方向に流す縦方向熱流路を形成する電源経路・縦方向熱流路兼用の貫通電極を有しており、
微細配線インターポーザはさらに、そのストリップライン構造を構成するグランドプレーンとして、前記電源経路・縦方向熱流路兼用の貫通電極に接続されて電気的アースを形成するとともに集積回路チップにて発生した熱を装置内横方向に流して前記縦方向熱流路に導く横方向熱流路を形成する電気的アース・横方向熱流路兼用のグランドプレーンを有し、
冷却装置を備え、この冷却装置に集積回路チップまたは微細配線インターポーザの前記電源経路・縦方向熱流路兼用の貫通電極が接続されていることを特徴とする積層型集積回路装置。 A laminated integrated circuit device in which an integrated circuit chip is laminated through a fine wiring interposer having a stripline structure,
The integrated circuit chip and the fine wiring interposer are connected to each other at the time of stacking to form a power supply path and to form a vertical heat flow path for flowing heat generated in the integrated circuit chip in the vertical direction in the apparatus. It has a combined through electrode,
The fine wiring interposer is further connected to the power supply path / longitudinal heat flow path through electrode as a ground plane constituting the stripline structure to form an electrical ground and to generate heat generated in the integrated circuit chip. flushed with inner lateral possess electrical ground lateral heat flow path shared ground plane to form a transverse heat flow path for guiding the longitudinal heat flow path,
A laminated integrated circuit device comprising a cooling device, wherein the cooling device is connected to the integrated circuit chip or the through-electrode serving as the power path / vertical heat flow channel of the fine wiring interposer . 前記貫通電極を有する一枚若しくは複数枚の集積回路チップと前記貫通電極および前記グランドプレーンを有する一枚若しくは複数枚の微細配線インターポーザを予め積層させてなる積層型集積回路モジュールを、複数個積み上げて構成されていることを特徴とする請求項１記載の積層型集積回路装置。   Stacking a plurality of stacked integrated circuit modules in which one or a plurality of integrated circuit chips having the through electrodes and one or a plurality of fine wiring interposers having the through electrodes and the ground plane are stacked in advance. 2. The stacked integrated circuit device according to claim 1, wherein the stacked integrated circuit device is configured.
JP2005038296A 2005-02-15 2005-02-15 Multilayer integrated circuit device Expired - Fee Related JP4300316B2 (en)

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