JP4250617B2 - 不揮発性半導体記憶装置とその製造方法 - Google Patents
不揮発性半導体記憶装置とその製造方法 Download PDFInfo
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- JP4250617B2 JP4250617B2 JP2005168325A JP2005168325A JP4250617B2 JP 4250617 B2 JP4250617 B2 JP 4250617B2 JP 2005168325 A JP2005168325 A JP 2005168325A JP 2005168325 A JP2005168325 A JP 2005168325A JP 4250617 B2 JP4250617 B2 JP 4250617B2
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- insulating film
- gate electrode
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- floating gate
- conductive film
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- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 238000002955 isolation Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 229920005591 polysilicon Polymers 0.000 description 18
- 230000008878 coupling Effects 0.000 description 14
- 238000010168 coupling process Methods 0.000 description 14
- 238000005859 coupling reaction Methods 0.000 description 14
- 239000007772 electrode material Substances 0.000 description 12
- 230000004048 modification Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
Description
すなわち、カップリング容量に影響を与えるのは、浮遊ゲート電極と制御ゲート電極間に存在するゲート間絶縁膜の面積である。
W2>W1 …(2)
T1≒T2 …(3)
式(1)に示すように、第2の部分14−2の幅W2を第3の部分14−3の幅W3にゲート間絶縁膜15の膜厚Tipを加えた幅より広くすることにより、第2の部分14−2と第3の部分14−3との間に段差を形成することができる。また、第2、第3の部分14−2、41−3それぞれの膜厚T1、T2をほぼ等しくすることにより、第2、第3の部分14−2、14−3それぞれの膜厚T1、T2を、段差を形成しない場合における浮遊ゲート電極14の膜厚より薄くすることができる。
Claims (2)
- 半導体基板内に形成され、複数の溝と、前記溝内に形成され上面が前記半導体基板の表面より厚く設定された素子分離絶縁膜とからなる素子分離領域と、
前記素子分離領域相互間の前記半導体基板上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成された第1のゲート電極と、前記第1のゲート電極上に形成されたゲート間絶縁膜と、前記ゲート間絶縁膜上に形成された第2のゲート電極とを有する不揮発性半導体記憶装置であって、
前記第1のゲート電極は、素子分離絶縁膜相互間の第1の部分と、
前記第1の部分上で、一部が前記素子分離領域上に位置する第2の部分と、
前記第2の部分上の第3の部分を有し、
前記第3の部分の幅に前記ゲート間絶縁膜の膜厚を加えた幅は前記第2の部分の幅より狭く設定され、
前記素子分離絶縁膜は上面中央部に、前記第1のゲート電極の第2の部分の膜厚より低い突部を有し、前記突部の上面に前記ゲート間絶縁膜と前記第2のゲート電極が形成されていることを特徴とする不揮発性半導体記憶装置。 - 半導体基板上にゲート絶縁膜、第1の導電膜、第1の絶縁膜を順次形成し、
前記第1の絶縁膜をマスクとして、第1の導電膜、ゲート絶縁膜、半導体基板に所定間隔離間して複数の溝を形成し、
前記複数の溝内に素子分離領域としての第2の絶縁膜を形成し、
前記第2の絶縁膜の相互間の前記第1の絶縁膜を除去し、前記第1の導電膜上に第1の開口部を形成し、
前記第2絶縁膜を等方性エッチングによりエッチングし、前記第1の開口部の幅を前記第1の導電膜の第1の幅より広い第2の幅に広げ、
前記第1の開口部内に第2の導電膜を形成し、
前記第2の導電膜をエッチバックして前記第2の導電膜の膜厚を第1の膜厚に設定し、
全面に第3の絶縁膜を形成し、
前記第3の絶縁膜をエッチングして前記第1の開口部の側壁に前記第3の絶縁膜を残し、前記第2の導電膜上に第2の開口部を形成し、
前記第2の開口部内に第3の導電膜を形成し、
前記第3の導電膜の膜厚を前記第1の膜厚とほぼ同等の第2の膜厚に設定し、
前記第3の絶縁膜を除去するとともに、前記第2の絶縁膜を前記第1の導電膜の高さとほぼ同等の高さまでエッチバックし、
全面にゲート間絶縁膜としての第4の絶縁膜を形成し、
前記第4の絶縁膜上に第4の導電膜を形成し、
前記素子分離領域としての第2の絶縁膜の延長方向と直交方向に形成された複数のマスク材を用いて前記第4の導電膜をエッチングして制御ゲート電極を形成し、
前記複数のマスク材を用いて前記第4の絶縁膜をエッチングし、
前記複数のマスク材を用いて前記第3、第2、第1の導電膜をエッチングして浮遊ゲート電極を形成する
ことを特徴とする不揮発性半導体記憶装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005168325A JP4250617B2 (ja) | 2005-06-08 | 2005-06-08 | 不揮発性半導体記憶装置とその製造方法 |
US11/263,916 US7508026B2 (en) | 2005-06-08 | 2005-11-02 | Non-volatile semiconductor memory device having a two-layer gate electrode transistor and method of manufacturing the device |
KR1020060050817A KR100815305B1 (ko) | 2005-06-08 | 2006-06-07 | 2층 게이트 전극 트랜지스터를 구비한 불휘발성 반도체기억 장치 및 그 제조 방법 |
Applications Claiming Priority (1)
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JP2005168325A JP4250617B2 (ja) | 2005-06-08 | 2005-06-08 | 不揮発性半導体記憶装置とその製造方法 |
Publications (2)
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JP2006344733A JP2006344733A (ja) | 2006-12-21 |
JP4250617B2 true JP4250617B2 (ja) | 2009-04-08 |
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JP2005168325A Expired - Fee Related JP4250617B2 (ja) | 2005-06-08 | 2005-06-08 | 不揮発性半導体記憶装置とその製造方法 |
Country Status (3)
Country | Link |
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US (1) | US7508026B2 (ja) |
JP (1) | JP4250617B2 (ja) |
KR (1) | KR100815305B1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4250617B2 (ja) | 2005-06-08 | 2009-04-08 | 株式会社東芝 | 不揮発性半導体記憶装置とその製造方法 |
JP2007005380A (ja) * | 2005-06-21 | 2007-01-11 | Toshiba Corp | 半導体装置 |
JP4822841B2 (ja) * | 2005-12-28 | 2011-11-24 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
JP2008016777A (ja) * | 2006-07-10 | 2008-01-24 | Toshiba Corp | 半導体装置およびその製造方法 |
US7588982B2 (en) * | 2006-08-29 | 2009-09-15 | Micron Technology, Inc. | Methods of forming semiconductor constructions and flash memory cells |
US8809932B2 (en) * | 2007-03-26 | 2014-08-19 | Samsung Electronics Co., Ltd. | Semiconductor memory device, method of fabricating the same, and devices employing the semiconductor memory device |
US7888210B2 (en) * | 2007-12-19 | 2011-02-15 | Sandisk Corporation | Non-volatile memory fabrication and isolation for composite charge storage structures |
KR100940644B1 (ko) * | 2007-12-27 | 2010-02-05 | 주식회사 동부하이텍 | 반도체 소자 및 그 제조방법 |
JP2010147241A (ja) * | 2008-12-18 | 2010-07-01 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2010272675A (ja) * | 2009-05-21 | 2010-12-02 | Toshiba Corp | 半導体記憶装置 |
JP2010283127A (ja) * | 2009-06-04 | 2010-12-16 | Toshiba Corp | 半導体装置およびその製造方法 |
US8853796B2 (en) * | 2011-05-19 | 2014-10-07 | GLOBALFOUNDIERS Singapore Pte. Ltd. | High-K metal gate device |
US9287280B2 (en) * | 2014-07-09 | 2016-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to improve memory cell erasure |
US11937426B2 (en) | 2021-01-08 | 2024-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device and manufacturing method thereof |
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KR0179163B1 (ko) * | 1995-12-26 | 1999-03-20 | 문정환 | 비휘발성 메모리 셀 및 그 제조방법 |
JP3991383B2 (ja) | 1997-03-07 | 2007-10-17 | ソニー株式会社 | 半導体記憶装置及びその製造方法 |
US7029081B1 (en) * | 1998-10-27 | 2006-04-18 | Canon Kabushiki Kaisha | Head substrate having data memory, printing head, printing apparatus and producing method therefor |
KR100311049B1 (ko) * | 1999-12-13 | 2001-10-12 | 윤종용 | 불휘발성 반도체 메모리장치 및 그의 제조방법 |
JP2001196476A (ja) * | 2000-01-07 | 2001-07-19 | Toshiba Corp | 半導体装置及びその製造方法 |
TW531790B (en) * | 2000-09-26 | 2003-05-11 | Macronix Int Co Ltd | Method of forming conducting structure |
KR100389918B1 (ko) * | 2000-11-14 | 2003-07-04 | 삼성전자주식회사 | 빠른 프로그램 속도를 갖는 고집적 불활성 메모리 셀 어레이 |
JP2003031702A (ja) | 2001-07-16 | 2003-01-31 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置およびその製造方法 |
US6468862B1 (en) * | 2001-11-20 | 2002-10-22 | Vanguard International Semiconductor Corp. | High capacitive-coupling ratio of stacked-gate flash memory having high mechanical strength floating gate |
JP3914142B2 (ja) | 2002-11-29 | 2007-05-16 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
KR100520680B1 (ko) * | 2003-06-30 | 2005-10-11 | 주식회사 하이닉스반도체 | 플래시 메모리소자의 플로팅 게이트 및 그 형성방법 |
JP2005302872A (ja) * | 2004-04-08 | 2005-10-27 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP4761747B2 (ja) * | 2004-09-22 | 2011-08-31 | 株式会社東芝 | 半導体装置 |
JP4250617B2 (ja) | 2005-06-08 | 2009-04-08 | 株式会社東芝 | 不揮発性半導体記憶装置とその製造方法 |
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2005
- 2005-06-08 JP JP2005168325A patent/JP4250617B2/ja not_active Expired - Fee Related
- 2005-11-02 US US11/263,916 patent/US7508026B2/en not_active Expired - Fee Related
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2006
- 2006-06-07 KR KR1020060050817A patent/KR100815305B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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US7508026B2 (en) | 2009-03-24 |
KR100815305B1 (ko) | 2008-03-19 |
KR20060128675A (ko) | 2006-12-14 |
US20060278916A1 (en) | 2006-12-14 |
JP2006344733A (ja) | 2006-12-21 |
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