JP4249763B2 - コンピュータ・システム、及び、その性能・電力消費の管理をする方法 - Google Patents
コンピュータ・システム、及び、その性能・電力消費の管理をする方法 Download PDFInfo
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- JP4249763B2 JP4249763B2 JP2006158750A JP2006158750A JP4249763B2 JP 4249763 B2 JP4249763 B2 JP 4249763B2 JP 2006158750 A JP2006158750 A JP 2006158750A JP 2006158750 A JP2006158750 A JP 2006158750A JP 4249763 B2 JP4249763 B2 JP 4249763B2
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- 238000000034 method Methods 0.000 title claims description 4
- 230000001133 acceleration Effects 0.000 claims description 5
- 230000006870 function Effects 0.000 description 34
- 238000012545 processing Methods 0.000 description 10
- 239000013078 crystal Substances 0.000 description 9
- 230000010355 oscillation Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000002452 interceptive effect Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000013479 data entry Methods 0.000 description 1
- 238000012905 input function Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Executing Machine-Instructions (AREA)
- Power Sources (AREA)
- Microcomputers (AREA)
Description
本発明の他の目的は、コンピュータ・システム内のアプリケーション・プログラムが、プロセッサ集中的機能時にプロセッサの高性能モードを選択できるようにすることである。
本発明の他の目的は、コンピュータ・システム内のアプリケーション・プログラムが、非プロセッサ集中的機能時にプロセッサの電力保存モードを選択できるようにすることである。
本発明の他の目的は、コンピュータ・システムのユーザが、プロセッサの一組の性能モード時にプロセッサ・クロック周波数を選択できるようにすることである。
本発明の他の目的は、ユーザがプロセッサ集中的機能時にプロセッサ・クロック周波数を上げることができる加速ボタン図形インタフェースを提供することである。
本発明の他の目的、特徴および利点は、添付の図面および以下の詳細な説明から明らかとなろう。
Claims (2)
- クロック速度レジスタ(34)と、前記クロック速度レジスタによって決定された周波数のプロセッサ・クロツク信号(32)を発生する回路(32)とを有するクロック発生回路(14)を備え;
プロセッサ命令を記憶する記憶手段を備え;
前記クロック発生回路(14)に結合され、前記プロセッサ・クロック信号(32)を受信してそれに同期するプロセッサ(12)であって、前記記憶手段から性能マネージャ・プログラム(44)をフェッチして実行するプロセッサ(12)を備え、前記性能マネージャ・プログラム(44)によって、プロセッサの集中的機能状態の開始時には、一組のクロック周波数のうちの1つの値であって、前記プロセッサ(12)で実行されるアプリケーション・プログラム(50, 52)からのシステム・コールによって指定される高性能状態に対応しているクロック周波数値が、前記クロック速度レジスタ(34)に書込まれ、プロセッサの集中的機能状態の終了時には、一組のクロック周波数のうちの1つの値であって、前記プロセッサで実行されるアプリケーション・プログラム(50, 52)からのシステム・コールによって指定される低性能状態に対応しているクロック周波数値が、前記クロック速度レジスタ(34)に書込まれ、かかる前記クロック速度レジスタ(34)への書込みは、前記性能マネージャ・プログラム(44)から、基本入出力ソフトウェア(BIOS)のクロック発生ドライバ・プログラム(42)を呼び出すことによって、行われるものであり、前記高性能状態および前記低性能状態は、前記性能マネージャ・プログラム(44)により維持されている性能状態テーブル(56)からアプリケーション・プログラム(50, 52)によって選択されたものであり、前記性能状態テーブル(56)には、プロセッサの一組の性能状態に対応する一組のクロック周波数が格納されており、
前記プロセッサ(12)は、前記記憶手段から、前記プロセッサ(12)の性能状態に応じたクロック周波数のユーザによる選択を可能とする性能制御パネル・プログラムをフェッチして、実行できる、
ことを特徴とするコンピュータ・システム。 - コンピュータ・システムの性能および電力消費を管理するための方法であって、
クロック速度レジスタ(34)によって決定された周波数においてプロセッサ・クロック信号(32)を発生させるステップと;
前記コンピュータ・システムのプロセッサ(12)を前記プロセッサ・クロック信号(32)と同期させるステップと;
前記プロセッサ(12)の一組の性能状態に対応する一組のクロック周波数を、前記プロセッサ(12)により実行中の性能マネージャ・プログラム(44)によって維持されている性能状態テーブル(56)に、格納するステップと;
前記コンピュータ・システムで実行されている性能制御パネル・プログラムを用いて、前記プロセッサ(12)の性能状態に対応するクロック周波数を選択するステップと;
前記プロセッサ(12)の集中的機能状態の開始時に、一組のクロック周波数のうちの1つの値であって、アプリケーション・プログラム(50, 52)からのシステム・コールによって指定される高性能状態に対応しているクロック周波数値を、基本入出力ソフトウェア(BIOS)のクロック発生ドライバ・プログラム(42)を呼び出すことによって前記クロック速度レジスタ(34)に書き込むステップと;
前記プロセッサ(12)の集中的機能状態の終了時に、一組のクロック周波数のうちの1つの値であって、アプリケーション・プログラム(50, 52)からのシステム・コールによって指定される低性能状態に対応しているクロック周波数値を、前記クロック発生ドライバ・プログラム(42)を呼び出すことによって前記クロック速度レジスタ(34)に書き込むステップと、
ディスプレイ装置に加速ボタンを生じさせ、ユーザによって加速ボタンが選択されると、性能マネージャ・プログラム(44)が、プロセッサの高性能状態に対応しているクロック周波数値を、前記クロック速度レジスタ(34)に書き込むステップと
を備えることを特徴とする方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US26145794A | 1994-06-17 | 1994-06-17 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8502504A Division JPH10501911A (ja) | 1994-06-17 | 1995-06-14 | コンピュータ・システム内のプロセッサ性能と電力との動的管理 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006302306A JP2006302306A (ja) | 2006-11-02 |
JP4249763B2 true JP4249763B2 (ja) | 2009-04-08 |
Family
ID=22993393
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8502504A Withdrawn JPH10501911A (ja) | 1994-06-17 | 1995-06-14 | コンピュータ・システム内のプロセッサ性能と電力との動的管理 |
JP2006158750A Expired - Lifetime JP4249763B2 (ja) | 1994-06-17 | 2006-06-07 | コンピュータ・システム、及び、その性能・電力消費の管理をする方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8502504A Withdrawn JPH10501911A (ja) | 1994-06-17 | 1995-06-14 | コンピュータ・システム内のプロセッサ性能と電力との動的管理 |
Country Status (9)
Country | Link |
---|---|
US (1) | US5630148A (ja) |
EP (1) | EP0765499B1 (ja) |
JP (2) | JPH10501911A (ja) |
CN (1) | CN1118760C (ja) |
AU (1) | AU2903295A (ja) |
BR (1) | BR9508040A (ja) |
DE (1) | DE69524873T2 (ja) |
TW (1) | TW282525B (ja) |
WO (1) | WO1995035540A1 (ja) |
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-
1995
- 1995-05-06 TW TW084104521A patent/TW282525B/zh not_active IP Right Cessation
- 1995-06-14 EP EP95924599A patent/EP0765499B1/en not_active Expired - Lifetime
- 1995-06-14 CN CN95193635A patent/CN1118760C/zh not_active Expired - Lifetime
- 1995-06-14 WO PCT/US1995/007668 patent/WO1995035540A1/en active IP Right Grant
- 1995-06-14 JP JP8502504A patent/JPH10501911A/ja not_active Withdrawn
- 1995-06-14 DE DE69524873T patent/DE69524873T2/de not_active Expired - Lifetime
- 1995-06-14 BR BR9508040A patent/BR9508040A/pt not_active IP Right Cessation
- 1995-06-14 AU AU29032/95A patent/AU2903295A/en not_active Abandoned
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1996
- 1996-02-28 US US08/613,778 patent/US5630148A/en not_active Expired - Lifetime
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TW282525B (ja) | 1996-08-01 |
DE69524873T2 (de) | 2002-09-05 |
EP0765499A4 (en) | 1997-08-27 |
EP0765499A1 (en) | 1997-04-02 |
AU2903295A (en) | 1996-01-15 |
EP0765499B1 (en) | 2002-01-02 |
WO1995035540A1 (en) | 1995-12-28 |
CN1150845A (zh) | 1997-05-28 |
JP2006302306A (ja) | 2006-11-02 |
JPH10501911A (ja) | 1998-02-17 |
BR9508040A (pt) | 1997-11-18 |
US5630148A (en) | 1997-05-13 |
DE69524873D1 (de) | 2002-02-07 |
CN1118760C (zh) | 2003-08-20 |
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