JP4227681B2 - Nonvolatile semiconductor device manufacturing method - Google Patents

Nonvolatile semiconductor device manufacturing method Download PDF

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JP4227681B2
JP4227681B2 JP18289598A JP18289598A JP4227681B2 JP 4227681 B2 JP4227681 B2 JP 4227681B2 JP 18289598 A JP18289598 A JP 18289598A JP 18289598 A JP18289598 A JP 18289598A JP 4227681 B2 JP4227681 B2 JP 4227681B2
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JPH11297866A (en
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元 ▲虎▼ 朴
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

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Description

【０００１】
【発明の属する技術分野】
本発明は非揮発性半導体素子及びその製造方法に係るもので、詳しくはトランジスタの構造変更を通じて非揮発性メモリセルの高集積化を図り得る非揮発性半導体素子及びその製造方法に関する。
【０００２】
【従来の技術】
非揮発性半導体素子は電気的にデータの消去と貯蔵が可能であり、電源が供給されなくてもデータの保存が可能であるという特長を有するので、最近多様な分野でその使用範囲が拡大している。
【０００３】
このような非揮発性半導体素子はメモリセルアレイの構造に従い大きくNAND型とNOR 型に区分され、これらは高集積化と高速性に大別されるそれぞれの長所と短所を有していて、多様な所でその使用が増加しつつある。
【０００４】
この中で、本発明と直接的に関連するNOR 型非揮発性半導体素子は、一つのビットラインに多数のメモリセルトランジスタが並列に接続され、ビットラインに接続されるドレインとソースライン間に一つのセルトランジスタだけが接続されるようになっていて、メモリセルの電流が増大し高速動作が可能であるという特徴を有する反面、ビットラインにメモリセルが並列に接続されているため、選択されたセルを読むとき共通ビットラインの隣接したセルが過剰に消去されて、メモリセルトランジスタのVth が非選択セルの第２ゲート電極に印加される電圧（例えば、０Ｖ）よりも低くなると、選択セルのオン、オフに係わらず電流が流れて全てのセルがオンセルに読まれるという誤動作が発生することが知られている。
【０００５】
そこで、最近、誤動作発生を構造的に解決するため、非揮発性半導体素子のメモリセル製造時ドレインとソースライン間に一つのトランジスタを追加形成して、二つのトランジスタで一つのメモリセルを構成するようにしている。
【０００６】
図９乃至図１６は、従来のNOR 型非揮発性半導体素子の製造方法を示す工程断面図であって、以下、その製造方法を詳しく説明する。
図９に示すように、半導体基板10上の所定部分にフィールド酸化膜12を形成して非活性領域と活性領域を区分する。
図９及び図１０に示すように、半導体基板10の活性領域上にゲート絶縁膜14を形成し、このゲート絶縁膜14の表面の所定部分が露出されるようにゲート絶縁膜14上に感光膜パターン16を形成した後、表面が露出したゲート絶縁膜14を介して不純物をイオン注入して基板10内に第１接合領域18a を形成する。
【０００７】
図１１に示すように、感光膜パターン16を除去し、第１接合領域18a 上の基板10表面の所定部分が露出されるようにゲート絶縁膜14を選択食刻した後、該食刻部分にゲート絶縁膜14よりも薄い厚さのトンネル絶縁膜20を形成する。その結果、中央部に形成されたトンネル絶縁膜20がその周りに形成されたゲート絶縁膜14により囲まれる構造のパターンが形成される。
【０００８】
図１２に示すように、フィールド酸化膜12とトンネル絶縁膜20を含めたゲート絶縁膜14上にポリシリコン材質の第１導電性膜22を形成する。
図１３に示すように、第１導電性膜22全面に層間絶縁膜24を形成し、セルとセル間のフローティングゲート分離のためフィールド酸化膜12表面の所定部分が露出されるように図示しない縦方向（図面上で紙面を突き抜ける方向）の所定部分の層間絶縁膜24と第１導電性膜22を選択食刻する。参照符号A には、理解を助けるため層間絶縁膜24と第１導電性膜22の所定部分が食刻処理された状態で、図１３の一点鎖線で囲んだ部分の平面図を示す。
【０００９】
図１４に示すように、フィールド酸化膜12の表面露出部を含めた層間絶縁膜24上にポリシリコン材質の第２導電性膜26を形成する。
図１５に示すように、酸化膜を食刻マスクとしてゲート絶縁膜14の表面所定部分が露出されるように第２導電性膜26、層間絶縁膜24、及び第１導電性膜22を選択食刻する。その結果、トンネル絶縁膜20と第１接合領域18a の形成された部分の基板10上には層間絶縁膜24を介して第１導電性膜材質のフローティングゲート22a と第２導電性膜材質のコントロールゲート26a が積層される構造のセンストランジスタＴ１が形成され、その一側の半導体基板10上には層間絶縁膜24を介して第１導電性膜材質のフローティングゲート22b と第２導電性膜材質のコントロールゲート26b が積層される構造のセレクトトランジスタＴ２が形成される。
【００１０】
図１６に示すように、ゲート絶縁膜14の表面露出部を介して不純物をイオン注入して、第１接合領域18a と隣接する部分の基板10内部にはセレクトトランジスタＴ２と一部がオーバーラップするように第２接合領域18b を形成し、センストランジスタＴ１の一側の基板10内部にはソース領域28を形成し、セレクトトランジスタＴ２の一側の基板10内部にはドレイン領域30を形成する。以上で全工程が終了する。
【００１１】
その結果、フィールド酸化膜12の形成された半導体基板10上の活性領域には基板10表面の所定部分が露出されるようにゲート絶縁膜14が形成され、該ゲート絶縁膜14間の表面の露出した基板10上には前記ゲート絶縁膜14よりも薄い厚さのトンネル絶縁膜20が形成され、このトンネル絶縁膜20とその周りのゲート絶縁膜14上の所定部分には層間絶縁膜24を介してフローティングゲート22a とコントロールゲート26a が積層される構造のセンストランジスタＴ１が形成され、このセンストランジスタＴ１の一側の前記ゲート絶縁膜14上の所定部分にはセンストランジスタＴ１と同様な積層構造のセレクトトランジスタＴ２が形成され、トンネル絶縁膜20下方の基板10内部には第１接合領域18a が形成され、該第１接合領域18a の一側にはセレクトトランジスタＴ２と一部がオーバーラップされるように第２接合領域18b が形成され、フィールド酸化膜12とセンストランジスタＴ１間の領域の基板10内部にはソース領域28が形成され、フィールド酸化膜12とセレクトトランジスタＴ２間の領域の基板10内部にはビットラインと接続されるドレイン領域30が形成された構造の非揮発性半導体素子が完成する。
【００１２】
従って、この構造の非揮発性半導体素子はデータの貯蔵、消去、及び判読作業と関連した一連の動作が次のような方法により行われる。この場合、データの貯蔵と関連する除去(erase) 及びデータの消去と関連するプログラム（又はライト）はFNトンネル(fowler-nordheim tunnel) 方式により行われる。以下、詳しく説明する。
【００１３】
まず、除去の場合に対して説明する。センストランジスタＴ１のコントロールゲート26a に高電圧（例えば16V ）を印加し、ドレイン領域30と接続されたビットラインを接地した状態でトランジスタを選択的にオンさせる役割を担当するセレクトトランジスタＴ２のコントロールゲート26b に高電圧（例えば16V)を印加してセンストランジスタＴ１のコントロールゲート26a とビットライン間に強い電界を供給すると、トンネル絶縁膜20の障壁が薄くなり、ソース領域28とドレイン領域30間に形成されたチャンネルを通じてビットラインから電子がトンネル絶縁膜20を通じてFNトンネル方式によりセンストランジスタＴ１のフローティングゲート22a 内に注入される。その結果、除去が行われてプログラムされたセルにデータが記録される。このようにフローティングゲート22a に電子が充填されると、この電子によりメモリセルのしきい値電圧（以下Vth と称する) が上がり、ワードラインと接続されたコントロールゲート26a に電源電圧を供給してセルを読むと、高いしきい値電圧によりチャンネルが形成されなくて電流が流れないので、一つの状態を記憶するようになる。
【００１４】
次いで、新しい情報を貯蔵するためにプログラムをしようとする場合に対して説明する。センストランジスタＴ１のコントロールゲート26a を接地させドレイン領域30と接続されるビットラインに高電圧（例えば16V ）を印加した状態で、トランジスタを選択的にオンさせる役割を担当するセレクトトランジスタＴ２のコントロールゲート26b に高電圧（例えば16V ）を印加してセンストランジスタＴ１のフローティングゲート22a と基板10間のトンネル絶縁膜20の両端に強い電界を供給すると、トンネル絶縁膜20の障壁が薄くなってFNトンネル方式によりフローティングゲート22a 内に貯蔵された電荷が薄くなった絶縁膜障壁を透過して、一度に第１，第２接合領域18a,18b を経て基板10内部のドレイン領域30側に抜け出る。その結果、データのプログラムが行われる。このようになると、フローティングゲート22a 内に電荷がなくてセルのVth が低くなるから、ワードラインと接続されたコントロールゲート26a に電源電圧を印加してセルを読むと、低いVth によりチャンネルが形成されて電流が流れることにより、初期とは異なる状態を記憶させることができる。
即ち、データの判読が選択セルのビットラインとコントロールゲートに適正電圧を印加してメモリセルトランジスタの電流の有無を判読する方式からなることを確認できる。
【００１５】
【発明が解決しようとする課題】
しかるに、上記のような従来の構造および製造方法では、一つのメモリセルに二つのトランジスタが所定間隔に並んで形成されて非揮発性素子が構成されるため、既存素子に比べて単位セルの面積が大きくなる問題点があった。したがって、スマートカードICに内蔵されて量産される製品のチップサイズ縮小に限界があって、半導体素子の高集積化を図り得ないという問題がある。
このような問題は、通常NOR 型の非揮発性半導体素子はメモリセルの電流が大きく高速動作ができるという特長を有するが、ビットラインコンタクトとソースラインが占める面積の増大によりメモリ素子の高集積化が難しいという短所を有することを勘案すると、一層大きな問題になる。したがって、これに対する改善策が至急に要求されている。
【００１６】
本発明の目的は、センストランジスタとセレクトトランジスタとを有するメモリセルの構造変形を通じて非揮発性素子の単位セル面積を最小化させて、メモリセルの高集積化を実現できる非揮発性半導体素子を提供することにある。
本発明の他の目的は、前記非揮発性半導体素子を効果的に製造できる非揮発性半導体素子の製造方法を提供することにある。
【００１７】
【課題を解決するための手段】
本発明の非揮発性半導体素子は、半導体基板上の所定部分に形成されたトンネル絶縁膜と、このトンネル絶縁膜と接するようにその周りの前記基板上の所定部分に形成された第１ゲート絶縁膜と、前記トンネル絶縁膜と第１ゲート絶縁膜上に形成され、層間絶縁膜を介してフローティングゲートとコントロールゲートが積層される構造のセンストランジスタと、前記コントロールゲート上に形成された任意膜と、この任意膜を含めたセンストランジスタの側壁に形成されたスペーサと、このスペーサの周りの基板上に形成された第２ゲート絶縁膜と、前記任意膜上の一側エッジ部とスペーサを含めた前記第２ゲート絶縁膜上の所定部分に亙って形成されたセレクトゲートと、このセレクトゲートと所定部分がオーバーラップされるように前記トンネル絶縁膜下方の基板内部に形成された接合領域と、前記センストランジスタとセレクトトランジスタとして作用する前記セレクトゲート両端の基板内部に形成されたソース領域及びドレイン領域とからなることを特徴とする。
【００１８】
本発明の非揮発性半導体素子の製造方法は、フィールド酸化膜が形成された半導体基板の活性領域上に第１ゲート絶縁膜を形成する工程と、前記第１ゲート絶縁膜所定部分下部の前記基板内に接合領域を形成する工程と、前記接合領域が形成された部分の前記基板表面が露出されるように第１ゲート絶縁膜を選択食刻し、その表面露出部にトンネル絶縁膜を形成する工程と、前記トンネル絶縁膜を含めた前記第１ゲート絶縁膜上に第１導電性膜と層間絶縁膜を順次形成する工程と、前記フィールド酸化膜の所定部分の表面が露出されるように前記層間絶縁膜と第１導電性膜の所定部分を選択食刻する工程と、前記フィールド酸化膜の表面露出部を含めた前記層間絶縁膜上に第２導電性膜を形成する工程と、前記第２導電性膜上の所定部分に任意膜を形成する工程と、前記任意膜をマスクとして前記第２導電性膜、層間絶縁膜、第１導電性膜、及び第１ゲート絶縁膜を順次食刻して層間絶縁膜を介してその上下部にコントロールゲートとフローティングゲートが積層される構造のセンストランジスタを形成する工程と、前記任意膜を含めた前記センストランジスタの両側壁にスペーサを形成する工程と、前記スペーサの周りの前記基板上に第２ゲート絶縁膜を形成する工程と、前記任意膜上の一側エッジ部とスペーサを含めた第２ゲート絶縁膜上の所定部分に亙って第３導電性膜材質のセレクトゲートを形成する工程と、前記センストランジスタとセレクトトランジスタとして作用する前記セレクトゲート両端の基板内部にソース領域とドレイン領域を形成する工程とからなることを特徴とする。
【００１９】
上記のような本発明によれば、絶縁膜（任意膜とスペーサ）を媒介体としてセンストランジスタの上端と側面に直接セレクトトランジスタが重なって形成される構造となるので、非揮発性半導体素子の単位セル面積を最小化できる。また、そのようにして単位セル面積を最小化できる非揮発性半導体素子を効果的に製造できる。
【００２０】
【発明の実施の形態】
以下、本発明の実施の形態を説明する。
本発明はセンストランジスタとセレクトトランジスタを有する非揮発性メモリセルの構造変更を通じて非揮発性半導体素子の単位セル面積を最小化できるようにした技術であって、図１乃至図８に示した工程断面図を参照して詳しく説明する。
【００２１】
図１に示すように、半導体基板100 上の所定部分にフィールド酸化膜102 を形成して非活性領域と活性領域を区分する。
図１および図２に示すように、基板100 の活性領域上に250 〜350 Å厚さの第１ゲート絶縁膜104 を酸化膜で形成し、該ゲート絶縁膜104 の表面の所定部分が露出されるようにゲート絶縁膜104 上に感光膜パターン106 を形成した後、表面が露出したゲート絶縁膜104 を介して不純物をイオン注入して基板100 内の所定部分に接合領域108 を形成する。
【００２２】
図３に示すように、感光膜パターン106 を除去し、新たに図示しない感光膜パターンを形成した後、これをマスクとして、接合領域108 上の基板100 表面所定部分が露出されるように第１ゲート絶縁膜104 を湿式食刻し、図示しない感光膜パターンを除去する。次いで、第１ゲート絶縁膜104 が食刻された部分の基板100 表面に70〜100 Å厚さのトンネル絶縁膜110 を酸化膜で形成する。その結果、中央部に形成されたトンネル絶縁膜110 がその周りに形成された第１ゲート絶縁膜104 により包囲される構造のパターンが形成される。
【００２３】
図４に示すように、フィールド酸化膜102 とトンネル絶縁膜110 を含めた第１ゲート絶縁膜104 上にポリシリコン材質の第１導電性膜112 と層間絶縁膜114 を順次形成した後、セルとセル間のフローティングゲート分離のためフィールド酸化膜102 表面の所定部分が露出されるように図示しない縦方向（図面上で紙面を突き抜ける方向）の所定部分の層間絶縁膜114 と第１導電性膜112 を選択食刻する。参照符号A には理解を助けるため層間絶縁膜114 と第１導電性膜112 の所定部分が食刻処理された状態で、図４の一点鎖線で囲んだ部分の平面図を示す。このとき、層間絶縁膜114 としては酸化膜の単層構造あるいは酸化膜／窒化膜／酸化膜の多層構造のいずれをも適用可能である。
【００２４】
図５に示すように、フィールド酸化膜102 の表面露出部を含めた層間絶縁膜114 上にポリシリコン材質の第２導電性膜116 と酸化膜材質の任意膜118 を順次形成し、その上にセンストランジスタ形成部を限定する感光膜パターン130 を形成した後、これをマスクとして任意膜118 を食刻する。次いで、前記感光膜パターン130 と任意膜118 を食刻マスクとして第２導電性膜116 、層間絶縁膜114 、第１導電性膜112 及び第１ゲート絶縁膜104 を順次食刻する。その結果、トンネル絶縁膜110 と第１ゲート絶縁膜104 上には層間絶縁膜114 を介して第１導電性膜材質のフローティングゲート112aと第２導電性膜材質のコントロールゲート116aが積層される構造のセンストランジスタＴ１１が形成され、その左右の基板100 表面は露出される。このように酸化膜材質の任意膜118 をマスクとしてセンストランジスタＴ１１を形成することは食刻工程の正確性を図るためである。この場合、前記第２導電性膜116 としてはポリシリコンの単層構造以外にポリシリコン／Ｗ−シリサイドの多層構造を適用可能である。
【００２５】
図６に示すように、感光膜パターン130 を除去し、任意膜118 とセンストランジスタＴ１１を含めた基板100 上の全面に酸化膜或いは窒化膜材質の絶縁膜を形成した後、この絶縁膜をエッチバックする。その結果、任意膜118 とセンストランジスタＴ１１の側壁に絶縁膜材質のスペーサ120 が形成される。
【００２６】
図７に示すように、スペーサ120 の周りの基板100 表面露出部に酸化工程によって第２ゲート絶縁膜122 を形成する。その後、基板100 上の全面にポリシリコン材質の第３導電性膜124 を形成した後、この第３導電性膜124 上にセレクトトランジスタ形成部を限定する感光膜パターン（図示せず）を形成し、これをマスクとして第３導電性膜124 を食刻する。その結果、任意膜118 上の一側エッジ部とスペーサ120 を含めた第２ゲート絶縁膜122 上の所定部分に亙って第３導電性膜材質のセレクトゲート124aが形成される。この場合も前記第３導電性膜としてはポリシリコンの単層構造以外にポリシリコン／Ｗ−シリサイドの多層構造を適用可能である。
【００２７】
図８に示すように、第２ゲート絶縁膜112 の露出部部分を介して不純物をイオン注入して、センストランジスタＴ１１とセレクトトランジスタＴ１２として作用するセレクトゲート124a両端の基板100 内部にソース領域126 とドレイン領域128 を形成し、全工程を完了する。
【００２８】
その結果、フィールド酸化膜120 が形成された半導体基板100 の活性領域の所定部分にはトンネル絶縁膜110 が形成され、その周りの活性領域所定部分にはトンネル絶縁膜110 と接するように第１ゲート絶縁膜104 が形成され、トンネル絶縁膜110 と第１ゲート絶縁膜104 上には層間絶縁膜114 を介して第１導電性膜材質のフローティングゲート112aと第２導電性膜材質のコントロールゲート116aが順次積層される構造のセンストランジスタＴ１１が形成され、コントロールゲート116a上には任意膜118 が形成され、任意膜118 とセンストランジスタＴ１１の側壁には絶縁膜材質のスペーサ120 が形成され、スペーサ120 近くの活性領域には第２ゲート絶縁膜122 が形成され、任意膜118 上端の一側エッジ部とスペーサ120 を含めた第２ゲート絶縁膜122 上の所定部分に亙って第３導電性膜材質のセレクトゲート124aが形成され、トンネル絶縁膜110 下部の基板100 内部にはセレクトゲート124aと所定部分がオーバーラップされるように接合領域108 が形成され、センストランジスタＴ１１とセレクトトランジスタＴ１２として作用するセレクトゲート124a両端の基板100 内部にはソース領域126 とドレイン領域128 が形成される構造の非揮発性半導体素子が完成する。
【００２９】
この構造の非揮発性メモリセルの場合は、センストランジスタＴ１１とセレクトトランジスタＴ１２が重なった形態を有するので、従来よりも単位セル面積を減らすことができる。
【００３０】
【発明の効果】
以上説明したように本発明によれば、任意膜とスペーサを媒介体としてセンストランジスタの上端エッジ側と側面を含めた第２ゲート絶縁膜上の所定部分に亙ってセレクトトランジスタが形成されて、センストランジスタとセレクトトランジスタが重なった構造となるので、センストランジスタとセレクトトランジスタが所定間隔だけ離隔して形成された従来の場合と比べて、基板上でこれらトランジスタが占める面積を減らすことができ、従って、単位セル面積を最小化することができて非揮発性半導体素子の高集積化を図ることが可能となる。また、そのようにして高集積化が可能な非揮発性半導体素子を効果的に製造できる。
【図面の簡単な説明】
【図１】本発明による非揮発性半導体素子の製造方法の実施の形態を示す工程断面図。
【図２】本発明による非揮発性半導体素子の製造方法の実施の形態を示す工程断面図。
【図３】本発明による非揮発性半導体素子の製造方法の実施の形態を示す工程断面図。
【図４】本発明による非揮発性半導体素子の製造方法の実施の形態を示す工程断面図。
【図５】本発明による非揮発性半導体素子の製造方法の実施の形態を示す工程断面図。
【図６】本発明による非揮発性半導体素子の製造方法の実施の形態を示す工程断面図。
【図７】本発明による非揮発性半導体素子の製造方法の実施の形態を示す工程断面図。
【図８】本発明による非揮発性半導体素子の製造方法の実施の形態を示す工程断面図。
【図９】従来の非揮発性半導体素子の製造方法を示す工程断面図。
【図１０】従来の非揮発性半導体素子の製造方法を示す工程断面図。
【図１１】従来の非揮発性半導体素子の製造方法を示す工程断面図。
【図１２】従来の非揮発性半導体素子の製造方法を示す工程断面図。
【図１３】従来の非揮発性半導体素子の製造方法を示す工程断面図。
【図１４】従来の非揮発性半導体素子の製造方法を示す工程断面図。
【図１５】従来の非揮発性半導体素子の製造方法を示す工程断面図。
【図１６】従来の非揮発性半導体素子の製造方法を示す工程断面図。
【符号の説明】
１００ 半導体基板
１０２ フィールド酸化膜
１０４ 第１ゲート絶縁膜
１０８ 接合領域
１１０ トンネル絶縁膜
１１２ａ フローティングゲート
１１４ 層間絶縁膜
１１６ａ コントロールゲート
１１８ 任意膜
１２０ スペーサ
１２２ 第２ゲート絶縁膜
１２４ａ セレクトゲート
１２６ ソース領域
１２８ ドレイン領域
Ｔ１１ センストランジスタ
Ｔ１２ セレクトトランジスタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor device and a method for manufacturing the same, and more particularly to a non-volatile semiconductor device capable of achieving high integration of non-volatile memory cells through a transistor structure change and a method for manufacturing the same.
[0002]
[Prior art]
Nonvolatile semiconductor devices have the feature that data can be erased and stored electrically, and data can be stored even when power is not supplied, so the range of use has recently expanded in various fields. ing.
[0003]
Such non-volatile semiconductor devices are roughly divided into NAND type and NOR type according to the structure of the memory cell array, and these have various advantages and disadvantages that can be roughly divided into high integration and high speed. However, its use is increasing.
[0004]
Among these, the NOR type nonvolatile semiconductor device directly related to the present invention has a large number of memory cell transistors connected in parallel to one bit line, and one drain line and one source line connected to the bit line. Only one cell transistor is connected, and it has the feature that the current of the memory cell increases and high speed operation is possible, but it is selected because the memory cell is connected in parallel to the bit line When the cell adjacent to the common bit line is excessively erased when the cell is read and the Vth of the memory cell transistor becomes lower than the voltage (for example, 0V) applied to the second gate electrode of the non-selected cell, It is known that a malfunction occurs in which all cells are read as on-cells regardless of whether they are on or off.
[0005]
Therefore, recently, in order to structurally solve the occurrence of malfunction, one transistor is additionally formed between the drain and the source line at the time of manufacturing the memory cell of the nonvolatile semiconductor element, and one memory cell is constituted by two transistors. I am doing so.
[0006]
9 to 16 are process cross-sectional views showing a conventional method for manufacturing a NOR-type non-volatile semiconductor device. The manufacturing method will be described in detail below.
As shown in FIG. 9, a field oxide film 12 is formed in a predetermined portion on the semiconductor substrate 10 to separate the inactive region from the active region.
As shown in FIGS. 9 and 10, a gate insulating film 14 is formed on the active region of the semiconductor substrate 10, and a photosensitive film is formed on the gate insulating film 14 so that a predetermined portion of the surface of the gate insulating film 14 is exposed. After the pattern 16 is formed, impurities are ion-implanted through the gate insulating film 14 whose surface is exposed to form a first junction region 18a in the substrate 10.
[0007]
As shown in FIG. 11, after the photosensitive film pattern 16 is removed and the gate insulating film 14 is selectively etched so that a predetermined portion of the surface of the substrate 10 on the first bonding region 18a is exposed, the etched portion is formed on the etched portion. A tunnel insulating film 20 having a thickness smaller than that of the gate insulating film 14 is formed. As a result, a pattern having a structure in which the tunnel insulating film 20 formed in the central portion is surrounded by the gate insulating film 14 formed therearound is formed.
[0008]
As shown in FIG. 12, a first conductive film 22 made of polysilicon is formed on the gate insulating film 14 including the field oxide film 12 and the tunnel insulating film 20.
As shown in FIG. 13, an interlayer insulating film 24 is formed on the entire surface of the first conductive film 22, and a vertical portion (not shown) is exposed so that a predetermined portion of the surface of the field oxide film 12 is exposed for the floating gate isolation between the cells. A predetermined portion of the interlayer insulating film 24 and the first conductive film 22 are selectively etched in a direction (a direction penetrating the paper surface in the drawing). Reference numeral A 1 shows a plan view of a portion surrounded by an alternate long and short dash line in FIG. 13 in a state in which predetermined portions of the interlayer insulating film 24 and the first conductive film 22 are etched to help understanding.
[0009]
As shown in FIG. 14, a second conductive film 26 made of polysilicon is formed on the interlayer insulating film 24 including the surface exposed portion of the field oxide film 12.
As shown in FIG. 15, the second conductive film 26, the interlayer insulating film 24, and the first conductive film 22 are selectively etched so that a predetermined portion of the surface of the gate insulating film 14 is exposed using the oxide film as an etching mask. Engrave. As a result, the floating gate 22a of the first conductive film material and the control of the second conductive film material are formed on the substrate 10 where the tunnel insulating film 20 and the first junction region 18a are formed via the interlayer insulating film 24. A sense transistor T1 having a structure in which a gate 26a is stacked is formed, and a floating gate 22b made of a first conductive film material and a second conductive film material are formed on a semiconductor substrate 10 on one side via an interlayer insulating film 24. A select transistor T2 having a structure in which the control gate 26b is stacked is formed.
[0010]
As shown in FIG. 16, impurities are ion-implanted through the exposed surface of the gate insulating film 14, and the select transistor T2 partially overlaps the substrate 10 in a portion adjacent to the first junction region 18a. Thus, the second junction region 18b is formed, the source region 28 is formed inside the substrate 10 on one side of the sense transistor T1, and the drain region 30 is formed inside the substrate 10 on one side of the select transistor T2. The entire process is thus completed.
[0011]
As a result, the gate insulating film 14 is formed in the active region on the semiconductor substrate 10 on which the field oxide film 12 is formed so that a predetermined portion of the surface of the substrate 10 is exposed, and the surface between the gate insulating films 14 is exposed. A tunnel insulating film 20 having a thickness smaller than that of the gate insulating film 14 is formed on the substrate 10, and a predetermined portion on the tunnel insulating film 20 and the surrounding gate insulating film 14 is provided with an interlayer insulating film 24 interposed therebetween. Thus, a sense transistor T1 having a structure in which a floating gate 22a and a control gate 26a are stacked is formed, and a select portion having a stacked structure similar to the sense transistor T1 is formed on a predetermined portion on the gate insulating film 14 on one side of the sense transistor T1. A transistor T2 is formed, a first junction region 18a is formed in the substrate 10 below the tunnel insulating film 20, and a select transistor T is formed on one side of the first junction region 18a. The second junction region 18b is formed so as to partially overlap the source region 28, and the source region 28 is formed in the substrate 10 in the region between the field oxide film 12 and the sense transistor T1, and the field oxide film 12 and the select transistor A nonvolatile semiconductor device having a structure in which a drain region 30 connected to a bit line is formed inside the substrate 10 in a region between T2 is completed.
[0012]
Accordingly, the nonvolatile semiconductor device having this structure is subjected to a series of operations related to data storage, erasure, and interpretation by the following method. In this case, the erase associated with the storage of data and the program (or write) associated with the erasure of data are performed by the FN tunnel (fowler-nordheim tunnel) method. This will be described in detail below.
[0013]
First, the case of removal will be described. The control gate 26b of the select transistor T2 in charge of selectively turning on the transistor while applying a high voltage (for example, 16V) to the control gate 26a of the sense transistor T1 and grounding the bit line connected to the drain region 30 When a high voltage (for example, 16V) is applied to the transistor to supply a strong electric field between the control gate 26a of the sense transistor T1 and the bit line, the barrier of the tunnel insulating film 20 is thinned and formed between the source region 28 and the drain region 30. Through the channel, electrons are injected from the bit line through the tunnel insulating film 20 into the floating gate 22a of the sense transistor T1 by the FN tunnel method. As a result, removal is performed and data is recorded in the programmed cells. When electrons are filled in the floating gate 22a in this way, the threshold voltage (hereinafter referred to as Vth) of the memory cell rises due to the electrons, and a power supply voltage is supplied to the control gate 26a connected to the word line to supply the cell. Is read, a channel is not formed due to a high threshold voltage and no current flows, so that one state is memorized.
[0014]
Next, the case where a program is intended to store new information will be described. The control gate 26b of the select transistor T2 in charge of selectively turning on the transistor in a state in which the control gate 26a of the sense transistor T1 is grounded and a high voltage (for example, 16V) is applied to the bit line connected to the drain region 30. When a strong electric field is applied to both ends of the tunnel insulating film 20 between the floating gate 22a of the sense transistor T1 and the substrate 10 by applying a high voltage (for example, 16V) to the tunnel 10, the barrier of the tunnel insulating film 20 becomes thin and the FN tunnel method is applied. The charges stored in the floating gate 22a pass through the insulating film barrier in which the charge is reduced, and escape to the drain region 30 side in the substrate 10 through the first and second junction regions 18a and 18b at a time. As a result, data programming is performed. In this case, there is no charge in the floating gate 22a and the Vth of the cell is lowered.Therefore, when a cell is read by applying a power supply voltage to the control gate 26a connected to the word line, a channel is formed by the low Vth. As a result, a state different from the initial state can be stored.
That is, it can be confirmed that the reading of data consists of a method in which an appropriate voltage is applied to the bit line and the control gate of the selected cell to read the presence / absence of the current of the memory cell transistor.
[0015]
[Problems to be solved by the invention]
However, in the conventional structure and manufacturing method as described above, a non-volatile element is formed by forming two transistors in a memory cell at a predetermined interval. There was a problem that increased. Therefore, there is a limit to reducing the chip size of products that are built in smart card ICs and mass-produced, and there is a problem that high integration of semiconductor elements cannot be achieved.
The problem is that NOR-type non-volatile semiconductor devices usually have a large memory cell current and can operate at high speed. However, the increase in the area occupied by bit line contacts and source lines increases the integration of memory devices. Considering the disadvantage of being difficult, it becomes a bigger problem. Therefore, there is an urgent need for improvement measures.
[0016]
An object of the present invention is to provide a non-volatile semiconductor device capable of realizing high integration of a memory cell by minimizing a unit cell area of the non-volatile device through structural modification of a memory cell having a sense transistor and a select transistor. There is to do.
Another object of the present invention is to provide a method for manufacturing a non-volatile semiconductor device capable of effectively manufacturing the non-volatile semiconductor device.
[0017]
[Means for Solving the Problems]
The nonvolatile semiconductor device of the present invention includes a tunnel insulating film formed in a predetermined portion on a semiconductor substrate, and a first gate insulating formed in the predetermined portion on the substrate surrounding the tunnel insulating film so as to be in contact with the tunnel insulating film. A sense transistor having a structure in which a floating gate and a control gate are stacked via an interlayer insulating film, and an arbitrary film formed on the control gate, and a film formed on the tunnel insulating film and the first gate insulating film. A spacer formed on the side wall of the sense transistor including the arbitrary film, a second gate insulating film formed on the substrate around the spacer, a one-side edge portion on the arbitrary film, and the spacer A select gate formed over a predetermined portion on the second gate insulating film, and the select gate and the predetermined portion overlap each other. A junction region formed in the substrate of the tunnel insulating film downward, characterized by comprising the said sense transistor and the select gate across the source and drain regions formed in the substrate of which acts as a select transistor.
[0018]
According to another aspect of the present invention, there is provided a non-volatile semiconductor device manufacturing method comprising: forming a first gate insulating film on an active region of a semiconductor substrate on which a field oxide film is formed; and the substrate under a predetermined portion of the first gate insulating film. Forming a junction region therein, and selectively etching the first gate insulating film so as to expose the surface of the substrate in a portion where the junction region is formed, and forming a tunnel insulating film on the surface exposed portion A step of sequentially forming a first conductive film and an interlayer insulating film on the first gate insulating film including the tunnel insulating film, and the surface of a predetermined portion of the field oxide film is exposed. Selectively etching a predetermined portion of the interlayer insulating film and the first conductive film, forming a second conductive film on the interlayer insulating film including the surface exposed portion of the field oxide film, 2 Assign to a predetermined part on the conductive film Forming a film, and sequentially etching the second conductive film, the interlayer insulating film, the first conductive film, and the first gate insulating film using the arbitrary film as a mask, and the upper and lower sides thereof through the interlayer insulating film Forming a sense transistor having a structure in which a control gate and a floating gate are stacked in a part, forming a spacer on both side walls of the sense transistor including the arbitrary film, and on the substrate around the spacer A select gate made of a third conductive film material is formed over a predetermined portion on the second gate insulating film including the step of forming the second gate insulating film and the one side edge on the arbitrary film and the spacer. And forming a source region and a drain region inside the substrate at both ends of the select gate that acts as the sense transistor and the select transistor. And butterflies.
[0019]
According to the present invention as described above, since the select transistor is directly formed on the upper end and the side surface of the sense transistor with the insulating film (arbitrary film and spacer) as a medium, the unit of the nonvolatile semiconductor element Cell area can be minimized. In addition, a non-volatile semiconductor element that can minimize the unit cell area can be effectively manufactured.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
The present invention is a technique for minimizing a unit cell area of a nonvolatile semiconductor element through a structural change of a nonvolatile memory cell having a sense transistor and a select transistor, and is a process cross section shown in FIGS. This will be described in detail with reference to the drawings.
[0021]
As shown in FIG. 1, a field oxide film 102 is formed in a predetermined portion on the semiconductor substrate 100 to separate the inactive region and the active region.
As shown in FIGS. 1 and 2, a first gate insulating film 104 having a thickness of 250 to 350 mm is formed on the active region of the substrate 100 with an oxide film, and a predetermined portion of the surface of the gate insulating film 104 is exposed. After the photosensitive film pattern 106 is formed on the gate insulating film 104 as described above, impurities are ion-implanted through the gate insulating film 104 whose surface is exposed to form a junction region 108 at a predetermined portion in the substrate 100.
[0022]
As shown in FIG. 3, after the photosensitive film pattern 106 is removed and a new photosensitive film pattern (not shown) is formed, this is used as a mask so that a predetermined portion of the surface of the substrate 100 on the bonding region 108 is exposed. The gate insulating film 104 is wet etched to remove a photosensitive film pattern (not shown). Next, a tunnel insulating film 110 having a thickness of 70 to 100 mm is formed of an oxide film on the surface of the substrate 100 where the first gate insulating film 104 is etched. As a result, a pattern having a structure in which the tunnel insulating film 110 formed in the central portion is surrounded by the first gate insulating film 104 formed therearound is formed.
[0023]
As shown in FIG. 4, after a first conductive film 112 made of polysilicon and an interlayer insulating film 114 are sequentially formed on the first gate insulating film 104 including the field oxide film 102 and the tunnel insulating film 110, the cell and A predetermined portion of the interlayer insulating film 114 and the first conductive film 112 in a vertical direction (direction penetrating the paper surface in the drawing) not shown so that a predetermined portion of the surface of the field oxide film 102 is exposed for floating gate separation between cells. Select to engrave. Reference numeral A 1 shows a plan view of a portion surrounded by an alternate long and short dash line in FIG. 4 in a state in which predetermined portions of the interlayer insulating film 114 and the first conductive film 112 have been etched. At this time, as the interlayer insulating film 114, either a single layer structure of oxide film or a multilayer structure of oxide film / nitride film / oxide film can be applied.
[0024]
As shown in FIG. 5, a second conductive film 116 made of a polysilicon material and an optional film 118 made of an oxide film material are sequentially formed on the interlayer insulating film 114 including the surface exposed portion of the field oxide film 102, After forming a photosensitive film pattern 130 for limiting the sense transistor formation portion, the optional film 118 is etched using this pattern as a mask. Next, the second conductive film 116, the interlayer insulating film 114, the first conductive film 112, and the first gate insulating film 104 are sequentially etched using the photosensitive film pattern 130 and the optional film 118 as an etching mask. As a result, the floating gate 112a made of the first conductive film material and the control gate 116a made of the second conductive film material are stacked on the tunnel insulating film 110 and the first gate insulating film 104 via the interlayer insulating film 114. Sense transistor T11 is formed, and the surfaces of the left and right substrates 100 are exposed. The reason why the sense transistor T11 is formed using the optional film 118 made of an oxide film as a mask is to improve the accuracy of the etching process. In this case, as the second conductive film 116, a multi-layer structure of polysilicon / W-silicide can be applied in addition to the single-layer structure of polysilicon.
[0025]
As shown in FIG. 6, after the photosensitive film pattern 130 is removed and an insulating film made of an oxide film or a nitride film is formed on the entire surface of the substrate 100 including the optional film 118 and the sense transistor T11, the insulating film is etched. Back. As a result, a spacer 120 made of an insulating film is formed on the arbitrary film 118 and the side walls of the sense transistor T11.
[0026]
As shown in FIG. 7, a second gate insulating film 122 is formed on the exposed surface of the substrate 100 around the spacer 120 by an oxidation process. Thereafter, a third conductive film 124 made of polysilicon is formed on the entire surface of the substrate 100, and then a photosensitive film pattern (not shown) for limiting a select transistor forming portion is formed on the third conductive film 124. The third conductive film 124 is etched using this as a mask. As a result, a select gate 124a made of the third conductive film material is formed over a predetermined portion on the second gate insulating film 122 including the one side edge portion on the arbitrary film 118 and the spacer 120. Also in this case, as the third conductive film, a multilayer structure of polysilicon / W-silicide can be applied in addition to the single layer structure of polysilicon.
[0027]
As shown in FIG. 8, impurities are ion-implanted through the exposed portion of the second gate insulating film 112, and source regions 126 and 126 are formed inside the substrate 100 at both ends of the select gate 124a acting as the sense transistor T11 and the select transistor T12. A drain region 128 is formed and the entire process is completed.
[0028]
As a result, the tunnel insulating film 110 is formed in a predetermined portion of the active region of the semiconductor substrate 100 on which the field oxide film 120 is formed, and the first gate is in contact with the predetermined portion of the active region around it. An insulating film 104 is formed, and a floating gate 112a made of a first conductive film material and a control gate 116a made of a second conductive film material are formed on the tunnel insulating film 110 and the first gate insulating film 104 via an interlayer insulating film 114. A sense transistor T11 having a structure of being sequentially stacked is formed, an arbitrary film 118 is formed on the control gate 116a, and a spacer 120 made of an insulating film is formed on the side wall of the arbitrary film 118 and the sense transistor T11. A second gate insulating film 122 is formed in the active region of the gate electrode, and is formed on a predetermined portion on the second gate insulating film 122 including the one side edge portion of the upper end of the arbitrary film 118 and the spacer 120. Then, a select gate 124a made of the third conductive film material is formed, and a junction region 108 is formed in the substrate 100 below the tunnel insulating film 110 so as to overlap a predetermined portion with the select gate 124a. A nonvolatile semiconductor element having a structure in which a source region 126 and a drain region 128 are formed in the substrate 100 at both ends of the select gate 124a acting as the T11 and the select transistor T12 is completed.
[0029]
The nonvolatile memory cell having this structure has a configuration in which the sense transistor T11 and the select transistor T12 overlap with each other, so that the unit cell area can be reduced as compared with the conventional case.
[0030]
【The invention's effect】
As described above, according to the present invention, the select transistor is formed over a predetermined portion on the second gate insulating film including the upper edge side and the side surface of the sense transistor using the arbitrary film and the spacer as a medium, Since the sense transistor and the select transistor overlap each other, the area occupied by these transistors on the substrate can be reduced as compared with the conventional case where the sense transistor and the select transistor are separated by a predetermined distance. Therefore, the unit cell area can be minimized, and high integration of the nonvolatile semiconductor element can be achieved. In addition, it is possible to effectively manufacture a non-volatile semiconductor element that can be highly integrated.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view showing an embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
FIG. 2 is a process sectional view showing an embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
FIG. 3 is a process cross-sectional view illustrating an embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
FIG. 4 is a process sectional view showing an embodiment of a method for manufacturing a nonvolatile semiconductor element according to the present invention.
FIG. 5 is a process sectional view showing an embodiment of a method for manufacturing a nonvolatile semiconductor element according to the present invention.
FIG. 6 is a process sectional view showing an embodiment of a method for manufacturing a nonvolatile semiconductor element according to the present invention.
FIG. 7 is a process cross-sectional view showing an embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
FIG. 8 is a process cross-sectional view illustrating an embodiment of a method for manufacturing a nonvolatile semiconductor device according to the present invention.
FIG. 9 is a process cross-sectional view illustrating a conventional method for manufacturing a nonvolatile semiconductor element.
FIG. 10 is a process cross-sectional view illustrating a conventional method for manufacturing a nonvolatile semiconductor element.
FIG. 11 is a process cross-sectional view illustrating a conventional method for manufacturing a nonvolatile semiconductor element.
FIG. 12 is a process cross-sectional view illustrating a conventional method for manufacturing a nonvolatile semiconductor element.
FIG. 13 is a process cross-sectional view illustrating a conventional method for manufacturing a nonvolatile semiconductor element.
FIG. 14 is a process cross-sectional view illustrating a conventional method for manufacturing a nonvolatile semiconductor element.
FIG. 15 is a process cross-sectional view illustrating a conventional method for manufacturing a nonvolatile semiconductor element.
FIG. 16 is a process cross-sectional view illustrating a conventional method for manufacturing a nonvolatile semiconductor element.
[Explanation of symbols]
100 Semiconductor substrate 102 Field oxide film 104 First gate insulating film 108 Junction region 110 Tunnel insulating film 112a Floating gate 114 Interlayer insulating film 116a Control gate 118 Arbitrary film 120 Spacer 122 Second gate insulating film 124a Select gate 126 Source region 128 Drain region T11 Sense transistor T12 Select transistor

Claims (9)

フィールド酸化膜が形成された半導体基板の活性領域上に第１ゲート絶縁膜を形成する工程と、
前記第１ゲート絶縁膜所定部分下部の前記基板内に接合領域を形成する工程と、
前記接合領域が形成された部分の前記基板表面が露出されるように第１ゲート絶縁膜を選択食刻し、その表面露出部にトンネル絶縁膜を形成する工程と、
前記トンネル絶縁膜を含めた前記第１ゲート絶縁膜上に第１導電性膜と層間絶縁膜を順次形成する工程と、
前記フィールド酸化膜の所定部分の表面が露出されるように前記層間絶縁膜と第１導電性膜の所定部分を選択食刻する工程と、
前記フィールド酸化膜の表面露出部を含めた前記層間絶縁膜上に第２導電性膜を形成する工程と、
前記第２導電性膜上に、センストランジスタ形成部を限定するように任意膜を形成する工程と、
前記任意膜をマスクとして前記第２導電性膜、層間絶縁膜、第１導電性膜、及び第１ゲート絶縁膜を順次食刻して層間絶縁膜を介してその上下部にコントロールゲートとフローティングゲートが積層される構造のセンストランジスタを形成する工程と、
前記任意膜を含めた前記センストランジスタの両側壁にスペーサを形成する工程と、
前記スペーサの周りの前記基板上に第２ゲート絶縁膜を形成する工程と、
前記任意膜上の一側エッジ部とスペーサを含めた第２ゲート絶縁膜上の所定部分に亙って第３導電性膜材質のセレクトゲートを形成する工程と、
前記センストランジスタとセレクトトランジスタとして作用する前記セレクトゲート両端の基板内部にソース領域とドレイン領域を形成する工程と
からなることを特徴とする非揮発性半導体素子の製造方法。Forming a first gate insulating film on the active region of the semiconductor substrate on which the field oxide film is formed;
Forming a junction region in the substrate below a predetermined portion of the first gate insulating film;
Selectively etching the first gate insulating film so that the substrate surface of the portion where the junction region is formed is exposed, and forming a tunnel insulating film on the surface exposed portion;
Sequentially forming a first conductive film and an interlayer insulating film on the first gate insulating film including the tunnel insulating film;
Selectively etching the interlayer insulating film and the predetermined portion of the first conductive film such that the surface of the predetermined portion of the field oxide film is exposed;
Forming a second conductive film on the interlayer insulating film including the exposed surface portion of the field oxide film;
Forming an arbitrary film on the second conductive film so as to limit a sense transistor formation portion ;
The second conductive film, the interlayer insulating film, the first conductive film, and the first gate insulating film are sequentially etched using the arbitrary film as a mask, and a control gate and a floating gate are formed above and below the interlayer insulating film. Forming a sense transistor having a structure in which are stacked,
Forming spacers on both side walls of the sense transistor including the arbitrary film;
Forming a second gate insulating film on the substrate around the spacer;
Forming a select gate made of a third conductive film material over a predetermined portion on the second gate insulating film including the one side edge portion on the arbitrary film and the spacer;
A method for manufacturing a non-volatile semiconductor device, comprising: forming a source region and a drain region in a substrate at both ends of the select gate that acts as the sense transistor and the select transistor. 前記第１ゲート絶縁膜は、250 〜350 Å厚さの酸化膜で形成することを特徴とする請求項１に記載の非揮発性半導体素子の製造方法。The first gate insulating film, a manufacturing method of the nonvolatile semiconductor device according to claim 1, characterized in that formed in the oxide film of 250 to 350 Å thick. 前記トンネル絶縁膜は、70〜100 Å厚さの酸化膜で形成することを特徴とする請求項１に記載の非揮発性半導体素子の製造方法。The method for manufacturing a non-volatile semiconductor device according to claim 1 , wherein the tunnel insulating film is formed of an oxide film having a thickness of 70 to 100 mm. 前記層間絶縁膜は、酸化膜の単層構造或いは酸化膜／窒化膜／酸化膜の多層構造で形成することを特徴とする請求項１に記載の非揮発性半導体素子の製造方法。2. The method of manufacturing a nonvolatile semiconductor device according to claim 1 , wherein the interlayer insulating film is formed with a single layer structure of an oxide film or a multilayer structure of an oxide film / nitride film / oxide film. 前記第２及び第３導電性膜は、ポリシリコンの単層構造或いはポリシリコン／Ｗ−シリサイドの多層構造で形成することを特徴とする請求項１に記載の非揮発性半導体素子の製造方法。2. The method of manufacturing a nonvolatile semiconductor device according to claim 1 , wherein the second and third conductive films are formed of a single layer structure of polysilicon or a multilayer structure of polysilicon / W-silicide. 前記任意膜は、酸化膜で形成することを特徴とする請求項１に記載の非揮発性半導体素子の製造方法。The method for manufacturing a nonvolatile semiconductor device according to claim 1 , wherein the arbitrary film is formed of an oxide film. 前記任意膜を含めた前記センストランジスタの両側壁にスペーサを形成する工程は、前記任意膜とセンストランジスタを含めた前記基板全面に所定厚さの絶縁膜を形成する工程と、前記絶縁膜をエッチバックする工程と
からなることを特徴とする請求項１に記載の非揮発性半導体素子の製造方法。The step of forming spacers on both side walls of the sense transistor including the arbitrary film includes the step of forming an insulating film having a predetermined thickness on the entire surface of the substrate including the arbitrary film and the sense transistor, and etching the insulating film. The method for manufacturing a non-volatile semiconductor device according to claim 1 , further comprising a step of backing. 前記絶縁膜は、酸化膜或いは窒化膜で形成することを特徴とする請求項７に記載の非揮発性半導体素子の製造方法。8. The method of manufacturing a nonvolatile semiconductor device according to claim 7 , wherein the insulating film is formed of an oxide film or a nitride film. 前記第２ゲート絶縁膜は、酸化工程により形成することを特徴とする請求項１に記載の非揮発性半導体素子の製造方法。The method of claim 1 , wherein the second gate insulating film is formed by an oxidation process.
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