JP4223455B2

JP4223455B2 - Susceptor

Info

Publication number: JP4223455B2
Application number: JP2004285280A
Authority: JP
Inventors: 雅也横川
Original assignee: Covalent Materials Corp
Current assignee: Coorstek KK
Priority date: 2004-03-23
Filing date: 2004-09-29
Publication date: 2009-02-12
Anticipated expiration: 2024-09-29
Also published as: JP2005311290A

Description

本発明はサセプタに係り、特にウェーハポケットに被覆されるＳｉＣ被膜の一部に研磨されないＳｉＣ結晶成長面部を残したサセプタに関する。 The present invention relates to a susceptor, and more particularly, to a susceptor in which a SiC crystal growth surface portion that is not polished is left on a part of an SiC film coated on a wafer pocket.

半導体デバイスは多くの製造工程を経て製造されるが、半導体ウェーハのエピタキシャル成長工程等に使用されるサセプタは、低反応性、高強度のために炭素基材にＳｉＣを被覆したＳｉＣ部材が多く用いられている。 Semiconductor devices are manufactured through many manufacturing processes. However, susceptors used in the epitaxial growth process of semiconductor wafers are often made of SiC members with SiC coated on a carbon substrate for low reactivity and high strength. ing.

サセプタは平板状のサセプタ基材に１個のウェーハ収納用の凹部が形成された枚葉式サセプタや多数の凹部が形成されたサセプタがある。 As the susceptor, there are a single-wafer type susceptor in which one concave portion for housing a wafer is formed on a flat susceptor base material and a susceptor in which a large number of concave portions are formed.

これらのサセプタは、機械研削等によって凹部が形成された炭素基材にＳｉＣを被覆して製造し、被覆した状態のまま熱処理等に用いるか（特許文献１）、あるいはこのＳｉＣ被覆面をさらに研磨装置により研磨して製造し、これを熱処理等に用いていた（特許文献２）。 These susceptors are manufactured by coating SiC on a carbon base material having recesses formed by mechanical grinding or the like, and are used for heat treatment or the like with the coated state (Patent Document 1) or further polishing this SiC coated surface. It was manufactured by polishing with an apparatus and used for heat treatment or the like (Patent Document 2).

しかし、従来の製造方法で製造されたサセプタは、特許文献１のようにＳｉＣ被膜を被覆した状態のまま熱処理等に用いる場合には、ＳｉＣは非常に硬いため、結晶粒が大きくなると、その結晶頂部が刃物のごとく作用して、半導体ウェーハの表面を切削してしまうことがあり、また、特許文献２のように被覆面を研磨して用いる場合には、半導体ウェーハが搭載される凹部の底面部と垂直部の境界部分近傍に研磨工程時に応力が集中して、この部分の被覆に微細なクラックが入り、さらに、熱処理時の熱応力により微細クラックを起点として被覆面に、図６に示すようなクラックが発生することがあり、その寿命が短かった。 However, when the susceptor manufactured by the conventional manufacturing method is used for heat treatment or the like with the SiC film coated as in Patent Document 1, since SiC is very hard, when the crystal grains become large, When the top part acts like a blade and cuts the surface of the semiconductor wafer, and the coated surface is polished as in Patent Document 2, the bottom surface of the concave portion on which the semiconductor wafer is mounted FIG. 6 shows stress on the coating surface in the vicinity of the boundary portion between the vertical portion and the vertical portion, where fine cracks are formed in the coating of this portion, and the fine cracks originate from the thermal stress during heat treatment. Such cracks may occur, and their lifetime was short.

また、ウェーハを載置する凹部全ての面を研磨した場合には、この凹部内において、ウェーハは接触界面でのガス残存によって、滑り易い状態にあり、かつ当該凹部の外周角部にガスが滞留する傾向があり、サセプタの回転運動に伴う遠心力及び上記ガスの影響によって、ウェーハが当該凹部から離脱するといった不具合があった。 In addition, when the entire surface of the concave portion on which the wafer is placed is polished, the wafer is in a slippery state due to the gas remaining at the contact interface, and the gas stays at the outer peripheral corner of the concave portion. There is a problem that the wafer is detached from the concave portion due to the centrifugal force accompanying the rotational movement of the susceptor and the influence of the gas.

これを解決するために、当該凹部のウェーハ接触面にサセプタ下面に連通する孔を設けたり、格子状に溝を設ける等の対策が採られているが、この場合には、ウェーハ面内に部分的な温度差が生じ、ウェーハの均一な熱処理ができないといった課題があった。 In order to solve this, measures are taken such as providing a hole communicating with the lower surface of the susceptor on the wafer contact surface of the recess or providing a groove in a lattice shape. There is a problem that a uniform temperature difference occurs and the wafer cannot be uniformly heat-treated.

また、従来のサセプタにおいては、ウェーハを載置する凹部の外周部に連なる外周平面部が通常のＣＶＤ−ＳｉＣコート後の状態のもの、あるいは、鏡面に研磨されたものが存在したが、前者はガス流れがウェーハ載置部の外周部で乱れ、例えばウェーハエピ層の均一化を悪化させると共に、繰り返し使用時において、上記外周部において、不純物成分が凝集し、ウェーハに悪影響を与える可能性が高かった。また、後者においては、上記外周部においてガス流れが過度に均一化し、例えばガス下流側にデポ層の異常成長突起を生じ、使用を繰り返すうちにウェーハのエピ層の均一性を悪化してしまうおそれがあった。
特開昭５６−１０９２１号公報特開平７−３３５５７２号公報 In addition, in the conventional susceptor, the outer peripheral flat part connected to the outer peripheral part of the concave portion on which the wafer is placed is in a state after a normal CVD-SiC coating, or is polished to a mirror surface. The gas flow is disturbed at the outer periphery of the wafer mounting portion, for example, worsening the uniformity of the wafer epi layer, and at the time of repeated use, there is a high possibility that the impurity components aggregate at the outer periphery and adversely affect the wafer. . In the latter case, the gas flow becomes excessively uniform in the outer peripheral portion, for example, abnormal growth protrusions of the deposition layer are formed on the gas downstream side, and the uniformity of the epilayer of the wafer may be deteriorated during repeated use. was there.
JP-A-56-10922 JP 7-335572 A

本発明は上述した事情を考慮してなされたもので、ＳｉＣ被膜表面の結晶の頂部により半導体ウェーハ表面を切削してしまうことがなく、長時間使用してもウェーハが搭載される凹部の外周部下方にクラックが発生することがなく長寿命であり、また、ウェーハが凹部から離脱することなく安定した使用ができ、さらに、ウェーハ面内の均一加熱が可能なサセプタを提供することを目的とする。 The present invention has been made in consideration of the above-described circumstances, and does not cut the surface of the semiconductor wafer by the top of the crystal on the surface of the SiC film. The purpose of the present invention is to provide a susceptor that does not generate cracks, has a long service life, can be used stably without the wafer being detached from the recess, and can uniformly heat the wafer surface. .

また、ウェーハエピ層の均一化が図れ、かつ繰り返し使用しても凹部の外周部に不純物成分の凝集がなく、ウェーハに悪影響を与えることがないサセプタを提供することを目的とする。 It is another object of the present invention to provide a susceptor that can make the wafer epi layer uniform and that does not cause adverse effects on the wafer without aggregation of impurity components on the outer periphery of the recess even when used repeatedly.

本発明者らは、上記目的実現のために、鋭意研究した結果、半導体ウェーハ、特にシリコンウェーハの外周部には必ずウェーハ周辺を面取りするベベリングが行われ、この面取部がサセプタと接触しないことに着目し、サセプタの面取部に対向する部位に研磨されないＳｉＣ結晶成長面部を残すことで、この部分の被覆面に微細なクラックが入らないことを見出し、本発明をするに至った。 As a result of diligent research to achieve the above object, the inventors of the present invention always beveled the periphery of a semiconductor wafer, particularly a silicon wafer, so that the periphery of the wafer does not contact the susceptor. Focusing on the above, it has been found that by leaving an unpolished SiC crystal growth surface portion at a portion facing the chamfered portion of the susceptor, fine cracks are not formed on the coating surface of this portion, and the present invention has been achieved.

すなわち、上記目的を達成するため、本発明によれば、少なくとも表面がＳｉＣで構成され、ウェーハが搭載される凹部を有するサセプタにおいて、前記凹部の外周部下方にＲ部が設けられ、このＲ部内でかつ少なくとも前記凹部の外周垂直部から０．０５ｍｍ以上０．３ｍｍ以下の範囲にＳｉＣ結晶成長面部がリング状に存在し、前記凹部のウェーハと接触する部分が表面粗さＲａで０．５μｍ以上３μｍ以下であることを特徴とするサセプタが提供される。これにより、ＳｉＣ被膜表面の結晶の頂部により半導体ウェーハ表面を切削してしまうことがなく、長時間使用してもウェーハが搭載される凹部の外周部下方にクラックが発生することがなく長寿命であり、また、ウェーハが凹部から離脱することなく安定した使用ができ、さらに、ウェーハ面内の均一加熱が可能なサセプタが実現される。 That is, in order to achieve the above object, according to the present invention, in a susceptor having at least a surface made of SiC and having a concave portion on which a wafer is mounted, an R portion is provided below the outer peripheral portion of the concave portion. In addition, the SiC crystal growth surface portion exists in a ring shape at least in the range of 0.05 mm or more and 0.3 mm or less from the outer peripheral vertical portion of the recess, and the portion of the recess that contacts the wafer has a surface roughness Ra of 0.5 μm or more. A susceptor is provided that is 3 μm or less. As a result, the surface of the semiconductor wafer is not cut by the top of the crystal on the surface of the SiC coating, and even if it is used for a long time, cracks do not occur below the outer periphery of the concave portion on which the wafer is mounted, resulting in a long life. In addition, a susceptor that can be used stably without the wafer being detached from the recess and that can uniformly heat the wafer surface is realized.

好適には、前記凹部の外周部に連なりサセプタの表面の一部あるいは全部をなす外周平面部が、その算術平均粗さＲａが０．０５μｍ以上、０．５μｍ以下の凹凸形状をなす。 Preferably, the outer peripheral flat surface portion that is continuous with the outer peripheral portion of the concave portion and forms part or all of the surface of the susceptor has an irregular shape with an arithmetic average roughness Ra of 0.05 μm or more and 0.5 μm or less.

本発明に係わるサセプタによれば、ＳｉＣ被膜表面の結晶の頂部により半導体ウェーハ表面を切削してしまうことがなく、長時間使用してもウェーハが搭載される凹部の外周部下方にクラックが発生することがなく長寿命であり、また、ウェーハが凹部から離脱することなく安定した使用ができ、さらに、ウェーハ面内の均一加熱が可能なサセプタを提供することができる。 According to the susceptor according to the present invention, the surface of the semiconductor wafer is not cut by the top of the crystal on the surface of the SiC film, and cracks are generated below the outer peripheral portion of the recess in which the wafer is mounted even when used for a long time. Therefore, it is possible to provide a susceptor that has a long life, can be used stably without detaching the wafer from the recess, and can uniformly heat the wafer surface.

また、ウェーハエピ層の均一化が図れ、かつ繰り返し使用しても凹部の外周部に不純物成分の凝集がなく、ウェーハに悪影響を与えることがないサセプタを提供することができる。 Further, it is possible to provide a susceptor in which the wafer epilayer can be made uniform, and the impurity component does not aggregate on the outer peripheral portion of the concave portion even when used repeatedly, and the wafer is not adversely affected.

以下、本発明に係るサセプタの一実施形態について添付図面を参照して説明する。 Hereinafter, an embodiment of a susceptor according to the present invention will be described with reference to the accompanying drawings.

図１は本発明に係るサセプタの縦断面図、図２はその使用状態を示す縦断面図、図３及び図４は図２のＢ部を拡大して示すＲ部近傍の拡大図である。 FIG. 1 is a longitudinal sectional view of a susceptor according to the present invention, FIG. 2 is a longitudinal sectional view showing a use state thereof, and FIGS. 3 and 4 are enlarged views in the vicinity of an R portion showing an enlarged portion B of FIG.

図１に示すように、本発明に係るサセプタ１は、炭素基材２の表面２ａにはＳｉＣ被膜４が被覆され、複数例えば５個の半導体ウェーハ搭載用の凹部３が形成された構造になっている。 As shown in FIG. 1, the susceptor 1 according to the present invention has a structure in which a surface 2a of a carbon substrate 2 is coated with a SiC film 4 and a plurality of, for example, five recesses 3 for mounting a semiconductor wafer are formed. ing.

図２に示すように、この凹部３には、ウェーハＷが搭載され接触するウェーハ接触部３ａとこのウェーハ接触部３ａから垂直に立ち上がる外周垂直部３ｂ間にＲ部３ｃが形成されており、図３及び図４に示すように、研磨されずＳｉＣ結晶成長によって形成されたままのＳｉＣ結晶成長面部４ａのリング状の内周端４ａ_１は、Ｒ部３ｃ内で、かつ凹部３の外周垂直部３ｂから０．０５ｍｍ以上０．３ｍｍ以下の範囲に位置するように形成され、かつ半導体ウェーハＷと接触するウェーハ搭載面３ａの表面粗さＲａが０．５μｍ以上３μｍ以下になっている。すなわち、内周端４ａ_１の外周垂直部３ｂからの距離ｘが、外周垂直部３ｂから０．０５〜０．３ｍｍの範囲にある。 As shown in FIG. 2, an R portion 3c is formed in the recess 3 between the wafer contact portion 3a on which the wafer W is mounted and in contact with the outer peripheral vertical portion 3b rising vertically from the wafer contact portion 3a. 3 and FIG. 4, the ring-shaped inner peripheral edge 4 a ₁ of the SiC crystal growth surface portion 4 a that is not polished and is formed by SiC crystal growth is within the R portion 3 c and the outer peripheral vertical portion of the recess 3. The surface roughness Ra of the wafer mounting surface 3a that is formed so as to be in the range of 3 mm to 0.05 mm and not more than 0.3 mm and is in contact with the semiconductor wafer W is not less than 0.5 μm and not more than 3 μm. That is, the distance x from the outer peripheral vertical portion 3b of the inner peripheral edge 4a ₁ is in the range of 0.05~0.3mm from the outer vertical portion 3b.

外周垂直部からの距離ｘが０．０５ｍｍより小さいと応力緩和効果がみられず、また０．３ｍｍを超えると結晶成長面部がウェーハ裏面に当接し、ウェーハを傷つけるおそれがある。また、結晶成長面部のＲａは５μｍ以上１０μｍ以下であることが好ましい。結晶成長面部の表面粗さＲａが５μｍより小さいと結晶粒界が多く、粒界を通じて応力によりクラックを生じる場合がある。また、Ｒａが１０μｍを超えると、応力緩和の効果が大きく、凹部３において、ウェーハが搭載される搭載面と外周垂直部のなす角が歪んでしまう可能性がある。 If the distance x from the outer peripheral vertical portion is smaller than 0.05 mm, the stress relaxation effect is not observed, and if it exceeds 0.3 mm, the crystal growth surface portion may come into contact with the back surface of the wafer and the wafer may be damaged. Further, Ra of the crystal growth surface portion is preferably 5 μm or more and 10 μm or less. If the surface roughness Ra of the crystal growth surface portion is smaller than 5 μm, there are many crystal grain boundaries, and cracks may occur due to stress through the grain boundaries. Further, if Ra exceeds 10 μm, the effect of stress relaxation is great, and in the recess 3, the angle formed by the mounting surface on which the wafer is mounted and the outer peripheral vertical portion may be distorted.

基材の材質は、任意に選定してよいが、等方性黒鉛質とすることで、容易に所望の形状にすることができる。 The material of the substrate may be arbitrarily selected, but can be easily formed into a desired shape by using isotropic graphite.

本実施形態においては、外周垂直部３ｂに半導体ウェーハが接することがないので、その表面は未研磨のＳｉＣ結晶成長面のままであってもよい。 In the present embodiment, since the semiconductor wafer does not contact the outer peripheral vertical portion 3b, the surface thereof may be an unpolished SiC crystal growth surface.

次に本発明に係るサセプタの製造方法について説明する。 Next, the manufacturing method of the susceptor according to the present invention will be described.

図５に示すように、凹部３が形成された炭素基材２の表面２ａにＳｉＣ被膜４が被覆されたサセプタ１を用意し、研磨装置１１により、ウェーハ搭載面３ａ及び外周垂直部３ｂの研磨を行い表面粗さＲａが０．５μｍ以上３μｍ以下にする。さらに、Ｒ部３ｃも外周垂直部３ｂから０．０５ｍｍ以上０．３ｍｍ以下の範囲の非研磨面部を残し、それ以外の部位を研磨し、表面粗さＲａが０．５μｍ以上３μｍ以下にする。ＳｉＣ結晶成長面部４ａが残るように、Ｒ部３ｃの外周垂直部３ｂから０．０５ｍｍ以上０．３ｍｍ以下の範囲は研磨されない。従って、ＳｉＣ結晶成長面部４ａである非研磨面部には、研磨時の応力により微細なクラックが発生しない。 As shown in FIG. 5, a susceptor 1 is prepared in which a surface 2a of a carbon substrate 2 having a recess 3 formed thereon is coated with a SiC coating 4. A polishing apparatus 11 polishes the wafer mounting surface 3a and the outer peripheral vertical portion 3b. The surface roughness Ra is adjusted to 0.5 μm or more and 3 μm or less. Further, the R portion 3c also leaves a non-polished surface portion in the range of 0.05 mm or more and 0.3 mm or less from the outer peripheral vertical portion 3b, and polishes other portions so that the surface roughness Ra is 0.5 μm or more and 3 μm or less. A range from 0.05 mm to 0.3 mm from the outer peripheral vertical portion 3b of the R portion 3c is not polished so that the SiC crystal growth surface portion 4a remains. Therefore, fine cracks do not occur in the non-polished surface portion, which is the SiC crystal growth surface portion 4a, due to stress during polishing.

また、本発明に係るサセプタを用いた半導体ウェーハの熱処理方法について説明する。 Also, a method for heat-treating a semiconductor wafer using the susceptor according to the present invention will be described.

図２及び図３のように、半導体ウェーハＷを炉内に設置されたサセプタ１に形成されたウェーハ搭載面３ａに搭載して、凹部３に収容する。 As shown in FIGS. 2 and 3, the semiconductor wafer W is mounted on the wafer mounting surface 3 a formed on the susceptor 1 installed in the furnace and accommodated in the recess 3.

このとき、半導体ウェーハＷはベベリングによって面取部ｃが形成されているので、Ｒ部３ｃのＳｉＣ結晶成長面部４ａに接触することがない。 At this time, since the chamfered portion c is formed by beveling in the semiconductor wafer W, it does not contact the SiC crystal growth surface portion 4a of the R portion 3c.

しかる後、炉内に原料ガスを供給するとともに、サセプタ１及び半導体ウェーハＷを加熱して、半導体ウェーハＷの熱処理を行う。 Thereafter, the raw material gas is supplied into the furnace, and the susceptor 1 and the semiconductor wafer W are heated to heat-treat the semiconductor wafer W.

このような熱処理工程において、サセプタ１には、ウェーハＷを搭載する凹部３の外周部下方にＲ部３ｃが設けられ、このＲ部３ｃ内でかつ少なくとも凹部３の外周垂直部から０．０５ｍｍ以上０．３ｍｍ以下の範囲にＳｉＣ結晶成長面部がリング状に存在し（研磨されずフラットになっていない）、ＳｉＣ結晶によって適度な凹凸が外周部に存在するため、凹部３の外周角部にガスが滞留することなく、結果、ウェーハＷが凹部３から離脱するといった問題も生じることもなく、安定した使用ができ、また、凹部３におけるウェーハＷとの接触部が表面粗さＲａで０．５μｍ以上３μｍ以下の均質な面となっている（連通孔や格子状の溝等が存在しない）ため、ウェーハＷの面内均一な熱処理ができる。 In such a heat treatment step, the susceptor 1 is provided with an R portion 3c below the outer peripheral portion of the concave portion 3 on which the wafer W is mounted, and at least 0.05 mm from the outer peripheral vertical portion of the concave portion 3 in the R portion 3c. Since the SiC crystal growth surface portion exists in a ring shape in a range of 0.3 mm or less (not polished and flat), and moderate irregularities are present in the outer peripheral portion due to the SiC crystal, gas is generated in the outer peripheral corner portion of the concave portion 3. Can be used stably without causing a problem that the wafer W is detached from the recess 3 as a result, and the contact portion with the wafer W in the recess 3 has a surface roughness Ra of 0.5 μm. Since the surface is a uniform surface of 3 μm or less (there are no communication holes or lattice-like grooves), the wafer W can be uniformly heat-treated in the surface.

また、半導体ウェーハＷが接するウェーハ搭載面３ａが、表面粗さＲａが０．５μｍ以上３μｍ以下に研磨されているので、半導体ウェーハの表面を切削してしまうこともない。また、研磨されないＳｉＣ結晶成長面部４ａのリング状の内周端４ａ_１は、Ｒ部内でかつ凹部３の外周垂直部から０．０５ｍｍ以上０．３ｍｍ以下の範囲に位置するように形成されているので、ＳｉＣ結晶成長面部４ａに研磨による微細なクラックが入っておらず、熱処理時の熱応力により微細クラックを起点としたクラックが被覆面に発生することがない。 Moreover, since the wafer mounting surface 3a with which the semiconductor wafer W is in contact is polished to a surface roughness Ra of 0.5 μm or more and 3 μm or less, the surface of the semiconductor wafer is not cut. Further, the ring-shaped inner peripheral end 4a ₁ of the SiC crystal growth surface portion 4a that is not polished is formed so as to be located within the R portion and within the range of 0.05 mm or more and 0.3 mm or less from the outer peripheral vertical portion of the recess 3. Therefore, there are no fine cracks due to polishing in the SiC crystal growth surface portion 4a, and cracks originating from the fine cracks do not occur on the coated surface due to thermal stress during heat treatment.

上記のように本実施形態によれば、ＳｉＣ被膜表面の結晶の頂部により半導体ウェーハ表面を切削してしまうことがなく、長時間使用してもウェーハが搭載される凹部の外周部下方にクラックが発生することがなく長寿命であり、また、ウェーハが凹部から離脱することなく安定した使用ができ、さらに、ウェーハ面内の均一加熱が可能になる。 As described above, according to the present embodiment, the surface of the semiconductor wafer is not cut by the top of the crystal on the surface of the SiC coating, and cracks are formed below the outer peripheral portion of the concave portion where the wafer is mounted even when used for a long time. It does not occur, has a long life, can be used stably without the wafer being detached from the recess, and can be uniformly heated within the wafer surface.

なお、上記実施形態では、基材に複数のウェーハ載置用の凹部が設けられた例で説明したが、本発明のサセプタは基材に１個の凹部が設けられた枚葉式サセプタであっても、同様の効果を奏する。 In the above embodiment, the example in which the substrate is provided with a plurality of recesses for mounting a wafer has been described. However, the susceptor of the present invention is a single-wafer type susceptor in which a substrate is provided with one recess. However, the same effect can be obtained.

また、本発明に係るサセプタの他の実施形態について説明する。 Further, another embodiment of the susceptor according to the present invention will be described.

本実施形態は、図２に示す上記実施形態において、凹部の外周部に連なる外周平面部の平面粗さの範囲を限定したサセプタである。 This embodiment is a susceptor in which the range of the planar roughness of the outer peripheral flat surface portion connected to the outer peripheral portion of the recess is limited in the embodiment shown in FIG.

例えば、図７に示すように、本実施形態に係るサセプタ１１は、凹部３の外周部に連なりサセプタ１１の表面の一部あるいは全部をなす外周平面部３ｄが設けられ、この外周平面部３ｄの算術平均粗さＲａ（ＪＩＳＢ０６０１−１９９４）は、０．０５μｍ以上、０．５ｕｍ以下の凹凸形状をなしている。 For example, as shown in FIG. 7, the susceptor 11 according to the present embodiment is provided with an outer peripheral plane portion 3 d that is connected to the outer peripheral portion of the recess 3 and forms part or all of the surface of the susceptor 11. The arithmetic average roughness Ra (JIS B0601-1994) has an uneven shape of 0.05 μm or more and 0.5 μm or less.

これにより、図８に示すように、例えばエピタキシャル成長工程において、エピタキシャル装置２１のベルジャー２２内に供給された原料ガスは、外周平面部３ｄに達し、この外周平面部３ｄの適度な凹凸形状の凸状部間すなわち凹状部を通って流れるため整流され、さらに、原料ガス流に含まれる不純物が凹状部に凝集して堆積されるので、ウェーハ上に流れる原料ガスの流れに乱れがなく、均一なエピ層の形成が可能となり、さらに、長期間使用しても、エピ層に不純物が混入するのが防止され、不純物不良発生が低減される。 As a result, as shown in FIG. 8, for example, in the epitaxial growth process, the source gas supplied into the bell jar 22 of the epitaxial apparatus 21 reaches the outer peripheral plane portion 3d, and this outer peripheral plane portion 3d has a moderately convex shape. Rectification is performed because the gas flows through the recesses, that is, through the recesses, and impurities contained in the source gas flow aggregate and accumulate in the recesses, so that the flow of the source gas flowing on the wafer is not disturbed and uniform epitaxy. The layer can be formed, and even when used for a long period of time, impurities are prevented from being mixed into the epi layer, and the occurrence of impurity defects is reduced.

外周平面部の表面粗さが０．５μｍ以上であると、整流作用が低下し、０．０５μｍ以下であると、外周平面部のガス流れが過度に均一化し、ガス下流側すなわち外周平面部の凹部側に異常成長突起を生じ、使用を繰り返すうちにウェーハのエピ層の均一性が悪化してしまう。 When the surface roughness of the outer peripheral plane portion is 0.5 μm or more, the rectification action is reduced, and when it is 0.05 μm or less, the gas flow in the outer peripheral plane portion becomes excessively uniform, and the gas downstream side, that is, the outer peripheral plane portion Abnormal growth protrusions are formed on the concave side, and the uniformity of the epilayer of the wafer deteriorates as the use is repeated.

なお、外周平面部は、本実施形態のように、基材に５個の凹部が形成されるようなサセプタにおいては、凹部を除く基材の表面の７０％以上を占めるのが好ましく、７０％以上においてガス流れが飛躍的に整流化される。また、基材に１個の凹部が形成される枚葉式サセプタにあっては、表面の全部であるのが好ましい。 In the susceptor in which five concave portions are formed in the base material as in the present embodiment, the outer peripheral plane portion preferably occupies 70% or more of the surface of the base material excluding the concave portions, and 70% In this way, the gas flow is dramatically rectified. Moreover, in the single wafer type susceptor in which one concave portion is formed on the base material, the entire surface is preferable.

さらに、凹部の周囲に形成される外周平面部を含む基材が、凹部と構造上一体製造あるいは組み付けが困難である場合や、または凹部と基材の寿命が異なる場合には、基材と凹部の一部または全部を別個に製造する分割形にあっても、本発明の同様の効果が得られる。 Furthermore, if the base material including the outer peripheral flat portion formed around the recess is difficult to manufacture or assemble with the recess structurally, or if the recess and the base material have different lifetimes, the base material and the recess The same effect of the present invention can be obtained even in a divided form in which a part or all of the parts are separately manufactured.

他の構成は図２に示すサセプタと異ならないので、同一符号を付して説明は省略する。 Since the other configuration is not different from the susceptor shown in FIG.

「試験１」
（実施例１）：凹部を１個備えたサセプタ形状に加工した等方性炭素基材にＲａが７．２μｍのＳｉＣで被覆したサセプタについて、外周側０．３ｍｍを除いた凹部の搭載面を、＃５００以下のダイヤモンド砥粒を備えた回転式研磨機で研削研磨し、サセプタを得た。
（実施例２）：凹部の外周側未研磨部分を０．０５ｍｍとする以外は実施例１と同様の方法でサセプタを得た。
（実施例３）：回転式研磨機の砥粒を＃４０以下とする以外は実施例１と同様の方法でサセプタを得た。
（実施例４）：回転式研磨機の砥粒を＃４０以下とする以外は実施例２と同様の方法でサセプタを得た。 "Test 1"
(Example 1): For a susceptor in which an isotropic carbon base material processed into a susceptor shape having one recess is coated with SiC having Ra of 7.2 μm, the mounting surface of the recess except for 0.3 mm on the outer peripheral side is used. The susceptor was obtained by grinding and polishing with a rotary polishing machine equipped with diamond abrasive grains of # 500 or less.
(Example 2): A susceptor was obtained in the same manner as in Example 1 except that the unpolished portion on the outer peripheral side of the recess was set to 0.05 mm.
(Example 3): A susceptor was obtained in the same manner as in Example 1 except that the abrasive grains of the rotary polishing machine were set to # 40 or less.
Example 4 A susceptor was obtained in the same manner as in Example 2 except that the abrasive grains of the rotary polishing machine were set to # 40 or less.

（比較例１）：凹部の外周側未研磨部分を０．４ｍｍまでとする以外は実施例１と同様の方法でサセプタを得た。
（比較例２）：凹部の外周側未研磨部分を０．４ｍｍとする以外は実施例３と同様の方法でサセプタを得た。
（比較例３）：回転式研磨機の砥粒を＃８００以下とする以外は実施例１と同様の方法でサセプタを得た。
（比較例４）：回転式研磨機の砥粒を＃８００以下とする以外は実施例２と同様の方法でサセプタを得た。 (Comparative example 1): The susceptor was obtained by the same method as Example 1 except the outer peripheral side unpolished part of a recessed part made into 0.4 mm.
(Comparative Example 2): A susceptor was obtained in the same manner as in Example 3 except that the unpolished portion on the outer peripheral side of the recess was 0.4 mm.
(Comparative Example 3): A susceptor was obtained in the same manner as in Example 1 except that the abrasive grains of the rotary polishing machine were set to # 800 or less.
(Comparative Example 4): A susceptor was obtained in the same manner as in Example 2 except that the abrasive grains of the rotary polishing machine were set to # 800 or less.

各実施例および各比較例の研磨面部の表面粗さを測定し、さらに、これらをエピタキシャル成長装置に組み込み、１００枚のシリコンウェーハを処理して、ウェーハ裏面キズの発生枚数を測定し、また、使用後の凹部におけるクラックの有無を調べた。 The surface roughness of the polished surface portion of each example and each comparative example is measured, and further, these are incorporated in an epitaxial growth apparatus, 100 silicon wafers are processed, the number of wafer backside scratches is measured, and used. The presence or absence of cracks in the subsequent recess was examined.

結果を表１に示す。

The results are shown in Table 1.

表１からもわかるように、結晶成長面部幅及び研磨面部Ｒａは本発明の範囲内の実施例１〜４は、いずれもウェーハに傷の発生がなく、凹部クラックの発生もなかった。 As can be seen from Table 1, in Examples 1 to 4 within the scope of the present invention, the crystal growth surface portion width and the polishing surface portion Ra were all free of scratches on the wafer and no cracks were generated.

これに対して、結晶成長面部幅の上限を外れ研磨面部Ｒａ下限内の比較例１は、傷発生が１２枚あり、凹部クラックの発生はなかった。 In contrast, Comparative Example 1 outside the upper limit of the crystal growth surface portion width and within the lower limit of the polishing surface portion Ra had 12 scratches and no recess cracks.

結晶成長面部幅の上限を外れ研磨面部Ｒａ上限内の比較例２は、傷発生が４２枚あり、凹部クラックはなかった。 Comparative Example 2 outside the upper limit of the crystal growth surface portion width and within the upper limit of the polishing surface portion Ra had 42 scratches and no recess cracks.

結晶成長面部幅の下限内で研磨面部Ｒａ下限外の比較例３は、傷発生が１１枚あり、また、ウェーハと搭載面部の固着が発生し、凹部クラックはなかった。 In Comparative Example 3 within the lower limit of the crystal growth surface portion width and outside the lower limit of the polishing surface portion Ra, there were 11 scratches, the wafer and the mounting surface portion were fixed, and there were no recess cracks.

結晶成長面部幅の下限内で研磨面部Ｒａ下限外の比較例４は、傷発生が１６枚あり、また、ウェーハと搭載面部の固着が発生し、凹部トクラックはなかった。 In Comparative Example 4 within the lower limit of the crystal growth surface portion width and outside the lower limit of the polishing surface portion Ra, there were 16 scratches, the wafer and the mounting surface portion were fixed, and there were no recess cracks.

「試験２」
凹部とこの凹部の外周に平面形状の外周平面部を備えたサセプタ形状に機械加工した等方性炭素に公知の方法でＳｉＣを被覆し、その後種々の仕上げに外周平面部を研削研磨して、表２に示すように、外周平面部の表面粗さ及び凹部を除く基材の表面に対する外周平面部の面積比を変化させ、実施例（５−９）および比較例（５、６）のサセプタを得た。 "Test 2"
The isotropic carbon machined into a susceptor shape having a flat outer peripheral plane portion on the outer periphery of the concave portion and the concave portion is coated with SiC by a known method, and then the outer peripheral flat portion is ground and polished for various finishes. As shown in Table 2, the surface roughness of the outer peripheral flat portion and the area ratio of the outer peripheral flat portion to the surface of the substrate excluding the recesses were changed, and the susceptors of Example (5-9) and Comparative Examples (5, 6) Got.

これらの実施例（５−９）および比較例（５、６）を用いて、シリコンウェーハのエピタキシャル成長処理を１００枚実施し、エピ層の均一性と不純物濃度を評価した。

Using these Examples (5-9) and Comparative Examples (5, 6), 100 silicon wafers were epitaxially grown, and the uniformity and impurity concentration of the epi layer were evaluated.

表２からもわかるように、外周平面部面粗さＲａが本発明の範囲内にある実施例５−９はいずれも、均一性不良発生数及び不純物不良発生数が少ないのに対して、範囲外の比較例５、６は均一性不良発生数が多く、また、比較例６は不純物不良発生数も多い。 As can be seen from Table 2, in Examples 5-9, in which the outer peripheral plane portion surface roughness Ra is within the scope of the present invention, the number of occurrences of uniformity defects and impurity defects is small. The other comparative examples 5 and 6 have a large number of uniformity defects, and the comparative example 6 also has a large number of impurity defects.

本発明の一実施形態に係わるサセプタの平面図。The top view of the susceptor concerning one Embodiment of this invention. 図１のＡ−Ａ線に沿う断面図。Sectional drawing in alignment with the AA of FIG. 図２のＢ部を拡大して示す断面図。Sectional drawing which expands and shows the B section of FIG. 図２のＢ部を拡大して示す断面図。Sectional drawing which expands and shows the B section of FIG. 本発明の一実施形態に係わるサセプタの製造方法の概念図。The conceptual diagram of the manufacturing method of the susceptor concerning one Embodiment of this invention. 従来のサセプタのクラック発生状態を示す説明図。Explanatory drawing which shows the crack generation state of the conventional susceptor. 本発明の他の実施形態に係わるサセプタの断面図。Sectional drawing of the susceptor concerning other embodiment of this invention. 本発明の他の実施形態に係わるサセプタの使用状態を示す概念図。The conceptual diagram which shows the use condition of the susceptor concerning other embodiment of this invention.

符号の説明Explanation of symbols

１サセプタ
２基材
２ａ表面
３凹部
３ａウェーハ搭載面
３ｂ外周垂直部
３ｃＲ部
４ＳｉＣ被膜
４ａＳｉＣ結晶成長面部
４ａ_１内周端 DESCRIPTION OF SYMBOLS 1 Susceptor 2 Base material 2a Surface 3 Recess 3a Wafer mounting surface 3b Periphery vertical part 3c R part 4 SiC coating 4a SiC crystal growth surface part 4a ₁ Inner peripheral edge

Claims

少なくとも表面がＳｉＣで構成され、ウェーハが搭載される凹部を有するサセプタにおいて、前記凹部の外周部下方にＲ部が設けられ、このＲ部内でかつ少なくとも前記凹部の外周垂直部から０．０５ｍｍ以上０．３ｍｍ以下の範囲にＳｉＣ結晶成長面部がリング状に存在し、前記凹部のウェーハと接触する部分が表面粗さＲａで０．５μｍ以上３μｍ以下であることを特徴とするサセプタ。 In a susceptor having at least a surface made of SiC and having a concave portion on which a wafer is mounted, an R portion is provided below the outer peripheral portion of the concave portion, and 0.05 mm or more from at least the outer peripheral vertical portion of the concave portion within the R portion. A susceptor characterized in that the SiC crystal growth surface portion is present in a ring shape in a range of 3 mm or less, and the portion of the recess that contacts the wafer has a surface roughness Ra of 0.5 μm or more and 3 μm or less.

前記凹部の外周部に連なりサセプタの表面の一部あるいは全部をなす外周平面部が、その算術平均粗さＲａが０．０５μｍ以上、０．５μｍ以下の凹凸形状をなすことを特徴とする請求項１に記載のサセプタ。 The outer peripheral plane portion that is connected to the outer peripheral portion of the concave portion and forms part or all of the surface of the susceptor has an uneven shape with an arithmetic average roughness Ra of 0.05 μm or more and 0.5 μm or less. The susceptor according to 1.