JP4151976B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4151976B2 JP4151976B2 JP2005051355A JP2005051355A JP4151976B2 JP 4151976 B2 JP4151976 B2 JP 4151976B2 JP 2005051355 A JP2005051355 A JP 2005051355A JP 2005051355 A JP2005051355 A JP 2005051355A JP 4151976 B2 JP4151976 B2 JP 4151976B2
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- metal
- layer
- insulating film
- gate electrode
- gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Description
図1は、本発明に係る半導体装置の第1の実施形態である。
図3は、本発明に係る半導体装置の第2の実施形態である。
図5は、本発明に係る半導体装置の第3の実施形態である。
図7は、本発明に係る半導体装置の第4の実施形態である。
図8は、本発明に係る半導体装置の第5の実施形態である。
図10は本発明に関する第6の実施形態である。
2…ソース・ドレイン領域
3…Wゲートコンタクトプラグ
4…Wソース・ドレインコンタクトプラグ
5…NiSi層
6…多結晶Si層(リンが高濃度に注入された多結晶Si層)
7…TiN層
8…シリコン熱酸化膜層(ゲート絶縁膜層)
9…素子分離Si酸化膜層(素子分離絶縁膜層)
10 …ソース・ドレイン(リンドープ拡散領域)
11 …ゲート側壁Si酸化膜層
12 …多結晶Si層
13 …堆積ニッケル層
14 …BPSG膜
15 …レジスト膜
16 …n型ウェル領域
17 …p型ウェル領域
18 …LaB6層
19 …PtGe層
20 …ボロンが高濃度に注入された多結晶Si層
21 …ソース・ドレイン(ボロンドープ拡散領域)
22 …埋め込み絶縁膜層
Claims (10)
- 半導体層を有する半導体基板と、前記半導体層上に形成されたゲート絶縁膜と、前記絶縁膜上に形成された金属または金属化合物とこの金属または金属化合物上に形成された多結晶シリコン層と前記多結晶シリコン層上に形成された金属珪化物との積層構造からなるゲート電極と、前記ゲート電極を挟む様に前記半導体基板の表面部に形成されたソース領域およびドレイン領域と、前記半導体層を囲むように形成された素子分離絶縁膜層と、前記ゲート電極に対し、前記金属珪化物および前記多結晶シリコン層を貫通して前記金属または金属化合物と接触する上部配線と、を含む事を特徴とする半導体装置。
- 半導体層を有する半導体基板と、前記半導体層上に形成されたゲート絶縁膜と、前記絶縁膜上に形成された金属または金属化合物とこの金属または金属化合物上に形成された多結晶シリコン層と前記多結晶シリコン層上に形成された金属珪化物との積層構造からなるゲート電極と、前記ゲート電極を挟む様に前記半導体基板の表面部に形成されたソース領域およびドレイン領域と、前記半導体層を囲むように形成された素子分離絶縁膜層と、前記ゲート電極の積層構造を貫通して前記素子分離絶縁膜層まで到達する上部配線と、を含む事を特徴とする半導体装置。
- 前記上部配線は、前記素子分離絶縁層上にて前記金属または金属化合物と接触することを特徴とする請求項1に記載の半導体装置。
- 前記上部配線との接続部のゲート電極構造は、金属珪化物の上に金属を有する金属/金属珪化物構造である事を特徴とする請求項1または2に記載の半導体装置。
- 前記金属または金属化合物と前記多結晶シリコン層の間に金属窒化膜を有することを特徴とする請求項1または2に記載の半導体装置。
- 前記ソース領域および前記ドレイン領域がn型であるn型MISトランジスタおよび前記ソース領域および前記ドレイン領域がp型であるp型MISトランジスタからなる相補型MISトランジスタを構成することを特徴とする請求項1乃至5のいずれかに記載の半導体装置。
- 前記n型MISトランジスタにおける金属または金属化合物が、希土類系、遷移金属の珪化物、ジャーマナイド、金属ボライドのいずれかひとつであり、前記p型MISトランジスタにおける金属または金属化合物が、金属炭化物、貴金属珪化物、金属窒化物、金属ジャーマナイド、W化合物、及び貴金属のいずれかひとつであることを特徴とする請求項6に記載の半導体装置。
- 前記希土類系、遷移金属の珪化物、ジャーマナイドはErSi1.7、YSi2、TaSi、ErGe1.7、前記金属ボライドはHfB、TaB、TiB、金属炭化物はTiC、TaC、貴金属珪化物はPtSi、PdSi、金属窒化物はTiN、TaN、金属ジャーマナイドはNiGe、PtGe、W化合物はWC、WB、貴金属はPt、Au、Ir、Ru、Wから各々選ばれたひとつの材料を主としたものあることを特徴とする請求項7に記載の半導体装置。
- 前記半導体基板内にさらに埋め込み絶縁膜層を有する完全空乏型のトランジスタにおける金属または金属化合物が、Ta、NiSi、Ta2N、ZrC、WSi2、TiN、TiCから選ばれた1つの材料を主としたものあることを特徴とする請求項1乃至6のいずれかに記載の半導体装置。
- 前記相補型MISトランジスタにおける前記金属または金属化合物の膜厚は10nm以下であることを特徴とする請求項6に記載の半導体装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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JP2005051355A JP4151976B2 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置 |
US11/329,228 US7429777B2 (en) | 2005-02-25 | 2006-01-11 | Semiconductor device with a gate electrode having a laminate structure |
US12/219,096 US7601623B2 (en) | 2005-02-25 | 2008-07-16 | Method of manufacturing a semiconductor device with a gate electrode having a laminate structure |
US12/549,298 US8203189B2 (en) | 2005-02-25 | 2009-08-27 | Semiconductor device including gate electrode having a laminate structure and plug electrically connected thereto |
US12/549,308 US20100035392A1 (en) | 2005-02-25 | 2009-08-27 | Semiconductor device |
US13/470,372 US8592924B2 (en) | 2005-02-25 | 2012-05-14 | Semiconductor device including gate electrode having a laminate structure and a plug electrically connected thereto |
Applications Claiming Priority (1)
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JP2005051355A JP4151976B2 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置 |
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JP4151976B2 true JP4151976B2 (ja) | 2008-09-17 |
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JP2005051355A Expired - Fee Related JP4151976B2 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置 |
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JP (1) | JP4151976B2 (ja) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4151976B2 (ja) | 2005-02-25 | 2008-09-17 | 株式会社東芝 | 半導体装置 |
JP4764030B2 (ja) * | 2005-03-03 | 2011-08-31 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7459382B2 (en) * | 2006-03-24 | 2008-12-02 | International Business Machines Corporation | Field effect device with reduced thickness gate |
JP2008177316A (ja) * | 2007-01-18 | 2008-07-31 | Toshiba Corp | 半導体装置およびその製造方法 |
US7973304B2 (en) | 2007-02-06 | 2011-07-05 | International Rectifier Corporation | III-nitride semiconductor device |
JP4459257B2 (ja) * | 2007-06-27 | 2010-04-28 | 株式会社東芝 | 半導体装置 |
KR100903383B1 (ko) * | 2007-07-31 | 2009-06-23 | 주식회사 하이닉스반도체 | 일함수가 조절된 게이트전극을 구비한 트랜지스터 및 그를구비하는 메모리소자 |
WO2009101704A1 (ja) * | 2008-02-15 | 2009-08-20 | Unisantis Electronics (Japan) Ltd. | 半導体装置の製造方法 |
JP2009224509A (ja) * | 2008-03-14 | 2009-10-01 | Panasonic Corp | 半導体装置及びその製造方法 |
US20110049639A1 (en) * | 2008-04-29 | 2011-03-03 | Nxp B.V. | Integrated circuit manufacturing method and integrated circuit |
JP2010010224A (ja) * | 2008-06-24 | 2010-01-14 | Panasonic Corp | 半導体装置及びその製造方法 |
US8120072B2 (en) | 2008-07-24 | 2012-02-21 | Micron Technology, Inc. | JFET devices with increased barrier height and methods of making same |
US8674451B2 (en) * | 2008-12-10 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | N/P metal crystal orientation for high-K metal gate Vt modulation |
US7863123B2 (en) * | 2009-01-19 | 2011-01-04 | International Business Machines Corporation | Direct contact between high-κ/metal gate and wiring process flow |
JP2010245433A (ja) * | 2009-04-09 | 2010-10-28 | Panasonic Corp | 半導体装置及びその製造方法 |
US8878363B2 (en) | 2009-06-26 | 2014-11-04 | Intel Corporation | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same |
JP2011071402A (ja) * | 2009-09-28 | 2011-04-07 | Panasonic Corp | 半導体装置の製造方法及びそれを用いた半導体装置 |
US8592889B1 (en) * | 2012-05-21 | 2013-11-26 | United Microelectronics Corp. | Memory structure |
US9041114B2 (en) * | 2013-05-20 | 2015-05-26 | Kabushiki Kaisha Toshiba | Contact plug penetrating a metallic transistor |
US9590105B2 (en) * | 2014-04-07 | 2017-03-07 | National Chiao-Tung University | Semiconductor device with metal alloy over fin, conductive layer over channel region of fin, and semiconductive layer over conductive layer and formation thereof |
US10692788B2 (en) * | 2017-08-28 | 2020-06-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device to decrease flicker noise in conductor-insulator-semiconductor (CIS) devices |
US10658482B2 (en) | 2017-11-01 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Plate design to decrease noise in semiconductor devices |
JP2020136446A (ja) * | 2019-02-19 | 2020-08-31 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、固体撮像装置、及び半導体装置の製造方法 |
US10714432B1 (en) | 2019-03-25 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Layout to reduce noise in semiconductor devices |
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JPS5748268A (en) | 1980-09-05 | 1982-03-19 | Hitachi Ltd | Manufacture of mos semiconductor device |
JPH05206461A (ja) | 1992-01-14 | 1993-08-13 | Nec Corp | 半導体装置の製造方法 |
JPH1117165A (ja) | 1997-06-20 | 1999-01-22 | Nkk Corp | 半導体装置の積層ゲート構造 |
US6020024A (en) | 1997-08-04 | 2000-02-01 | Motorola, Inc. | Method for forming high dielectric constant metal oxides |
US5854114A (en) * | 1997-10-09 | 1998-12-29 | Advanced Micro Devices, Inc. | Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide |
JP3394022B2 (ja) * | 1999-08-16 | 2003-04-07 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP2003142683A (ja) * | 2001-11-02 | 2003-05-16 | Mitsubishi Electric Corp | 半導体装置および半導体製造方法 |
US6696345B2 (en) * | 2002-01-07 | 2004-02-24 | Intel Corporation | Metal-gate electrode for CMOS transistor applications |
US6936508B2 (en) * | 2003-09-12 | 2005-08-30 | Texas Instruments Incorporated | Metal gate MOS transistors and methods for making the same |
US7279413B2 (en) * | 2004-06-16 | 2007-10-09 | International Business Machines Corporation | High-temperature stable gate structure with metallic electrode |
JP4151976B2 (ja) * | 2005-02-25 | 2008-09-17 | 株式会社東芝 | 半導体装置 |
-
2005
- 2005-02-25 JP JP2005051355A patent/JP4151976B2/ja not_active Expired - Fee Related
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2006
- 2006-01-11 US US11/329,228 patent/US7429777B2/en active Active
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2008
- 2008-07-16 US US12/219,096 patent/US7601623B2/en active Active
-
2009
- 2009-08-27 US US12/549,308 patent/US20100035392A1/en not_active Abandoned
- 2009-08-27 US US12/549,298 patent/US8203189B2/en active Active
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2012
- 2012-05-14 US US13/470,372 patent/US8592924B2/en active Active
Also Published As
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JP2006237372A (ja) | 2006-09-07 |
US8203189B2 (en) | 2012-06-19 |
US7429777B2 (en) | 2008-09-30 |
US20080280405A1 (en) | 2008-11-13 |
US8592924B2 (en) | 2013-11-26 |
US20100032765A1 (en) | 2010-02-11 |
US20100035392A1 (en) | 2010-02-11 |
US20120223393A1 (en) | 2012-09-06 |
US20060192258A1 (en) | 2006-08-31 |
US7601623B2 (en) | 2009-10-13 |
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