JP4076930B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4076930B2 JP4076930B2 JP2003308859A JP2003308859A JP4076930B2 JP 4076930 B2 JP4076930 B2 JP 4076930B2 JP 2003308859 A JP2003308859 A JP 2003308859A JP 2003308859 A JP2003308859 A JP 2003308859A JP 4076930 B2 JP4076930 B2 JP 4076930B2
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- Prior art keywords
- thin film
- substrate
- film
- transistor
- amorphous
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Description
集積回路の分野において用いられるSOI基板は、良好なトランジスタを作って半導体素子の機能を飛躍的に向上させることが目的である。集積回路では、通常、単結晶Si膜が形成される基板は絶縁性であればよく、それが透明であっても不透明であっても、あるいは結晶質であっても非晶質であっても構わない。また、集積回路の分野においては素子が完全分離されるため動作上の制約が少なく、SOI基板を用いてトランジスタを作ることにより、良好な特性と高い性能を実現できる。
このため、上記改質工程におけるエネルギービーム照射時に、後に行われる上記剥離工程で剥離される上記転写用基板の一部がヒートシンクの役割を果たし、エネルギービーム照射に伴う熱的ダメージにより転写トランジスタが損傷されることを防止できる。したがって、絶縁基板上に、転写トランジスタと成膜トランジスタとを、両者の特性を低下させることなくモノリシックに搭載することができるという効果を奏する。
2 絶縁基板
3 絶縁膜(SiO2膜)
4 層間絶縁膜(SiO2膜)
5 非晶質Si薄膜
5’ 多結晶Si薄膜
6 ゲート電極
7 ゲート絶縁膜(SiO2膜)
8 層間絶縁膜(SiO2膜)
10 単結晶Siウエハ
10a 単結晶Si基板(転写用基板)
11 シリコン片(転写用基板の一部)
12 ゲート電極
13 ゲート絶縁膜
14a 単結晶Si薄膜
15 水素イオン注入部
16a 単結晶Si薄膜トランジスタ(転写トランジスタ)
Claims (4)
- 絶縁基板上に、該絶縁基板上に転写されてなる転写トランジスタと、該絶縁基板上で形成される成膜トランジスタとが混在する半導体装置の製造方法において、
上記転写トランジスタの形成工程では、上記転写トランジスタの主要部が形成され、水素イオンが注入された転写用基板を上記絶縁基板上に貼り合わせる貼合工程と、上記転写用基板の一部を熱処理により剥離する剥離工程とを含み、
上記成膜トランジスタの形成工程では、上記絶縁基板上に非晶質Si薄膜を形成する非晶質Si薄膜形成工程と、上記非晶質Si薄膜にエネルギービームを照射することにより多結晶Si薄膜に改質する改質工程とを含み、
上記非晶質Si薄膜が触媒CVD法によって形成され、
上記改質工程が、上記貼合工程より後、かつ、上記剥離工程より前に行われることを特徴とする半導体装置の製造方法。 - 絶縁基板上に、該絶縁基板上に転写されてなる転写トランジスタと、該絶縁基板上で形成される成膜トランジスタとが混在する半導体装置の製造方法において、
上記転写トランジスタの形成工程では、上記転写トランジスタの主要部が形成され、水素イオンが注入された転写用基板を上記絶縁基板上に貼り合わせる貼合工程と、上記転写用基板の一部を熱処理により剥離する剥離工程とを含み、
上記成膜トランジスタの形成工程では、上記絶縁基板上に非晶質Si薄膜を形成する非晶質Si薄膜形成工程と、上記非晶質Si薄膜にエネルギービームを照射することにより多結晶Si薄膜に改質する改質工程とを含み、
上記非晶質Si薄膜形成工程で形成される上記非晶質Si薄膜の水素含有量が1×1019cm-3以下であり、
上記改質工程が、上記貼合工程より後、かつ、上記剥離工程より前に行われることを特徴とする半導体装置の製造方法。 - 上記転写用基板が、上記貼合工程の前に、ゲート絶縁膜、ゲート電極、ソース・ドレイン不純物注入領域、層間絶縁膜を形成され、表面の平坦化および水素イオン注入がなされていることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 上記転写トランジスタが、単結晶Siトランジスタであることを特徴とする請求項1〜3のいずれかに記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003308859A JP4076930B2 (ja) | 2003-09-01 | 2003-09-01 | 半導体装置の製造方法 |
US10/910,620 US7253040B2 (en) | 2003-08-05 | 2004-08-04 | Fabrication method of semiconductor device |
FR0408662A FR2858714B1 (fr) | 2003-08-05 | 2004-08-05 | Procede de fabrication d'un dispositif a semi-conducteur |
KR1020040061714A KR100586356B1 (ko) | 2003-08-05 | 2004-08-05 | 반도체 장치의 제조 방법 |
Applications Claiming Priority (1)
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JP2003308859A JP4076930B2 (ja) | 2003-09-01 | 2003-09-01 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2005079384A JP2005079384A (ja) | 2005-03-24 |
JP4076930B2 true JP4076930B2 (ja) | 2008-04-16 |
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JP2003308859A Expired - Fee Related JP4076930B2 (ja) | 2003-08-05 | 2003-09-01 | 半導体装置の製造方法 |
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JP (1) | JP4076930B2 (ja) |
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