JP4051027B2 - Power semiconductor device module - Google Patents

Power semiconductor device module Download PDF

Info

Publication number
JP4051027B2
JP4051027B2 JP2003502885A JP2003502885A JP4051027B2 JP 4051027 B2 JP4051027 B2 JP 4051027B2 JP 2003502885 A JP2003502885 A JP 2003502885A JP 2003502885 A JP2003502885 A JP 2003502885A JP 4051027 B2 JP4051027 B2 JP 4051027B2
Authority
JP
Japan
Prior art keywords
power semiconductor
thermally conductive
substrate
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003502885A
Other languages
Japanese (ja)
Other versions
JP2004529505A (en
Inventor
マングタニ ビジャ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of JP2004529505A publication Critical patent/JP2004529505A/en
Application granted granted Critical
Publication of JP4051027B2 publication Critical patent/JP4051027B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0101—Neon [Ne]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

本発明は、パワー半導体デバイスモジュールに関し、より詳細には、製造コストおよび信頼性を単純化するようなパワー半導体デバイスモジュールについての新規な構造に関する。 The present invention relates to power semiconductor devices Sumo Joules, and more particularly to a novel structure for a power semiconductor device module so as to simplify the manufacturing cost and reliability.

複数のパワー半導体ダイ（ｄｉｅ）を、絶縁金属基板（ＩＭＳ）などのセラミックベースの基板支持に固定して、デバイス間を相互接続すると共にパワーダイ制御用制御回路を備えたプリント回路板（ＰＣＢ）を支持する主支持シェル（main support shell）内にこれらのパワー半導体ダイを担持させる半導体モジュールは周知である。直接接合銅（ＤＢＣ）基板をＩＭＳの代わりに使用することもできる。電源端子が、モータなどの負荷に接続するためにＩＭＳから延び、ＰＣＢは、外部制御信号源に接続するための端子コネクタを担持する。このようなデバイスは通常、ＩＭＳがシェルの小さい開口内に固定され（その結果、高価なＩＭＳの領域を最小にすることができる）、ＩＭＳの底面を押し付けてヒートシンクの平面と接触させるように構成される。   A printed circuit board (PCB) having a plurality of power semiconductor dies (die) fixed to a ceramic-based substrate support such as an insulating metal substrate (IMS) and interconnecting the devices and having a control circuit for power die control Semiconductor modules that carry these power semiconductor dies in a supporting main support shell are well known. Direct bonded copper (DBC) substrates can also be used instead of IMS. A power supply terminal extends from the IMS for connection to a load such as a motor, and the PCB carries a terminal connector for connection to an external control signal source. Such devices are typically configured so that the IMS is secured within a small opening in the shell (so that the area of the expensive IMS can be minimized) and the bottom surface of the IMS is pressed into contact with the heat sink plane. Is done.

ＰＣＢは一般に、ＩＭＳの平面上の１つの平面内に支持され、ＩＭＳ領域から横方向に除去される。ＰＣＢの底部は、構成要素をＰＣＢの底面および頂面に取り付けることができるように支持シェルの頂面の上に間隔を置いて配置される。   The PCB is generally supported in one plane on the plane of the IMS and removed laterally from the IMS region. The bottom of the PCB is spaced above the top surface of the support shell so that components can be attached to the bottom and top surfaces of the PCB.

この構造では、ＩＭＳ上のパワーダイの制御電極、例えばＭＯＳＦＥＴおよびＩＧＢＴのゲート電極、温度感知電極、電流感知電極、およびケルビン電極へのワイアボンドは、パワーダイの頂面（top surface）のうちの低い面から、ＰＣＢの上面(upper surface)の上平面(upper plane)まで延びなければならず、管理するのが困難な長いワイアボンドが生み出される。   In this structure, the wire bond to the control electrode of the power die on the IMS, eg, MOSFET and IGBT gate electrode, temperature sensing electrode, current sensing electrode, and Kelvin electrode is from the lower side of the top surface of the power die. A long wire bond is created which must extend to the upper plane of the upper surface of the PCB and is difficult to manage.

さらに、従来技術の構造では、相互接続されたパワー半導体ダイ、分路、温度センサ、および電流センサを含む、通常はＩＭＳである基板が、絶縁ベースシェルにまず取り付けられる。次に、ＰＣＢがベースシェルに取り付けられ、ワイアボンドが、シリコンダイとＰＣＢに対する基板との間に形成される。次に、キャップがＩＭＳの上に配置され、カプセル材、例えばシリコーンが、キャップの開口を通じてキャップ内部のＩＭＳの頂部に導入され、シリコーンが硬化する。モジュールの多い部品数を削減することに有利である。   Further, in the prior art structure, a substrate, usually an IMS, including interconnected power semiconductor dies, shunts, temperature sensors, and current sensors is first attached to the insulating base shell. Next, the PCB is attached to the base shell, and a wire bond is formed between the silicon die and the substrate for the PCB. The cap is then placed over the IMS and an encapsulant, such as silicone, is introduced through the cap opening to the top of the IMS inside the cap and the silicone is cured. It is advantageous to reduce the number of parts with many modules.

一般に、セラミックベースの基板は、様々な半導体ダイを担持するのに頻繁に利用される。これらの基板は通常、基板３２０について図１３および図１４に示す構造を有し、底部銅層３２１と、中央絶縁セラミック３２２（Ａｌ2Ｏ3またはＡｌＮでよい）と、図示する６つの絶縁領域３２３、３２４、３２５、３２６、３２７、および３２８などの様々な領域中にパターン形成された頂部銅層（top copper layer）とを有する。頂部銅層に対して任意の他のパターンを形成することもできる。領域３２３から３２８は、はんだ付け、または導電性エポキシなどによってそれらに固定されたパワー半導体デバイスダイ３３０〜３３５をそれぞれ有する。ダイ３３０〜３３５の底部電極は絶縁されるが、導電性トレースまたはワイアボンドによって所望の通りに互いに接続することができる。図１３および図１４の基板３２０は、直接接合銅（direct bonded copper:ＤＢＣ）基板でもよい。 In general, ceramic-based substrates are frequently used to carry various semiconductor dies. These substrates typically have the structure shown in FIGS. 13 and 14 for substrate 320, with a bottom copper layer 321, a central insulating ceramic 322 (which can be Al 2 O 3 or AlN), and six insulating regions 323 as shown. With top copper layers patterned in various regions, such as 324, 325, 326, 327, and 328. Any other pattern can be formed for the top copper layer. Regions 323-328 have power semiconductor device dies 330-335, respectively, secured to them, such as by soldering or conductive epoxy. The bottom electrodes of the dies 330-335 are insulated but can be connected to each other as desired by conductive traces or wire bonds. The substrate 320 of FIGS. 13 and 14 may be a direct bonded copper (DBC) substrate.

このような基板の機械的保全性(mechanical integrity)を保証し、かつセラミックが割れることを防止するために、このような基板の長さは、通常約２インチ（５．０８ｃｍ）未満に限定される。したがって、パワーモジュールがより大きな基板を必要とするとき、２つ以上の短い基板を使用しなければならない。したがって、図１５に示すように、２つの同一の基板３２０および３４０が、共通ベースプレート３４１に取り付けられる。共通ベースプレート３４１は、より高性能の応用例向けに、銅製またはＡｌＳｉＣ製である。   In order to ensure the mechanical integrity of such substrates and to prevent the ceramic from cracking, the length of such substrates is usually limited to less than about 2 inches (5.08 cm). The Thus, when the power module requires a larger substrate, two or more short substrates must be used. Accordingly, two identical substrates 320 and 340 are attached to a common base plate 341 as shown in FIG. The common base plate 341 is made of copper or AlSiC for higher performance applications.

基板３２０および３４０は、通常通り、はんだリフロー技法または導電性エポキシによって共通ベースプレート３４１に取り付けられる。次いで基板３２０、３４０、およびベースプレート３４１のサブアセンブリは、ベースプレート３４１の底部がフラットヒートシンク３５１に接続するために露出されて、プラスチック支持シェル３５０内に固定される。次いで、適切なプリント電流板および端子が設けられる。シリコンダイおよび基板はワイアボンディングされ、またはＰＣＢに接続され、端子および基板は、適切なポットボリューム内に封入される。   The substrates 320 and 340 are attached to the common base plate 341 by solder reflow techniques or conductive epoxy as usual. Substrates 320 and 340 and base plate 341 are then secured in plastic support shell 350 with the bottom of base plate 341 exposed for connection to flat heat sink 351. Appropriate printed current plates and terminals are then provided. The silicon die and substrate are wire bonded or connected to the PCB, and the terminals and substrate are encapsulated in a suitable pot volume.

上述の構造はいくつかの欠点を有する。その欠点には、
１．ベースプレート３４１に関するツーリングコストおよび材料コスト
２．ベースプレート３４１を使用するのに必要な追加の処理
３．プレート３４１の頂部および底部の追加の界面による、シリコンダイとヒートシンク３５１との間の追加の熱抵抗
４．追加の界面による、パワー循環能力および温度循環能力の劣化
を含む。 The above structure has several drawbacks. Its drawbacks are:
1. Tooling and material costs for base plate 341 1. 2. Additional processing required to use base plate 341 3. Additional thermal resistance between the silicon die and the heat sink 351 due to the additional interface at the top and bottom of the plate 341. Includes degradation of power and temperature cycling capabilities due to additional interfaces.

追加の共通ベースプレートによってもたらされる欠点なしに、パワーモジュールで複数の基板を利用することが望ましい。   It is desirable to utilize multiple substrates in a power module without the disadvantages introduced by the additional common base plate.

周知の従来技術の構造では、上述のように、モジュール全体は、ねじなどによって単一の一体型ヒートシンクに取り付けられる。個々のデバイスは、高価なＩＭＳまたはＤＢＣを使用することによって、共通ヒートシンクを伝わる伝導に対して互いに電気的に絶縁される。ＩＭＳまたはＤＢＣなどの基板を使用することにより、ダイとヒートシンクの間の熱抵抗が増加する。   In known prior art structures, as described above, the entire module is attached to a single integrated heat sink, such as by screws. Individual devices are electrically isolated from each other through conduction through a common heat sink by using expensive IMS or DBC. By using a substrate such as IMS or DBC, the thermal resistance between the die and the heat sink is increased.

モータ制御回路に関しては独立型回路であり、高価な単一または複数の絶縁基板を必要とせず、かつダイからヒートシンクへの熱流を妨げないパワー半導体デバイスモジュールを提供することが望ましい。 It is desirable to provide a power semiconductor device module that is a stand-alone circuit with respect to the motor control circuit, does not require expensive single or multiple insulating substrates, and does not impede heat flow from the die to the heat sink.

本発明の第１の特徴によれば、支持絶縁シェル構造が、シェルの底部の上のより高い平面内に、ＰＣＢの平面により接近してＩＭＳを支持するように変更される。モジュールを受ける主ヒートシンクも、ＩＭＳの***した底面と係合する、***した平頂メサを有するように変更される。したがって、ＩＭＳ（または他の類似の基板）とＰＣＢとの高さの差が減少し、これらは、密に隣接する平行な各平面内にある。「密に隣接する」とは、ＩＭＳの厚さの約２倍未満であることを意味する。   According to a first aspect of the invention, the supporting insulating shell structure is modified to support the IMS closer to the plane of the PCB, in a higher plane above the bottom of the shell. The main heat sink that receives the module is also modified to have a raised flat top mesa that engages the raised bottom surface of the IMS. Thus, the height difference between the IMS (or other similar substrate) and the PCB is reduced and they are in each closely adjacent parallel plane. “Closely adjacent” means less than about twice the thickness of the IMS.

この新規な構造により、いくつかの利点が生み出される。まず、ＩＭＳ上のダイの頂部とＰＣＢの頂部との高さの差が減少することにより、ワイアボンドのワイア接合性および品質が向上し、したがって製造歩留まりが向上する。   This new structure creates several advantages. First, the reduction in height difference between the top of the die on the IMS and the top of the PCB improves the wire bondability and quality of the wire bond, thus improving the manufacturing yield.

第２に、ワイアボンドの長さが縮小され、デバイス動作中のワイアボンドに対する機械的ストレスが軽減される。   Second, the length of the wire bond is reduced, reducing the mechanical stress on the wire bond during device operation.

第３に、カプセル材で充填する必要のある、ＩＭＳの上の空洞の容積が縮小され、使用するポッティング材料の容積が縮小される。   Third, the volume of the cavity above the IMS that needs to be filled with encapsulant is reduced and the volume of potting material used is reduced.

本発明の第２の特徴によれば、パワーダイ、ならびに電流センサおよび温度センサを担持する基板、分路などがＰＣＢに直接取り付けられてＰＣＢを支持し、従来の絶縁ベースシェルが不要となる。ＰＣＢはＩＭＳ基板の頂部を露出するための適切な開口を有し、シリコン基板とＰＣＢとの間をボンディングするためのアクセス可能なワイアボンディングの場所が残る。次に、キャップがアセンブリの頂部に取り付けられ、接着剤またはねじ構造によって固定される。キャップは、ヒートシンクの表面に向かって押し付けられる。全モジュールの電気的テストは、ヒートシンクの装着およびカプセル化の前に実施することができる。   According to the second feature of the present invention, the power die, the substrate carrying the current sensor and the temperature sensor, the shunt, etc. are directly attached to the PCB to support the PCB, and the conventional insulating base shell is not required. The PCB has an appropriate opening to expose the top of the IMS substrate, leaving an accessible wire bonding location for bonding between the silicon substrate and the PCB. A cap is then attached to the top of the assembly and secured with an adhesive or screw structure. The cap is pressed toward the surface of the heat sink. All module electrical tests can be performed prior to heat sink installation and encapsulation.

制御回路が複雑であり、かつヒートシンクの底面の制御構成要素が望ましい場合、その領域でヒートシンクを切り取り、必要なスペースを設けることができる。   If the control circuitry is complex and a control component on the bottom surface of the heat sink is desired, the heat sink can be cut in that area to provide the necessary space.

本発明における基板は、シェルに接着され、ヒートシンクに押し付けられて接触するのではなく、熱的特性を改善するために、接着剤でヒートシンクに直接取り付けられる。あるいは、頂部キャップを通るねじが、基板およびＰＣＢをヒートシンクに固定することもできる。   The substrate in the present invention is attached directly to the heat sink with an adhesive to improve thermal properties, rather than being bonded to the shell and pressed against the heat sink. Alternatively, screws through the top cap can secure the substrate and PCB to the heat sink.

本発明の別の態様によれば、複数の基板がプラスチックシェルの各開口にそれぞれ装着され、中間の共通伝導性ベースが不要となる。ＰＣＢは基板の上に配設され、シリコンダイ、基板、およびＰＣＢと端子との間の必要な相互接続およびワイアボンディングのための、各基板の頂部へのアクセスを提供する開口を含む。   According to another aspect of the present invention, a plurality of substrates are mounted in each opening of the plastic shell, eliminating the need for an intermediate common conductive base. The PCB is disposed on the substrate and includes an opening that provides access to the top of each substrate for the necessary interconnection and wire bonding between the silicon die, the substrate, and the PCB and the terminals.

望むなら、ＰＣＢは、別のＰＣＢ、あるいはその他の構成要素またはワイアを他の装置に接続するための、はんだ付け可能／スナップマウントピン、端子、コネクタなどの追加の相互接続を含むことができる。   If desired, the PCB can include additional interconnects, such as solderable / snap mount pins, terminals, connectors, etc., for connecting another PCB or other components or wires to other devices.

別の実装では、ＰＣＢを省略することができ、絶縁シェルは、リードフレームに対してワイアボンド接続が行われた挿入成形リードフレームを含むことができる。このリードは、相互接続を作成するためにモジュール外部のＰＣＢにはんだ付けすることができる。   In another implementation, the PCB can be omitted and the insulating shell can include an insert molded leadframe with a wire bond connection to the leadframe. This lead can be soldered to a PCB outside the module to create an interconnect.

本発明のさらに別の実装では、内部ＰＣＢを外部ＰＣＢで置き換えることができ、基板は、（リフローハンダによって基板に接続された）端子ピンを含むことができ、端子ピンは、外部ＰＣＢに接続される。   In yet another implementation of the present invention, the internal PCB can be replaced with an external PCB, the substrate can include terminal pins (connected to the substrate by reflow solder), and the terminal pins are connected to the external PCB. The

本発明のさらに別の実装では、別々の基板を縦方向に整列して、ＰＣＢを絶縁支持シェルに装着するのに必要な装着ねじの数を減らすことができる。   In yet another implementation of the present invention, separate substrates can be aligned vertically to reduce the number of mounting screws required to mount the PCB to the insulating support shell.

本発明のさらに別の態様では、従来技術の単一ヒートシンクが、モジュールの主支持絶縁シェルに固定され、互いに間隔を置いて配置され、かつ絶縁シェルによって互いに絶縁される、複数の別々のヒートシンクに分割される。ダイは、はんだリフローまたは伝導性エポキシ技法などによってそれぞれのヒートシンクに取り付けられる。したがって、底部電極が同じ電位にある１つまたは複数のダイは、それぞれのヒートシンクの頂部ベア伝導性表面に直接固定される。したがって、異なる電位のダイを分離するのにＩＭＳは不要であり、ダイは、それぞれのヒートシンクに熱的に密に接続される。ダイオード、パワーＭＯＳＦＥＴ、ＩＧＢＴ、サイリスタなどのパワーダイのどんな混合も使用できることに留意されたい。   In yet another aspect of the present invention, a prior art single heat sink is connected to a plurality of separate heat sinks secured to the main support insulating shell of the module, spaced apart from each other and insulated from each other by the insulating shell. Divided. The dies are attached to their respective heat sinks, such as by solder reflow or conductive epoxy techniques. Thus, one or more dies whose bottom electrodes are at the same potential are secured directly to the top bare conductive surface of the respective heat sink. Thus, no IMS is required to separate the different potential dies, and the dies are thermally and tightly connected to their respective heat sinks. Note that any mix of power dies such as diodes, power MOSFETs, IGBTs, thyristors, etc. can be used.

まず図１および図２を参照すると、典型的な従来技術のモジュールが示されている。したがって、成形シェル支持ベース１２がＰＣＢ１３を支持し、ＩＭＳ１５（図２）を装着する底部開口１４を有する。ＩＭＳは、上側と下側の導電層が中央の絶縁フィルムで絶縁される材料のフラットシートである。導電層は、下側の厚い銅またはアルミニウムのヒートシンクと、上側の薄い銅層とを含み、薄い上側の銅層は、ダイ２０および２１などのパワーダイを装着および相互接続することができる導電性装着パッドを形成するようにパターン形成することができる。ダイ取り付けは、はんだリフローまたは導電性エポキシなどによって得ることができる。   Referring first to FIGS. 1 and 2, a typical prior art module is shown. Thus, the molded shell support base 12 supports the PCB 13 and has a bottom opening 14 for mounting the IMS 15 (FIG. 2). IMS is a flat sheet of material in which the upper and lower conductive layers are insulated by a central insulating film. The conductive layer includes a lower thick copper or aluminum heat sink and an upper thin copper layer, the thin upper copper layer being capable of mounting and interconnecting power dies such as dies 20 and 21. Patterns can be formed to form pads. The die attachment can be obtained by solder reflow or conductive epoxy.

ＩＭＳ１５の底面は、シェル１２中の絶縁ボルト３１、３２、３３（図１および図２Ａ）によって押し付けられ、単一のヒートシンク３０（図２）の平坦な上面と接触する。ＩＭＳ１５は、開口１４(図２)内の肩付き溝４０にはめ込まれることに留意されたい。さらに、プリント回路板１３は、このプリント回路板１３の底部の構成要素のためにスペースを設けるように、シェル１２内のシェルフ４１の頂部に置かれる。 The bottom surface of the IMS 15 is pressed by insulating bolts 31, 32, 33 (FIGS. 1 and 2A) in the shell 12 and contacts the flat top surface of a single heat sink 30 (FIG. 2). Note that IMS 15 fits into shouldered groove 40 in opening 14 (FIG. 2). Further, the printed circuit board 13 is placed on top of the shelf 41 in the shell 12 so as to provide space for components at the bottom of the printed circuit board 13 .

次いで、ダイ２０および２１からプリント回路板１３上の端子までワイアボンディングが行われ、このワイアボンディングは、パワーダイ２０および２１の動作を制御する制御端子５０からの制御信号を導通する。出力端子５５〜５６に電力供給するためにもワイアボンドが形成される。   Next, wire bonding is performed from the dies 20 and 21 to the terminals on the printed circuit board 13, and this wire bonding conducts a control signal from the control terminal 50 that controls the operation of the power dies 20 and 21. Wire bonds are also formed to supply power to the output terminals 55-56.

高グレードポッティング化合物、例えば適切な柔軟なシラスティック６０は、図３に示すように、キャップ７０よって包含される、ＩＭＳ１５の上の空洞を充填する。キャップ７０をまず定位置に接続し、シラスティックまたは他のポッティング材料をキャップの開口を通じて注入し、その後に硬化させることができることに留意されたい。低グレードポッティング材料を使用して、シェル１２の内部全体を充填することもできる。 A high grade potting compound, such as a suitable flexible silastic 60, fills the cavity above the IMS 15 which is encompassed by the cap 70 as shown in FIG. Note that the cap 70 can be first connected in place and silastic or other potting material can be injected through the opening in the cap and then cured. Low grade potting material can also be used to fill the entire interior of the shell 12 .

フィルタコンデンサ８０をモジュールと共に含めることもできる。   A filter capacitor 80 can also be included with the module.

図１および図２に示す構造は、全寸法７．５ｃｍ×５ｃｍ×１ｃｍを有することができ、インバータ、入力回路、保護回路、およびマイクロプロセッサを含む全モータ制御回路を収容することができる。インバータおよび他のパワーダイはＩＭＳ１５に固定され、他の構成要素はＰＣＢ１３上にある。   The structure shown in FIGS. 1 and 2 can have a total dimension of 7.5 cm × 5 cm × 1 cm and can accommodate the entire motor control circuit including the inverter, input circuit, protection circuit, and microprocessor. The inverter and other power die are fixed to the IMS 15 and the other components are on the PCB 13.

図３に、キャップ７０が定位置に置かれ、シラスティック６０が封入されている、図２の構造の拡大した部分を示す。ＩＭＳ１５とＰＣＢ１３のワイアボンド表面の高さが異なることを理解されよう。この結果として、ＩＭＳ１５表面と、ＩＭＳ１５からＰＣＢ１３あるいは端子５５および５６の端子パッド（図１および図２）にワイアボンディングすべきワイア９０および９１（図３）とを覆うのに、多量のカプセル材が必要となる。さらに、ワイアボンドは長く、管理するのが比較的難しい。   FIG. 3 shows an enlarged portion of the structure of FIG. 2 where the cap 70 is in place and the silastic 60 is encapsulated. It will be appreciated that the wire bond surface heights of IMS 15 and PCB 13 are different. This results in a large amount of encapsulant covering the IMS 15 surface and the wires 90 and 91 (FIG. 3) to be wire bonded from the IMS 15 to the PCB 13 or the terminal pads of the terminals 55 and 56 (FIGS. 1 and 2). Necessary. Furthermore, wire bonds are long and relatively difficult to manage.

図２で、ＰＣＢ１３の平面を大幅に低くすることは可能である。しかしそれにより、ＰＣＢ１３の下側に構成要素を配置することが不可能となり、したがって多数の構成要素が必要な場合にＰＣＢ１３のためにより広い領域が必要となる。さらに、ＰＣＢ１３もヒートシンク３０に接近し、ＰＣＢ１３が熱くなる。   In FIG. 2, it is possible to significantly reduce the plane of the PCB 13. However, this makes it impossible to place components below the PCB 13, thus requiring a larger area for the PCB 13 when multiple components are required. Further, the PCB 13 approaches the heat sink 30 and the PCB 13 becomes hot.

本発明の第１の特徴によれば、図４に示すように、ショルダ４０がＰＣＢ１３の平面に向かってずっと高い位置に移動するように絶縁シェル１２の構造を変更することができる。次いでＩＭＳ１５の底部がシェル１２の底部の平面よりかなり上に移動する。したがって、平坦な上面を有するメサ１００がヒートシンク３０上に形成され、メサ１００は、開口１４を取り囲むショルダ４０内に閉じ込められるＩＭＳ１５の底面を押しつけるように構成される。   According to the first feature of the present invention, the structure of the insulating shell 12 can be modified such that the shoulder 40 moves to a much higher position toward the plane of the PCB 13 as shown in FIG. The bottom of the IMS 15 then moves significantly above the plane of the bottom of the shell 12. Accordingly, a mesa 100 having a flat top surface is formed on the heat sink 30 and the mesa 100 is configured to press against the bottom surface of the IMS 15 that is confined within the shoulder 40 surrounding the opening 14.

図４に示すように、得られる構造により、ダイ２０および２１の上面が、ＩＭＳ１５を取り囲むＰＣＢ１３の平面に接近する。したがって、高グレード、すなわち高価なシラスティック６０で充填しなければならないＩＭＳ１５の上の容積がかなり削減される。ワイアボンド９０および９１の長さは短くなり、動作中のワイアボンドに対する機械的ストレスが軽減され、ワイアの接合性および品質が向上し、製造歩留まりが向上する。   As shown in FIG. 4, the resulting structure brings the top surfaces of the dies 20 and 21 closer to the plane of the PCB 13 that surrounds the IMS 15. Thus, the volume above the IMS 15 that must be filled with a high grade, i.e., expensive silastic 60, is significantly reduced. The lengths of the wire bonds 90 and 91 are reduced, reducing mechanical stress on the wire bond during operation, improving the bondability and quality of the wire, and improving the manufacturing yield.

図４Ａおよび図４Ｂに、本発明の第２の特徴と、同じ識別符号を有する図１から図４と同様の部品とを示す。まず、図４Ａでは、拡大された開口４００を有するようにＰＣＢ１３が変更されていることに留意されたい。ＩＭＳ１５は、その外縁部で、下にある開口４００の縁に接合される。次いでダイ、基板、およびＰＣＢが適切にワイアボンディングされ、サブアセンブリが電気的にテストされる。   FIGS. 4A and 4B show a second feature of the present invention and parts similar to FIGS. 1-4 having the same identification numbers. First, note that in FIG. 4A, the PCB 13 has been modified to have an enlarged opening 400. The IMS 15 is joined at its outer edge to the edge of the underlying opening 400. The die, substrate, and PCB are then properly wire bonded and the subassembly is electrically tested.

次いで絶縁キャップ４１０が図示されるように装着され、ＩＭＳ１５の上面とワイアボンドがその中に封入される。ＰＣＢ１３を通過するねじ４１１および４１２は、ヒートシンク３０を貫通し、キャップ４１０、ＰＣＢ１３、およびＩＭＳ１５が定位置に固定される。キャップおよびＩＭＳは、適切な接着剤によってヒートシンク３０に固定することができる。次いでキャップは、キャップの開口（図示せず）を通じて適切なポッティング化合物で充填され、次いで化合物が硬化する。   The insulating cap 410 is then installed as shown and the upper surface of the IMS 15 and the wire bond are encapsulated therein. Screws 411 and 412 passing through the PCB 13 pass through the heat sink 30 and the cap 410, PCB 13 and IMS 15 are fixed in place. The cap and IMS can be secured to the heat sink 30 with a suitable adhesive. The cap is then filled with the appropriate potting compound through the cap opening (not shown) and the compound is then cured.

図４Ａおよび図４Ｂの新規な構造により、図１から図４の従来の絶縁ベースシェル１２が不要となる。さらに、ＩＭＳ１５と基板１５の熱的接続が向上し、キャッピングの前に回路の事前テストが可能である。   The novel structure of FIGS. 4A and 4B eliminates the need for the conventional insulating base shell 12 of FIGS. Furthermore, the thermal connection between the IMS 15 and the substrate 15 is improved, and a pre-test of the circuit is possible before capping.

ＰＣＢ１３の下側に構成要素が望まれる場合、図４Ｂの点線４３０、４４０で示すようにヒートシンク３０を切り取り、ヒートシンク３０の周辺部分に必要な空間を設けることができることに留意されたい。   It should be noted that if a component is desired under the PCB 13, the heat sink 30 can be cut out as shown by the dotted lines 430, 440 in FIG.

次に図５から図９を参照すると、図１から図４に類似の構成要素が同じ参照符号を有しており、主支持シェル１２が、図５に示すように、互いに絶縁すべきヒートシンクをそれぞれ受けるようなサイズに作られた複数の開口１１０、１１１、１１２、１１３、１１４、および１１５を有するように本発明の別の特徴に従って変更されている。   Referring now to FIGS. 5-9, components similar to FIGS. 1-4 have the same reference numerals, and the main support shell 12 has a heat sink to be insulated from each other as shown in FIG. It has been modified in accordance with another aspect of the present invention to have a plurality of apertures 110, 111, 112, 113, 114, and 115 each sized to receive.

図６から図９に、開口１１３に装着されるヒートシンク１２０のうちの１つを示す。ヒートシンク１２０は、平坦なダイ受け上面１２１、フィン付きボディ１２２、および外部フランジ１２３を有する。ヒートシンク１２０と、同一のヒートシンク１２４、１２５、１２６、１２７、および１２８（図８および図９）のボディは、それぞれ開口１１３、１１４、１１５、１１０、１１１、および１１２にはめ込まれる。これらは、ヒートシンク１２０のフランジ１２３などのフランジの下側に接合するなど、どんな所望の方式でもシェル１２に固定することができる。明らかに、ヒートシンクはシェル１２の絶縁材料によって互いに絶縁される。 FIGS. 6 to 9 show one of the heat sinks 120 attached to the opening 113. The heat sink 120 has a flat die receiving upper surface 121, a finned body 122, and an outer flange 123. The body of heat sink 120 and the same heat sink 124, 125, 126, 127, and 128 (FIGS. 8 and 9) are fitted into openings 113, 114, 115, 110, 111, and 112, respectively. They can be secured to the shell 12 in any desired manner, such as joining to the underside of a flange, such as the flange 123 of the heat sink 120. Obviously, the heat sinks are insulated from each other by the insulating material of the shell 12.

ヒートシンク１２０および１２４から１２８を設置する前または後に、ダイ１３０、１３１、１３２、１３３、１３４、および１３５（図８および図９）などの個々のパワー半導体ダイ１３４が、それぞれヒートシンク１２０および１２４から１２８の表面１２１などの頂面に接続される。ダイは、熱的および電気的に各ヒートシンクにそれぞれ直接結合することができる底部電極を有するパワーダイである。次いでダイ１３０から１３５の頂部電極を電気的に接続して、ダイを相互接続し外部リードに接続されるワイアボンドによって、どんな所望の回路も形成される。これらの外部リードまたは端子を、ヒートシンク１２６、１２７、および１２８（したがってダイ１３３、１３４、および１３５の底部電極）のそれぞれに接続される端子１５０として示し、また、ダイ１３３、１３４、および１３５と、ヒートシンク１２０、１２４、および１２５にそれぞれワイアボンディングされる端子１５１、１５２、および１５３として示し、また、ダイ１３０、１３１、および１３２の頂部金属電極にそれぞれ接続される端子１５４、１５５、および１５６として示し、さらに、１３３から１３５および１３０から１３２のゲート電極または制御電極にそれぞれ接続される制御端子１６０、１６１、１６２、１６３、１６４、および１６５として示す。端子１５０から１６５は共通リードフレームの要素とすることができることに留意されたい。 Before or after installing heat sinks 120 and 124 to 128 , individual power semiconductor dies 134, such as dies 130, 131, 132, 133, 134, and 135 (FIGS. 8 and 9), respectively, are heat sinks 120 and 124 to 128 , respectively. Connected to the top surface such as the surface 121 of the. The die is a power die having a bottom electrode that can be directly and thermally coupled to each heat sink. Any desired circuit is then formed by wire bonds that electrically connect the top electrodes of dies 130-135 and interconnect the dies and connect to external leads. These external leads or terminals are shown as terminals 150 connected to each of heat sinks 126, 127, and 128 (and thus the bottom electrodes of dies 133, 134, and 135), and dies 133, 134, and 135; the heat sink 120, 124, and shown in 125 as a terminal 151, 152, and 153 are wire bonding, respectively, also shown as terminals 154, 155, and 156 are respectively connected to the top metal electrodes of the die 130, 131, and 132 Further shown as control terminals 160, 161, 162, 163, 164, and 165 connected to the gate electrodes or control electrodes 133-135 and 130-132, respectively. Note that terminals 150-165 may be elements of a common lead frame.

制御端子１６０から１６５に印加される制御信号を供給または処理するために、図１から図４のボード１３などの制御プリント回路板を、図５から図９のシェル１２内のダイ１３０から１３５の高さの上に固定できることに留意されたい。   In order to provide or process control signals applied to control terminals 160-165, a control printed circuit board, such as board 13 of FIGS. 1-4, may be connected to dies 130-135 in shell 12 of FIGS. Note that it can be fixed above the height.

本発明ではまた、図５から図９に示すように、別々のヒートシンクを使用することにより、ダイ１３０から１３５のそれぞれを適切に絶縁するための高価なＩＭＳ基板が不要となり、熱性能の改善も得られる。   The present invention also eliminates the need for expensive IMS substrates to properly insulate each of the dies 130 to 135 by using separate heat sinks, as shown in FIGS. can get.

図５から図９の実施形態の構造は、それぞれのダイについて別々のヒートシンクを示しているが、複数のダイを帯状のヒートシンク上に装着できることを理解されよう。例えば、図１０および図１１に、３つのヒートシンク１８０、１８１、および１８２を使用する実施形態を示す。各ヒートシンクは、それぞれ、ＰチャネルＭＯＳＦＥＴ １８３、１８４、および１８５と、ＮチャネルＭＯＳＦＥＴ １８６、１８７、１８８を担持する。ヒートシンク１８０から１８２のそれぞれは、間隔を置いて配置された２つのダイを受ける平坦な上面、絶縁シェル１２の開口に接合することができるフランジ（図１１のフランジ１９０）、フィン１９１、または他の所望の構造を有する。構造および回路はどんな所望の方式でも完成することができる。   While the structure of the embodiment of FIGS. 5-9 shows a separate heat sink for each die, it will be appreciated that multiple dies can be mounted on a strip-shaped heat sink. For example, FIGS. 10 and 11 illustrate an embodiment that uses three heat sinks 180, 181, and 182. Each heat sink carries P-channel MOSFETs 183, 184, and 185 and N-channel MOSFETs 186, 187, 188, respectively. Each of the heat sinks 180-182 has a flat top surface that receives two spaced apart dies, a flange that can be joined to the opening of the insulating shell 12 (flange 190 in FIG. 11), fins 191, or other Has the desired structure. The structure and circuit can be completed in any desired manner.

図１２に示すように、様々なサイズのヒートシンクを混在させることも可能である。すなわち、図１２に示すように、１つの長いヒートシンク２００が、間隔を置いて配置され、（底部電極で）相互接続されたＭＯＳＦＥＴ ２０１、２０２、および２０３を担持することができ、一方、図８および図９のヒートシンク１２０、１２４、および１２５などの別々のヒートシンクが、完全に電気的に絶縁されたパワーＭＯＳＦＥＴ １３０、１３１、および１３２をそれぞれ担持することができる。 As shown in FIG. 12, heat sinks of various sizes can be mixed. That is, as shown in FIG. 12, one long heat sink 200 can carry spaced apart and interconnected MOSFETs 201, 202, and 203 (at the bottom electrode), while FIG. And separate heat sinks, such as heat sinks 120, 124 , and 125 of FIG. 9, can carry fully electrically isolated power MOSFETs 130, 131, and 132, respectively.

次に図１６、図１７、および図１８を参照すると、本発明の別の態様の別の実施形態が示されている。すなわち、基板３２０と３４０にそれぞれ類似する２つの別々の基板３６０および３６１が、絶縁支持ハウジング３８２（図１５のハウジング３５０と同様）内の装着ねじによって、ヒートシンクに別々に押し付けられる。基板３６０および３６１は、それぞれ別々の開口３６３および３６４内に含まれ（図１７および図１８）、それらの上面は、ＰＣＢ ３７２の開口３７０および３７１を通じて露出する。ＰＣＢ ３７２はハウジング３８２内に装着され、ハウジング３８２から一体的に延びるボスに貫通するねじ３９０、３９１、３９２、および３９３によってハウジング３８２に固定される。ねじ３９１と３９３に対するボス３９５および３９６をそれぞれ図１７に示す。   Referring now to FIGS. 16, 17 and 18, another embodiment of another aspect of the present invention is shown. That is, two separate substrates 360 and 361, each similar to substrates 320 and 340, are pressed against the heat sink separately by mounting screws in an insulating support housing 382 (similar to housing 350 in FIG. 15). Substrates 360 and 361 are contained in separate openings 363 and 364, respectively (FIGS. 17 and 18), and their upper surfaces are exposed through openings 370 and 371 in PCB 372. PCB 372 is mounted within housing 382 and is secured to housing 382 by screws 390, 391, 392, and 393 that pass through bosses that extend integrally from housing 382. Boss 395 and 396 for screws 391 and 393 are shown in FIG. 17, respectively.

図１６、図１７、および図１８の組立ての後、基板、シリコンダイ、ＰＣＢ、および端子（図示せず）をワイアボンディングし、または相互接続することができる。   After assembly of FIGS. 16, 17, and 18, the substrate, silicon die, PCB, and terminals (not shown) can be wire bonded or interconnected.

図１９に、図１６、図１７、および図１８よりも長く、かつ狭い絶縁シェル内で、縦方向に一列になった基板３６０および３６１の構成を示す。この構成により、ＰＣＢ３７２をシェル３８２に固定するためのねじ４００、４０１、および４０２の使用数を少なくすることが可能となる。   FIG. 19 shows the configuration of substrates 360 and 361 that are vertically aligned in an insulating shell that is longer and narrower than that of FIGS. With this configuration, it is possible to reduce the number of screws 400, 401, and 402 used to fix the PCB 372 to the shell 382.

以上、例示および説明のために本発明の好ましい実施形態を説明した。本発明を完全に開示の厳密な形態にすること、または本発明を開示の厳密な形態に限定することは意図されない。上記の教示に照らして、多数の修正形態および変形形態が可能である。本発明の範囲はこの詳細な説明に限定されず、頭記の特許請求の範囲によって限定されるものとする。   In the foregoing, preferred embodiments of the present invention have been described for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

パワー半導体ダイを装着するためにＩＭＳ基板を使用する従来技術のモジュールの上面図である。1 is a top view of a prior art module that uses an IMS substrate to mount a power semiconductor die. FIG. 図１の切断線２−２に沿う図１の断面図である。It is sectional drawing of FIG. 1 which follows the cutting line 2-2 of FIG. 図１の断面線２Ａ−２Ａに沿う図１の断面図である。It is sectional drawing of FIG. 1 which follows sectional line 2A-2A of FIG. 本発明の一特徴にしたがって変更された絶縁キャップを示す、図２の拡大図である。FIG. 3 is an enlarged view of FIG. 2 showing an insulating cap modified in accordance with one aspect of the present invention. 図１から図３のデバイスの構造と類似しているが、本発明の一特徴に従って変更された、図２の構造と類似する図である。FIG. 4 is a view similar to the structure of FIG. 2, similar to the structure of the device of FIGS. 1-3, but modified according to one aspect of the present invention. 本発明に従ってＰＣＢを変更する方式を示す図である。FIG. 6 is a diagram illustrating a method of changing a PCB according to the present invention. 図２Ａの断面図と類似しているが、本発明に従って絶縁シェルが除去された、デバイスのアセンブリの断面図である。2B is a cross-sectional view of the assembly of the device similar to the cross-sectional view of FIG. 2A but with the insulating shell removed in accordance with the present invention. 本発明に従って変更された、図１から図４のシェル構造の上面図である。5 is a top view of the shell structure of FIGS. 1-4 as modified in accordance with the present invention. FIG. 主絶縁シェルに装着すべき分離ヒートシンクのうちの１つの上面図である。FIG. 6 is a top view of one of the separate heat sinks to be attached to the main insulating shell. 図６のヒートシンクの側面図である。It is a side view of the heat sink of FIG. 別々のヒートシンクが定位置に接合された、図５の絶縁シェルの上面図である。FIG. 6 is a top view of the insulating shell of FIG. 5 with separate heat sinks joined in place. 図８の断面線９−９に沿う図８の断面図である。FIG. 9 is a sectional view of FIG. 8 taken along section line 9-9 of FIG. ３つのヒートシンクがそれぞれ、同じ電位の底部電極を有するＰチャネルＭＯＳＦＥＴおよびＮチャネルＭＯＳＦＥＴを受ける本発明の第２実施形態の上面図である。FIG. 6 is a top view of a second embodiment of the present invention in which three heat sinks each receive a P-channel MOSFET and an N-channel MOSFET having a bottom electrode of the same potential. 図１０の断面線１１−１１に沿う図１０の概略断面図である。It is a schematic sectional drawing of FIG. 10 which follows sectional line 11-11 of FIG. 本発明の別の実施形態の上面図である。It is a top view of another embodiment of the present invention. 従来の絶縁セラミックの上面図である。It is a top view of the conventional insulating ceramic. 図１３の断面線１４−１４に沿う図１３の断面図である。FIG. 14 is a sectional view of FIG. 13 taken along section line 14-14 of FIG. 13. いくつかの基板を絶縁シェルに装着する方式を断面図で示す図である。It is a figure which shows the system which attaches several board | substrates to an insulation shell with sectional drawing. 本発明に従って作成されたＰＣＢおよび基板アセンブリの上面図である。1 is a top view of a PCB and substrate assembly made in accordance with the present invention. FIG. 図１６の断面線１７−１７に沿う図１６の断面図である。FIG. 17 is a cross-sectional view of FIG. 16 taken along section line 17-17 of FIG. 図１６の断面線１８−１８に沿う図１６の断面図である。FIG. 19 is a cross-sectional view of FIG. 16 taken along section line 18-18 of FIG. 本発明の別の実施形態の、図１６と同様の図である。FIG. 17 is a view similar to FIG. 16 of another embodiment of the present invention.

Claims (12)

底面と頂面をそれぞれ有する複数のパワー半導体ダイと、該パワー半導体ダイのそれぞれの前記底面を受ける複数の熱伝導性半導体ダイ支持基板と、該熱伝導性半導体ダイ支持基板を支持する絶縁支持シェルと、前記複数のパワー半導体ダイの動作を制御する制御回路を上に含むプリント回路板との組合せを備え、
前記プリント回路板は、その平面内に、前記熱伝導性半導体ダイ支持基板の平面に対して平行に配設されるとともに、間隔を置いて配置された複数の開口を有し、
前記絶縁支持シェルは、前記プリント回路板の各開口に対してそれぞれ心合せされる複数の同一平面上の開口を有し、
前記複数の熱伝導性半導体ダイ支持基板は、前記絶縁支持シェル内の前記開口のそれぞれに配設および固定されるように、前記絶縁支持シェルに取り付けられているとともに、前記絶縁支持シェルによって互いに電気的に絶縁され、
ワイアボンドは、前記プリント回路板の前記開口を通じて延び、前記制御回路を前記パワー半導体ダイのそれぞれに接続する
ことを特徴とするパワー半導体デバイスモジュール。A plurality of power semiconductor dies each having a bottom surface and a top surface, a plurality of thermally conductive semiconductor die support substrates that receive the respective bottom surfaces of the power semiconductor dies , and an insulating support shell that supports the thermally conductive semiconductor die support substrate And a combination with a printed circuit board including a control circuit on the top for controlling the operation of the plurality of power semiconductor dies,
The printed circuit board, in its plane, while being disposed parallel to the plane of the thermally conductive semiconductor die supporting substrate has a plurality of openings spaced,
The insulating support shell has a plurality of coplanar openings that are respectively aligned with the openings of the printed circuit board;
Wherein the plurality of thermally conductive semiconductor die supporting substrate, said to be disposed and fixed to each of the openings in the insulating support shell, with is attached to the insulating support shell, electric each other by the insulating support shell Insulated and
A wire bond extends through the opening in the printed circuit board and connects the control circuit to each of the power semiconductor dies. 前記複数の熱伝導性半導体ダイ支持基板は、それぞれ導電性ヒートシンクであり、前記複数のパワー半導体ダイのうち少なくとも１つは、前記導電性ヒートシンクのそれぞれの上面に取り付けられることを特徴とする請求項１に記載のパワー半導体デバイスモジュール。  The plurality of thermally conductive semiconductor die support substrates are each conductive heat sinks, and at least one of the plurality of power semiconductor dies is attached to an upper surface of each of the conductive heat sinks. 2. The power semiconductor device module according to 1. 前記複数の熱伝導性半導体ダイ支持基板は、それぞれ導電性上面領域を有する電気的絶縁基板を備え、前記複数のパワー半導体ダイのうち少なくとも１つは、前記電気的絶縁基板のそれぞれの前記導電性上面に取り付けられ、前記電気的絶縁基板のそれぞれは、前記電気的絶縁基板の底面と熱的に連絡する前記導電性ヒートシンクを受けるように適合されていることを特徴とする請求項１に記載のパワー半導体デバイスモジュール。  The plurality of thermally conductive semiconductor die support substrates each include an electrically insulating substrate having an electrically conductive upper surface region, and at least one of the plurality of power semiconductor dies is each electrically conductive of the electrically insulating substrate. 2. The electrically conductive heat sink of claim 1, wherein the electrically insulating substrate is attached to a top surface and each of the electrically insulating substrates is adapted to receive the conductive heat sink in thermal communication with the bottom surface of the electrically insulating substrate. Power semiconductor device module. 前記熱伝導性半導体ダイ支持基板のそれぞれは、正方形の上面を有することを特徴とする請求項１、２、または３に記載のパワー半導体デバイスモジュール。  4. The power semiconductor device module according to claim 1, wherein each of the thermally conductive semiconductor die support substrates has a square upper surface. 前記熱伝導性半導体ダイ支持基板のそれぞれは、細長い長方形の表面を有することを特徴とする請求項１、２、または３に記載のパワー半導体デバイスモジュール。  4. The power semiconductor device module according to claim 1, wherein each of the thermally conductive semiconductor die support substrates has an elongated rectangular surface. 前記熱伝導性半導体ダイ支持基板のそれぞれは、前記熱伝導性半導体ダイ支持基板の頂面で、間隔を置いて配置された少なくとも２つのパワー半導体ダイを受け、前記各熱伝導性半導体ダイ支持基板上の前記少なくとも２つのパワー半導体ダイは、前記パワー半導体ダイの底面で電気的に接続されていることを特徴とする請求項１、２、または３に記載のパワー半導体デバイスモジュール。  Each of the thermally conductive semiconductor die support substrates receives at least two power semiconductor dies spaced from each other on a top surface of the thermally conductive semiconductor die support substrate, and each of the thermally conductive semiconductor die support substrates. The power semiconductor device module according to claim 1, wherein the at least two power semiconductor dies are electrically connected to each other at a bottom surface of the power semiconductor die. 前記熱伝導性半導体ダイ支持基板のそれぞれは、前記熱伝導性半導体ダイ支持基板の頂面で、間隔を置いて配置された少なくとも２つのパワー半導体ダイを受け、前記各熱伝導性半導体ダイ支持基板表面上の前記少なくとも２つのパワー半導体ダイは、前記パワー半導体ダイの底面で電気的に接続されていることを特徴とする請求項５に記載のパワー半導体デバイスモジュール。  Each of the thermally conductive semiconductor die support substrates receives at least two power semiconductor dies spaced from each other on a top surface of the thermally conductive semiconductor die support substrate, and each of the thermally conductive semiconductor die support substrates. The power semiconductor device module according to claim 5, wherein the at least two power semiconductor dies on the surface are electrically connected to each other at a bottom surface of the power semiconductor die. ヒートシンクの表面によって係合可能な底面と、少なくとも１つのパワー半導体ダイを表面対表面の接触で受ける頂面とを有する薄い平坦な熱伝導性基板を備えるパワー半導体デバイスモジュールであって、
前記少なくとも１つのパワー半導体ダイ上には制御電極を有し、
プリント回路板は、該プリント回路板上に、前記少なくとも１つのパワー半導体ダイを制御するための電気的構成要素を有するとともに、前記熱伝導性基板の形状に応じた形状の開口を有し、かつ、前記熱伝導性基板の平面に平行な平面に配設され、前記熱伝導性基板の上方に位置し、
前記プリント回路板の前記平面は、前記熱伝導性基板の平面に密に隣接し、それによって前記熱伝導性基板の頂面と前記プリント回路板の頂面は、前記熱伝導性基板の厚さの２倍未満だけ離間し、
少なくとも１つのワイアボンドは、前記プリント回路板上の前記電気的構成要素のうち少なくとも１つから、前記プリント回路板の前記開口を通じて、前記パワー半導体ダイ上の前記制御電極に延びて接続し、
前記熱伝導性基板を支持する絶縁シェルは、前記熱伝導性基板の周辺縁の周りで該熱伝導性基板の前記底面を前記ヒートシンク側に向けて露出し、前記熱伝導性基板の前記底面と係合する前記ヒートシンクの投影メサを受ける開口を有し、
前記絶縁シェルの上面は、前記プリント回路板の底面を受けて支持することを特徴とするパワー半導体デバイスモジュール。A power semiconductor device module comprising a thin flat thermally conductive substrate having a bottom surface engageable by a surface of a heat sink and a top surface that receives at least one power semiconductor die in surface-to-surface contact,
A control electrode on the at least one power semiconductor die;
Printed circuit board, in the printed circuit board, which has an electrical component for controlling the at least one power semiconductor die having an opening of a shape corresponding to the shape of the thermally conductive substrate, and , it is disposed in a plane parallel to the plane of the thermally conductive substrate, located above side of the thermally conductive substrate,
The plane of the printed circuit board is closely adjacent to the plane of the thermally conductive substrate so that the top surface of the thermally conductive substrate and the top surface of the printed circuit board are the thickness of the thermally conductive substrate. Separated by less than 2 times,
At least one wire bond extends from and connects to at least one of the electrical components on the printed circuit board through the opening in the printed circuit board to the control electrode on the power semiconductor die;
Insulating shell for supporting the thermally conductive substrate, the bottom surface of the thermally conductive substrate around the circumferential edge of the thermally conductive substrate exposed toward the heat sink side, and the bottom surface of the thermally conductive substrate An opening for receiving a projection mesa of the heat sink to engage;
The power semiconductor device module, wherein an upper surface of the insulating shell receives and supports a bottom surface of the printed circuit board. 前記プリント回路板の頂部に配設され、前記開口の領域を封入し、前記パワー半導体ダイの頂部に誘電液充填体を構成する絶縁キャップをさらに備えたことを特徴とする請求項８に記載のパワー半導体デバイスモジュール。 9. The insulation circuit according to claim 8, further comprising an insulating cap disposed on a top of the printed circuit board, enclosing the region of the opening, and forming a dielectric liquid filling on the top of the power semiconductor die. Power semiconductor device module. 前記熱伝導性基板の周辺上面の少なくとも一部は、前記プリント回路板の前記開口に隣接する前記プリント回路板の底部の周辺部分と対応するように固定されていることを特徴とする請求項８または９に記載のパワー半導体デバイスモジュール。9. The at least part of the peripheral upper surface of the thermally conductive substrate is fixed so as to correspond to the peripheral portion of the bottom of the printed circuit board adjacent to the opening of the printed circuit board. Or a power semiconductor device module according to 9; 前記熱伝導性基板の前記周辺面とプリント回路板は、互いに接着剤で固定されていることを特徴とする請求項１０に記載のパワー半導体デバイスモジュール。The power semiconductor device module according to claim 10, wherein the peripheral surface of the thermally conductive substrate and the printed circuit board are fixed to each other with an adhesive. 前記プリント回路板は、複数の間隔を置いて配置された開口を有し、前記絶縁シェルは、前記プリント回路板の前記開口のうちの１つにそれぞれ心合せされる複数の同一平面上の開口を有し、前記複数の熱伝導性基板は、各々少なくとも１つの前記パワー半導体ダイを搭載するとともに、前記絶縁シェルの前記開口のうちの１つにそれぞれ配設および固定され、前記絶縁シェルによって互いに電気的に絶縁され、ワイアボンド手段は、前記開口を通じて延び、前記各制御電極手段を前記パワー半導体ダイのうちの１つにそれぞれ接続することを特徴とする請求項８に記載のパワー半導体デバイスモジュール。The printed circuit board has a plurality of spaced openings, and the insulating shell is a plurality of coplanar openings each aligned with one of the openings of the printed circuit board. The plurality of thermally conductive substrates each mounted with at least one of the power semiconductor dies, and disposed and fixed to one of the openings of the insulating shell, respectively. 9. A power semiconductor device module according to claim 8, wherein electrically insulated and wire bond means extend through said opening and connect each of said control electrode means to one of said power semiconductor dies, respectively.
JP2003502885A 2001-05-30 2001-05-30 Power semiconductor device module Expired - Fee Related JP4051027B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2001/017415 WO2002099878A1 (en) 2001-05-30 2001-05-30 Power semiconductor module

Publications (2)

Publication Number Publication Date
JP2004529505A JP2004529505A (en) 2004-09-24
JP4051027B2 true JP4051027B2 (en) 2008-02-20

Family

ID=21742610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003502885A Expired - Fee Related JP4051027B2 (en) 2001-05-30 2001-05-30 Power semiconductor device module

Country Status (3)

Country Link
JP (1) JP4051027B2 (en)
DE (1) DE10196942B4 (en)
WO (1) WO2002099878A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4583191B2 (en) * 2005-01-28 2010-11-17 三菱電機株式会社 Rotating electric machine
JP2007012857A (en) * 2005-06-30 2007-01-18 Renesas Technology Corp Semiconductor device
JP5103445B2 (en) * 2009-06-30 2012-12-19 パナソニック株式会社 Induction heating cooker
JP2012199596A (en) * 2012-07-25 2012-10-18 Mitsubishi Electric Corp Semiconductor module
WO2014052616A2 (en) * 2012-09-27 2014-04-03 The Trustees Of The University Of Pennsylvania Insulated nanoelectrode-nanopore devices and related methods
CN104835794B (en) * 2015-03-23 2018-02-02 广东美的制冷设备有限公司 SPM and its manufacture method
DE102019206523A1 (en) 2019-05-07 2020-11-12 Zf Friedrichshafen Ag Power module with housed power semiconductors for controllable electrical power supply to a consumer
DE102019218157A1 (en) * 2019-11-25 2021-05-27 Zf Friedrichshafen Ag Power module with housed power semiconductors for the controllable electrical power supply of a consumer and a method for production

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5012386A (en) * 1989-10-27 1991-04-30 Motorola, Inc. High performance overmolded electronic package
US5287247A (en) * 1990-09-21 1994-02-15 Lsi Logic Corporation Computer system module assembly
JP3058047B2 (en) * 1995-04-04 2000-07-04 株式会社日立製作所 Sealed cooling structure of multi-chip module
DE19645636C1 (en) * 1996-11-06 1998-03-12 Telefunken Microelectron Power module for operating electric motor with speed and power control
US6060772A (en) * 1997-06-30 2000-05-09 Kabushiki Kaisha Toshiba Power semiconductor module with a plurality of semiconductor chips
US6147869A (en) * 1997-11-24 2000-11-14 International Rectifier Corp. Adaptable planar module
JP3547333B2 (en) * 1999-02-22 2004-07-28 株式会社日立産機システム Power converter

Also Published As

Publication number Publication date
JP2004529505A (en) 2004-09-24
DE10196942B4 (en) 2009-09-03
WO2002099878A1 (en) 2002-12-12
DE10196942T5 (en) 2004-04-22

Similar Documents

Publication Publication Date Title
US6272015B1 (en) Power semiconductor module with insulation shell support for plural separate substrates
US6424026B1 (en) Power module with closely spaced printed circuit board and substrate
US6313598B1 (en) Power semiconductor module and motor drive system
US5767573A (en) Semiconductor device
KR100307465B1 (en) Power module
US6690087B2 (en) Power semiconductor module ceramic substrate with upper and lower plates attached to a metal base
US7759778B2 (en) Leaded semiconductor power module with direct bonding and double sided cooling
US6703703B2 (en) Low cost power semiconductor module without substrate
KR101505551B1 (en) Semiconductor power module package with temperature sensor mounted thereon and method of fabricating the same
WO2016031462A1 (en) Power semiconductor module
US7859079B2 (en) Power semiconductor device
JPH10178151A (en) Power module for controlling electric motor
JP4465906B2 (en) Power semiconductor module
JP4051027B2 (en) Power semiconductor device module
US20070145576A1 (en) Power Semiconductor Circuit And Method Of Manufacturing A Power Semiconductor Circuit
JP3740329B2 (en) Component mounting board
JP2001085613A (en) Transfer mold power module
WO2022056679A1 (en) Power module and manufacturing method therefor, converter, and electronic device
JP2000196011A (en) Electronic device and manufacture thereof
JPH11307721A (en) Power module device and manufacture therefor
WO2020254143A1 (en) Half-bridge power assembly
JPH11220074A (en) Semiconductor device
JP2003133514A (en) Power module
JP2004048084A (en) Semiconductor power module
CN114556554A (en) Substrate, packaging structure and electronic equipment

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050802

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050816

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051108

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061114

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070109

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071116

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071130

R150 Certificate of patent or registration of utility model

Ref document number: 4051027

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101207

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101207

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111207

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111207

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121207

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131207

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees