JP3973615B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3973615B2
JP3973615B2 JP2003354439A JP2003354439A JP3973615B2 JP 3973615 B2 JP3973615 B2 JP 3973615B2 JP 2003354439 A JP2003354439 A JP 2003354439A JP 2003354439 A JP2003354439 A JP 2003354439A JP 3973615 B2 JP3973615 B2 JP 3973615B2
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semiconductor
semiconductor element
carrier
resin
electrode
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JP2005123277A (en
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年隆 赤星
康司 竹村
嘉昭 竹岡
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a laminated semiconductor device capable of preventing the insufficient filling and excess protrusion of a thermosetting-resin sheet, when even the insulating thermosetting-resin sheet interposed between a semiconductor carrier and a semiconductor element is deformed and sealed with a resin, in a heating pressure process in which the semiconductor element is flip-chip mounted on the semiconductor carrier. <P>SOLUTION: The first semiconductor element 8 is flip-chip mounted on the semiconductor carrier 4 by using the thermosetting-resin sheet 5 in which a central section is pressured and deformed in a recessed shape, regarding the manufacturing method for the semiconductor device in which a plurality of the semiconductor elements are laminated. It means that the quantities of a resin at the central sections of sides with a lot of the quantities of the protrusions are collected previously at corners with less quantities of the resin. The quantities of the protrusion up to the outside can be made smaller than the first semiconductor element 8, surely filling sections up to the corners of the first semiconductor element 8 with the resin in the case of a heating pressure. Accordingly, the miniaturized semiconductor device with improved reliability can be obtained stably and easily. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

本発明は複数の半導体素子を積層した半導体装置の製造方法に関し、特にフリップチップ方式の接合とワイヤーボンディング方式の接合とを用いた半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device in which a plurality of semiconductor elements are stacked, and more particularly to a method for manufacturing a semiconductor device using flip-chip bonding and wire bonding bonding.

携帯情報機器等の小型、軽量化に伴って、半導体装置パッケージの高密度化、小型化、薄型化が要求されている。これらの要求に応えるために、半導体素子を重ねて多段に搭載した積層型の半導体装置が開発されているが、より小型化を実現するためには、フリップチップ方式の接合とワイヤーボンディング方式の接合とを用いた半導体装置が有利であり、フリップチップ方式の接合では半導体素子と半導体キャリアとの間隙に素子表面の保護を目的とした樹脂封止が行なわれている（たとえば特許文献１参照）。   As portable information devices and the like become smaller and lighter, semiconductor device packages are required to have higher density, smaller size, and thinner thickness. In order to meet these demands, multi-layered semiconductor devices with multiple stacked semiconductor elements have been developed. To achieve further miniaturization, flip chip bonding and wire bonding bonding are used. In flip-chip bonding, resin sealing is performed in the gap between the semiconductor element and the semiconductor carrier for the purpose of protecting the element surface (for example, see Patent Document 1).

従来の積層型半導体装置の製造方法を説明する。
まず、図４(ａ)に示すような、搭載しようとする第１および第２の半導体素子のための第１の電極１と第２の電極２と外部電極端子３とを備えた半導体キャリア４を準備し、半導体キャリア４の表面上に、図４(ｂ)に示すように、絶縁性の熱硬化性樹脂シート５を貼り付ける。 A conventional method for manufacturing a stacked semiconductor device will be described.
First, as shown in FIG. 4A, a semiconductor carrier 4 having a first electrode 1, a second electrode 2, and an external electrode terminal 3 for the first and second semiconductor elements to be mounted. Is prepared, and an insulating thermosetting resin sheet 5 is attached on the surface of the semiconductor carrier 4 as shown in FIG.

次に、図４(ｃ)に示すように、第１半導体素子８を半導体キャリア４上に位置合わせして搭載し、加熱・加圧力によって、第１半導体素子８のバンプ９と半導体キャリア４の第１の電極１とを接続するとともに、熱硬化性樹脂シート５を第１半導体素子８・半導体キャリア４間の間隙に充填し、余分な樹脂を第２の電極２に被らない様に第１の半導体素子８の外側に押し出す。この熱硬化性樹脂シート５が硬化後に第１封止樹脂となる。   Next, as shown in FIG. 4C, the first semiconductor element 8 is mounted in alignment on the semiconductor carrier 4, and the bumps 9 of the first semiconductor element 8 and the semiconductor carrier 4 are formed by heating and pressing force. The first electrode 1 is connected and the thermosetting resin sheet 5 is filled in the gap between the first semiconductor element 8 and the semiconductor carrier 4 so that the second resin 2 is not covered with excess resin. 1 is pushed out of the semiconductor element 8. This thermosetting resin sheet 5 becomes the first sealing resin after curing.

次に、図４(ｄ)に示すように、第２の半導体素子１０を第１の半導体素子８の裏面に搭載し、図４(ｅ)に示すように、第２の半導体素子１０の電極（図示せず）と半導体キャリア４上の第２の電極２とをワイヤ１１でワイヤーボンディング接続する。その後に、図４(ｆ)に示すように、半導体キャリア４に実装された第１の半導体素子８と第２の半導体素子１０とワイヤ１１の領域を覆うように封止樹脂１２でモールドする。これにより半導体装置の製造が完了する。このようにして搭載する第１の半導体素子８と第２の半導体素子１０の組み合わせには、特に制限はなく、アナログＩＣとマイコンＩＣであってもよいし、アナログＩＣ同士であってもよい。   Next, as shown in FIG. 4D, the second semiconductor element 10 is mounted on the back surface of the first semiconductor element 8, and as shown in FIG. 4E, the electrodes of the second semiconductor element 10 are mounted. (Not shown) and the second electrode 2 on the semiconductor carrier 4 are connected by wire bonding with a wire 11. Thereafter, as shown in FIG. 4 (f), molding is performed with a sealing resin 12 so as to cover the regions of the first semiconductor element 8, the second semiconductor element 10 and the wire 11 mounted on the semiconductor carrier 4. Thereby, the manufacture of the semiconductor device is completed. The combination of the first semiconductor element 8 and the second semiconductor element 10 mounted in this manner is not particularly limited, and may be an analog IC and a microcomputer IC, or may be analog ICs.

以上の製造工程の中で、図４(ｃ)により説明した、熱硬化性樹脂シート５を加圧して第１の半導体素子８の外側にはみ出す程度に変形させる際に、第１の半導体素子８と半導体キャリア４との間隙に未充填をなくし、またはみ出し量を少なくすることが、半導体装置の信頼性を確保し、かつ、半導体装置の小型化を実現するうえで重要となる。   In the above manufacturing process, when the thermosetting resin sheet 5 described with reference to FIG. 4C is pressed and deformed to the extent that it protrudes outside the first semiconductor element 8, the first semiconductor element 8. In order to ensure the reliability of the semiconductor device and to reduce the size of the semiconductor device, it is important to eliminate unfilling in the gap between the semiconductor carrier 4 and the amount of protrusion.

ところが、厚さが均一な熱硬化性樹脂シート５を加熱・加圧すると、図５および図６に示すように第１の半導体素子８（矩形）の外側に扇状に押し出される。熱硬化性樹脂シート５・半導体素子８間の未充填を避けるために熱硬化性樹脂シート５のサイズを大きく設定すると、図５に示すように、第１の半導体素子８の辺中央付近のはみ出し量が大きくなってしまい、この熱硬化性樹脂シート５が被らない様に第２の電極位置２０７をその分だけ遠く配置しなければならず、結果、半導体装置が大きくなってしまう。逆に熱硬化性樹脂シート５のサイズを小さく設定すると、図６に示すように、第１の半導体素子８の辺中央付近からのはみ出し量は少なくなるものの、第１の半導体素子８のコーナー部が未充填になってしまい、第１の半導体素子８の電気的接続の信頼性が低下してしまう。
特開平１１−２１９９８４号公報 However, when the thermosetting resin sheet 5 having a uniform thickness is heated and pressurized, it is pushed out in a fan shape outside the first semiconductor element 8 (rectangle) as shown in FIGS. When the size of the thermosetting resin sheet 5 is set large in order to avoid unfilling between the thermosetting resin sheet 5 and the semiconductor element 8, as shown in FIG. The amount becomes large, and the second electrode position 207 must be arranged so far away that the thermosetting resin sheet 5 is not covered. As a result, the semiconductor device becomes large. Conversely, when the size of the thermosetting resin sheet 5 is set small, the amount of protrusion from the vicinity of the center of the side of the first semiconductor element 8 is reduced as shown in FIG. Becomes unfilled, and the reliability of the electrical connection of the first semiconductor element 8 decreases.
JP-A-11-219984

本発明は上記した従来の問題を解決するもので、半導体キャリア上に半導体素子をフリップチップ実装する加熱加圧工程で、両者間に介在させた絶縁性熱硬化性樹脂シートを変形させることで樹脂封止する際に、前記熱硬化性樹脂シートの充填不足および過剰なはみ出しを防止できる半導体装置の製造方法を提供することを目的とする。   The present invention solves the above-described conventional problems, and in a heating and pressurizing process in which a semiconductor element is flip-chip mounted on a semiconductor carrier, the insulating thermosetting resin sheet interposed therebetween is deformed to form a resin. An object of the present invention is to provide a semiconductor device manufacturing method capable of preventing insufficient filling and excessive protrusion of the thermosetting resin sheet during sealing.

上記課題を解決するために、本発明の半導体装置の製造方法は、半導体キャリアの素子実装領域に絶縁性の熱硬化性樹脂シートを設置する工程と、前記熱硬化性樹脂シートを加圧して凹型に変形させる工程と、第１の半導体素子のバンプ電極と前記半導体キャリアの第１の電極とを位置合わせし、加熱および加圧することにより、前記第１の半導体素子と前記半導体キャリアとを電気的に接続させるとともに、前記第１の半導体素子と前記半導体キャリアとの間隙に介在する前記熱硬化性樹脂シートを変形および硬化させて前記間隙を樹脂封止する工程と、前記第１の半導体素子の上に第２の半導体素子を積層する工程と、前記第２の半導体素子の電極端子と前記第１の半導体素子の実装領域の周囲の前記半導体キャリア上に形成された第２の電極とをボンディングワイヤを介して電気接続する工程と、前記第１の半導体素子、前記第２の半導体素子および前記ボンディングワイヤを覆うように封止樹脂でモールドする工程とを行なうことを特徴とする。このように熱硬化性シートを予め凹型に変形させておくことにより、第１の半導体素子のコーナー部まで確実に樹脂を充填しながら、第１の半導体素子よりも外側までのはみ出し量を小さくすることができ、小型化、高信頼性化された半導体装置を安定かつ、容易に得ることが可能になる。 In order to solve the above problems, a method of manufacturing a semiconductor device of the present invention includes the steps of placing a semi-conductor thermosetting resin sheet insulating the element mounting area of the carrier, the thermosetting resin sheet pressure a step of deforming the concave mold by applying, the bump electrodes of the first semiconductor element by aligning the first electrode of the semiconductor carrier, by heating and pressing, the said first semiconductor element semiconductor carrier And electrically sealing the gap by deforming and curing the thermosetting resin sheet interposed in the gap between the first semiconductor element and the semiconductor carrier; and a step of on a semiconductor element stacking a second semiconductor element, a second formed on the second of said electrode terminals of the semiconductor element and the first surrounding mounting region of the semiconductor element of the semiconductor carrier A step of electrically connecting the electrodes via a bonding wire, and the first semiconductor element, characterized by performing the step of molding a sealing resin so as to cover the second semiconductor element and the bonding wire . By deforming the thermosetting sheet into a concave shape in advance as described above, the amount of protrusion to the outside of the first semiconductor element is reduced while reliably filling the resin up to the corner of the first semiconductor element. Therefore, it is possible to stably and easily obtain a miniaturized and highly reliable semiconductor device.

３個以上の半導体素子を積層するには、第２の半導体素子の電極端子と半導体キャリア上の第２の電極とをボンディングワイヤを介して電気接続する工程の後に、最上層の半導体素子の上に別途の半導体素子を積層する工程と、前記別途の半導体素子の電極端子と第１の半導体素子の実装領域の周囲の前記半導体キャリア上に予め形成された所定の電極とをボンディングワイヤを介して電気接続する工程とを、所望回数だけ行い、その後に、積層された各半導体素子と前記ボンディングワイヤとを覆うように封止樹脂でモールドする工程を行なうようにすればよい。 In order to stack three or more semiconductor elements, after the step of electrically connecting the electrode terminal of the second semiconductor element and the second electrode on the semiconductor carrier via a bonding wire, A step of laminating a separate semiconductor element, and an electrode terminal of the separate semiconductor element and a predetermined electrode formed in advance on the semiconductor carrier around the mounting region of the first semiconductor element via a bonding wire The step of electrical connection may be performed as many times as desired, and then the step of molding with a sealing resin so as to cover each of the stacked semiconductor elements and the bonding wire may be performed.

本発明の半導体装置の製造方法は、フリップチップ＋ワイヤボンディングを用いて積層型半導体装置を構成する際に、第１の半導体素子をフリップチップ実装する際の熱と圧力で流動させる熱硬化性樹脂シートを予め凹状に変形させるようにしたため、流動した樹脂を第１の半導体素子のコーナー部まで確実に充填しながら、第１の半導体素子よりも外周側へのはみ出し量を小さくすることができ、小型化、高信頼性化された半導体装置を安定かつ、容易に得ることが可能になる。   A method of manufacturing a semiconductor device according to the present invention includes a thermosetting resin that is made to flow by heat and pressure when a first semiconductor element is flip-chip mounted when a stacked semiconductor device is configured using flip chip + wire bonding. Since the sheet was deformed into a concave shape in advance, the amount of protrusion to the outer peripheral side of the first semiconductor element can be reduced while reliably filling the fluidized resin up to the corner of the first semiconductor element, It is possible to stably and easily obtain a miniaturized and highly reliable semiconductor device.

以下、本発明の実施の形態について、図面を参照しながら説明する。
（第１の実施の形態）
図１および図２は本発明の第１の実施の形態における半導体装置の製造方法を説明する工程断面図である。製造しようとする半導体装置は先に図４を用いて説明した半導体装置と同様の構成を有するものである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
1 and 2 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention. The semiconductor device to be manufactured has the same configuration as the semiconductor device described above with reference to FIG.

図１（ａ）に示すように、半導体キャリア４の一側面に設定された素子実装領域（図中の中央部）の周縁部に、搭載する第１の半導体素子のバンプ電極を接続するための第１電極１が形成され、前記素子実装領域の周囲に第２の半導体素子の電極端子を接続するための第２電極２が形成されている。半導体キャリア４の他側面には外部電極端子３が一定の間隔で格子状に形成されている。   As shown in FIG. 1A, a bump electrode of a first semiconductor element to be mounted is connected to a peripheral part of an element mounting region (center part in the figure) set on one side of the semiconductor carrier 4. A first electrode 1 is formed, and a second electrode 2 for connecting an electrode terminal of a second semiconductor element is formed around the element mounting region. External electrode terminals 3 are formed in a lattice pattern at regular intervals on the other side surface of the semiconductor carrier 4.

この半導体キャリア４の素子実装領域の中央部に、図１（ｂ）に示すように、絶縁性の熱硬化性樹脂シート５を貼り付ける。ここで、半導体キャリア４として、多層セラミック基板、ガラス布積層エポキシ基板（ガラエポ基板）、アラミド不織布基板、ガラス布積層ポリイミド樹脂基板などを用いることができる。樹脂シート５は、シリカなどの無機系フィラーを入れたもの(例えば、エポキシ樹脂、フェノール樹脂、ポリイミドなど)、無機系フィラーを全く入れないもの(例えば、エポキシ樹脂、フェノール樹脂、ポリイミドなど)が好適に使用できるとともに、後工程のリフロー工程での高温に耐えうる程度の耐熱性（例えば、２４０℃に１０秒間耐えうる程度の耐熱性）を有するものが好適に使用できる。このような樹脂シート５を所望のサイズにカットして所定位置に配置し、例えば８０〜１２０℃に熱せられた貼付けツールにより例えば５〜１０ｋｇｆ／ｃｍ2程度の圧力で半導体キャリアに貼付ける。 As shown in FIG. 1B, an insulating thermosetting resin sheet 5 is attached to the center of the element mounting region of the semiconductor carrier 4. Here, as the semiconductor carrier 4, a multilayer ceramic substrate, a glass cloth laminated epoxy substrate (glass epoxy substrate), an aramid nonwoven fabric substrate, a glass cloth laminated polyimide resin substrate, or the like can be used. The resin sheet 5 is preferably one containing an inorganic filler such as silica (for example, epoxy resin, phenol resin, polyimide, etc.) or one not containing any inorganic filler (eg, epoxy resin, phenol resin, polyimide, etc.). In addition, those having heat resistance that can withstand high temperatures in the subsequent reflow process (for example, heat resistance that can withstand 240 ° C. for 10 seconds) can be suitably used. Such a resin sheet 5 is cut into a desired size, placed at a predetermined position, and attached to a semiconductor carrier with a pressure of, for example, about 5 to 10 kgf / cm 2 by an application tool heated to 80 to 120 ° C., for example.

次に、図１（ｃ）に示すように、熱硬化性樹脂シート５の中央部を金属製のほぼ円柱状の冶具６などで加圧することにより、中央部の樹脂量をシートコーナー部に寄せる。このとき例えば、熱硬化性樹脂シート５のゲル化温度が９０度である場合には９０度に加熱することで、冶具６による加圧が開放されたあとでも、所望の形状を保つことが出来る。   Next, as shown in FIG.1 (c), the center part of the thermosetting resin sheet 5 is pressed with the metal substantially cylindrical jig 6 etc., and the resin amount of a center part is brought near to a sheet | seat corner part. . At this time, for example, when the gelation temperature of the thermosetting resin sheet 5 is 90 degrees, the desired shape can be maintained even after the pressurization by the jig 6 is released by heating to 90 degrees. .

その際に、熱硬化性樹脂シート５が外方へ広がってしまわないように、四角筒状の冶具７を用いて熱硬化性シート５の外周を拘束する。またその際の加圧は、熱硬化性樹脂シート５の中央部の厚みが所望の接合高さ（第１半導体素子の下面と半導体キャリア４の上面との所望の最終距離）以上となるように行なう。たとえば熱硬化性樹脂シート５の初期厚みが５０μmで、所望の接合高さが４０μmである場合には、熱硬化性樹脂シート５の中央部の厚みが４０μm以上になるように治具６を加圧制御する。図１（ｄ）は、加圧によって熱硬化性シート５が凹型に変形した状態を示す断面図、図１（ｅ）は同じく上面図である。   At that time, the outer periphery of the thermosetting sheet 5 is constrained using a square cylindrical jig 7 so that the thermosetting resin sheet 5 does not spread outward. In addition, the pressurization at that time is such that the thickness of the central portion of the thermosetting resin sheet 5 is equal to or greater than a desired bonding height (a desired final distance between the lower surface of the first semiconductor element and the upper surface of the semiconductor carrier 4). Do. For example, when the initial thickness of the thermosetting resin sheet 5 is 50 μm and the desired joining height is 40 μm, the jig 6 is added so that the thickness of the central portion of the thermosetting resin sheet 5 is 40 μm or more. Pressure control. FIG.1 (d) is sectional drawing which shows the state which the thermosetting sheet 5 deform | transformed into the concave shape by pressurization, FIG.1 (e) is a top view similarly.

次に、図２（ａ）に示すように、第1の半導体素子８のバンプ電極９と半導体キャリア４の第１の電極１とを位置合わせし、加熱および加圧することにより、バンプ電極９を変形させながら第１の電極１に電気的に接続させるとともに、第1の半導体素子８と半導体キャリア４との間に介在する熱硬化性シート５を変形させて両者間の間隙に充填し、余分な樹脂を第1の半導体素子８の外側へ押し出す、という樹脂封止を行なう。   Next, as shown in FIG. 2 (a), the bump electrode 9 of the first semiconductor element 8 and the first electrode 1 of the semiconductor carrier 4 are aligned, heated and pressurized, whereby the bump electrode 9 is formed. While being deformed, it is electrically connected to the first electrode 1, and the thermosetting sheet 5 interposed between the first semiconductor element 8 and the semiconductor carrier 4 is deformed to fill the gap between them, and the extra Resin sealing is performed by extruding a new resin to the outside of the first semiconductor element 8.

その際に、上述したように熱硬化性シート５の中央部の樹脂量を予め、樹脂量が少なくなるシートコーナー部に寄せているので、従来のようにコーナー部での広がりが少ないために扇状に広がる現象は発生しない。このため、図２（ｂ）の平面図に示すように、第１の半導体素子８のコーナー部に樹脂の未充填部分が発生することなく、少ないはみ出し量を実現できる。上述したように熱硬化性シート５の中央部の厚みを所望の接合高さ以上に設定しているので、樹脂に内部ボイドが発生することもない。   At that time, as described above, since the resin amount at the center of the thermosetting sheet 5 is preliminarily moved to the sheet corner portion where the resin amount is reduced, the fan-shaped because the spread at the corner portion is small as in the past. The phenomenon that spreads out does not occur. For this reason, as shown in the plan view of FIG. 2B, a small protrusion amount can be realized without generating an unfilled portion of the resin in the corner portion of the first semiconductor element 8. As described above, since the thickness of the central portion of the thermosetting sheet 5 is set to be equal to or higher than a desired bonding height, internal voids are not generated in the resin.

その後に、図２（ｃ）に示すように、第1の半導体素子８の上に第２の半導体素子１０を搭載する。さらにその後に、図２（ｄ）に示すように、第２の半導体素子１０の電極端子（図示せず）と、第１の半導体素子８の実装領域の外側の第２の電極２とをボンディングワイヤ１１を介してワイヤーボンディング方式により電気接続する。最後に、図２（ｅ）に示すように、第１の半導体素子８と第２の半導体素子１０とボンディングワイヤ１１の領域を覆うように封止樹脂１２でモールドする。   Thereafter, as shown in FIG. 2C, the second semiconductor element 10 is mounted on the first semiconductor element 8. Further thereafter, as shown in FIG. 2D, the electrode terminal (not shown) of the second semiconductor element 10 and the second electrode 2 outside the mounting region of the first semiconductor element 8 are bonded together. Electrical connection is made through the wire 11 by a wire bonding method. Finally, as shown in FIG. 2E, the first semiconductor element 8, the second semiconductor element 10, and the bonding wire 11 are molded with a sealing resin 12 so as to cover the regions.

以上のように、熱硬化性シート５を予め凹型に変形させておくことにより、第１の半導体素子８と半導体キャリア４との間隙に第１の半導体素子８のコーナー部まで確実に樹脂充填しながら、第１の半導体素子８よりも外側へのはみ出し量を従来よりも小さくすることができ、小型化、高信頼性化された半導体装置を安定かつ、容易に得ることができる。   As described above, by deforming the thermosetting sheet 5 into a concave shape in advance, the gap between the first semiconductor element 8 and the semiconductor carrier 4 is surely filled with the resin up to the corner of the first semiconductor element 8. However, the amount of protrusion to the outside of the first semiconductor element 8 can be made smaller than before, and a semiconductor device that is downsized and highly reliable can be obtained stably and easily.

たとえば、搭載する第1の半導体素子８がサイズ１０ｍｍ□（１０ｍｍ×１０ｍｍの矩形；以下同様に記す）で、所望の接合高さが４０μmである場合、第1の半導体素子８と半導体キャリア４との間に未充填部分が発生しないようにするには、理論的には、熱硬化性シート５として初期厚さ５０μm、初期サイズ９ｍｍ□のものを用いればよいことが体積計算される。   For example, when the first semiconductor element 8 to be mounted has a size of 10 mm □ (10 mm × 10 mm rectangle; similarly described below) and a desired junction height is 40 μm, the first semiconductor element 8 and the semiconductor carrier 4 In order to prevent an unfilled portion from being generated between the two, it is theoretically calculated that the thermosetting sheet 5 having an initial thickness of 50 μm and an initial size of 9 mm □ may be used.

実際に、１０ｍｍ□サイズの第1の半導体素子８に対し、初期厚さ５０μm、初期サイズ９ｍｍ□の熱硬化性シート５を、上記実施の形態に記載したように予め凹状に変形させて介在させておき、最終接合高さ４０μmまで加圧したところ、熱硬化性シート５の変形・広がりは概ね第1の半導体素子８と同等サイズに抑えられ、未充填の発生はなく、はみ出し量も少なかった。このため、半導体キャリア４において、第２の電極２を第1の半導体素子８の搭載領域の近傍に配置することが可能になり、半導体装置の小型化を実現可能な結果となった。   Actually, the thermosetting sheet 5 having an initial thickness of 50 μm and an initial size of 9 mm □ is interposed in the first semiconductor element 8 having a size of 10 mm □, deformed in advance into a concave shape as described in the above embodiment. In addition, when the final bonding height was increased to 40 μm, the deformation / expansion of the thermosetting sheet 5 was suppressed to approximately the same size as the first semiconductor element 8, no unfilling occurred, and the amount of protrusion was small. . For this reason, in the semiconductor carrier 4, the second electrode 2 can be disposed in the vicinity of the mounting region of the first semiconductor element 8, and the semiconductor device can be downsized.

これに対して従来の方法では、同じ１０ｍｍ□サイズの第1の半導体素子８に対して用いて最終接合高さ４０μmまで変形させるには、熱硬化性シート５は第１の半導体素子８とほぼ同じ初期サイズ（１０ｍｍ□）、初期厚さ５０μmが必要である。初期段階で第１の半導体素子８と同じサイズでないと、広がりの少ないコーナー部に未充填が発生するからである。この場合、第1の半導体素子８の辺中央部からのはみ出し量は約０．８ｍｍになる。半導体キャリア４においてこのはみ出し量より外側に第２の電極２を設ける必要があることを考えると、半導体装置のサイズは余計に大きくなってしまう。
（第２の実施の形態）
図３は本発明の第２の実施の形態における半導体装置の製造方法を説明する工程断面図である。この第２の実施の形態の方法は上記した第１の実施の形態の方法とほぼ同様なので、第１の実施と同様の構成を有する部材に図１と同じ符号を付して、詳細な説明を省略する。 On the other hand, in the conventional method, the thermosetting sheet 5 is almost the same as the first semiconductor element 8 in order to be deformed to the final junction height of 40 μm using the same 10 mm □ -sized first semiconductor element 8. The same initial size (10 mm □) and initial thickness of 50 μm are required. This is because if the size is not the same as the size of the first semiconductor element 8 in the initial stage, unfilled corner portions are not filled. In this case, the amount of protrusion from the center of the side of the first semiconductor element 8 is about 0.8 mm. Considering that it is necessary to provide the second electrode 2 outside the protrusion amount in the semiconductor carrier 4, the size of the semiconductor device becomes excessively large.
(Second Embodiment)
FIG. 3 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Since the method of the second embodiment is substantially the same as the method of the first embodiment described above, the same reference numerals as those in FIG. Is omitted.

この第２の実施の形態の方法が、上記した第１の実施の形態の方法と相違するのは、熱硬化性樹脂シートを貼り付け、かつ、凹型に変形させるために、図３（ｂ）（ｃ）に示す搭載ツール２０を用いた点である。   The method of the second embodiment is different from the method of the first embodiment described above in order to attach the thermosetting resin sheet and deform it into a concave shape as shown in FIG. This is a point using the mounting tool 20 shown in FIG.

搭載ツール２０は、熱硬化性シート５の外周を拘束する筒状冶具２１の上端に、熱硬化性シート５を吸着する吸着治具２２を取り付け、この吸着治具２２に熱硬化性シート５を加圧する加圧冶具２３を昇降自在に保持した構造である。筒状冶具２１，加圧冶具２３は第１の実施の形態で説明した筒状冶具７，加圧冶具６と同様の形状である。   The mounting tool 20 attaches an adsorption jig 22 that adsorbs the thermosetting sheet 5 to the upper end of a cylindrical jig 21 that restrains the outer periphery of the thermosetting sheet 5, and attaches the thermosetting sheet 5 to the adsorption jig 22. In this structure, the pressurizing jig 23 to be pressed is held up and down. The cylindrical jig 21 and the pressure jig 23 have the same shape as the cylindrical jig 7 and the pressure jig 6 described in the first embodiment.

吸着治具２２は、加圧冶具２３を昇降自在に保持した中央穴２２ａおよびその周囲に貫設された複数の吸着穴２２ｂを有し、筒状冶具２１よりも小さい端面を有した柱状部材２２ｃと、この柱状部材２２ｃを保持し、柱状部材２２ｃの端面および中央穴２２ａが筒状冶具２１と同心をなすように筒状冶具２１の上端に取り付けられたフレーム部材２２ｄとからなる。   The suction jig 22 has a central hole 22a that holds the pressure jig 23 so as to be movable up and down, and a plurality of suction holes 22b that penetrate the periphery thereof, and a columnar member 22c that has an end surface smaller than the cylindrical jig 21. And a frame member 22d attached to the upper end of the tubular jig 21 so that the end surface of the columnar member 22c and the central hole 22a are concentric with the tubular jig 21.

柱状部材２２ｃはフレーム部材２２ｄよりも上方および下方へ突出していて、柱状部材２２ｃの下端面のみが熱硬化性シート５に当接し、かつ、柱状部材２２ｃとフレーム部材２２ｄとの間に所定の間隙が形成されるようになっている。筒状冶具２１の下端から柱状部材２２ｃの下端面までの距離も、熱硬化性シート５の厚みと同等の距離に設定されている。   The columnar member 22c protrudes upward and downward from the frame member 22d, only the lower end surface of the columnar member 22c abuts on the thermosetting sheet 5, and a predetermined gap is provided between the columnar member 22c and the frame member 22d. Is to be formed. The distance from the lower end of the cylindrical jig 21 to the lower end surface of the columnar member 22 c is also set to a distance equivalent to the thickness of the thermosetting sheet 5.

このような搭載ツール２０を用いることにより、熱硬化性シート５の貼り付けおよび変形の工程を第１の実施の形態と同様に、しかもより容易に、短時間で行なうことが可能になり、生産性の向上を実現できる。   By using the mounting tool 20 as described above, it is possible to perform the process of attaching and deforming the thermosetting sheet 5 more easily and in a short time as in the first embodiment. Can improve the performance.

実際にはまず、図３（ａ）に示した半導体キャリア４の素子実装領域の中央部に、図３（ｂ）に示すように熱硬化性シート５を吸着穴２２ｂで吸着した冶具１０７を設置し、吸着解除することにより、熱硬化性シート５を貼り付ける。   Actually, first, a jig 107 for adsorbing the thermosetting sheet 5 through the adsorbing holes 22b as shown in FIG. 3B is installed at the center of the element mounting area of the semiconductor carrier 4 shown in FIG. 3A. Then, the thermosetting sheet 5 is pasted by releasing the adsorption.

その状態で、図３（ｃ）に示すように、加圧冶具２３を徐々に降下させることにより、熱硬化性シート５の外周を筒状冶具７で拘束しながら、中央部を加圧して、中央部の樹脂量をシートコーナー部に寄せる。図３（ｄ）は、加圧によって熱硬化性シート５が凹型に変形した状態を示す。   In that state, as shown in FIG. 3 (c), by gradually lowering the pressure jig 23, the central portion is pressurized while restraining the outer periphery of the thermosetting sheet 5 with the cylindrical jig 7, Move the resin amount in the center to the seat corner. FIG.3 (d) shows the state which the thermosetting sheet 5 deform | transformed into the concave shape by pressurization.

以降の工程は第１の実施の形態と同様なので説明を省略する。
なお、図示を省略するが、３個以上の半導体素子を積層するには、第２の半導体素子１０の電極端子と半導体キャリア上の第２の電極２とをボンディングワイヤ１１を介して電気接続する工程の後に、第２の半導体素子１０の上に別途の半導体素子を積層する工程と、この半導体素子の電極端子と前記第１の半導体素子８の実装領域の周囲の半導体キャリア４上に予め形成された所定の電極とをボンディングワイヤを介して電気接続する工程とを、所望回数だけ行い、その後に、積層された各半導体素子と前記ボンディングワイヤとを覆うように封止樹脂１２でモールドする工程を行なうようにすればよい。積層する半導体素子は順次に上に配置してもよいし、１つの半導体素子の上に並列に複数個配置してもよい。 Subsequent steps are the same as those in the first embodiment, and a description thereof will be omitted.
Although not shown, in order to stack three or more semiconductor elements, the electrode terminal of the second semiconductor element 10 and the second electrode 2 on the semiconductor carrier are electrically connected via a bonding wire 11. After the step, a step of laminating a separate semiconductor element on the second semiconductor element 10, and an electrode terminal of this semiconductor element and a semiconductor carrier 4 around the mounting region of the first semiconductor element 8 are formed in advance. A step of electrically connecting the predetermined electrodes to each other through a bonding wire, and then molding with a sealing resin 12 so as to cover the stacked semiconductor elements and the bonding wires. Should be done. The semiconductor elements to be stacked may be sequentially arranged on top, or a plurality of semiconductor elements may be arranged in parallel on one semiconductor element.

本発明の半導体装置の製造方法は、フリップチップ方式で半導体素子を接合させる積層型半導体装置などの製造方法として有用である。   The method for manufacturing a semiconductor device of the present invention is useful as a method for manufacturing a stacked semiconductor device or the like in which semiconductor elements are joined by a flip chip method.

本発明の第１実施形態における半導体装置の製造方法の前半の工程を説明する工程断面図Process sectional drawing explaining the process of the first half of the manufacturing method of the semiconductor device in 1st Embodiment of this invention. 本発明の第１実施形態における半導体装置の製造方法の後半の工程を説明する工程断面図Process sectional drawing explaining the latter process of the manufacturing method of the semiconductor device in 1st Embodiment of this invention. 本発明の第２実施形態における半導体装置の製造方法を説明する工程断面図Process sectional drawing explaining the manufacturing method of the semiconductor device in 2nd Embodiment of this invention 従来の半導体装置の製造方法を説明する工程断面図Process sectional drawing explaining the manufacturing method of the conventional semiconductor device 図４に示した方法で製造される半導体装置の平面図FIG. 4 is a plan view of a semiconductor device manufactured by the method shown in FIG. 図４に示した方法で、サイズの異なる樹脂シートを用いて製造される半導体装置の平面図FIG. 4 is a plan view of a semiconductor device manufactured using resin sheets of different sizes by the method shown in FIG.

符号の説明Explanation of symbols

１：第1の電極
２：第２の電極
３：外部電極端子
４：半導体キャリア
５：熱硬化性シート
６：加圧冶具
７：せき止め用の筒状冶具
８：第１の半導体素子
９：バンプ
１０：第２の半導体素子
１１：ワイヤ
１２：封止樹脂 1: First electrode 2: Second electrode 3: External electrode terminal 4: Semiconductor carrier 5: Thermosetting sheet 6: Pressure jig 7: Cylindrical jig 8 for damming: First semiconductor element 9: Bump 10: Second semiconductor element 11: Wire 12: Sealing resin

Claims (2)

半導体キャリアの素子実装領域に絶縁性の熱硬化性樹脂シートを設置する工程と、
前記熱硬化性樹脂シートを加圧して凹型に変形させる工程と、
第１の半導体素子のバンプ電極と前記半導体キャリアの第１の電極とを位置合わせし、加熱および加圧することにより、前記第１の半導体素子と前記半導体キャリアとを電気的に接続させるとともに、前記第１の半導体素子と前記半導体キャリアとの間隙に介在する前記熱硬化性樹脂シートを変形および硬化させて前記間隙を樹脂封止する工程と、
前記第１の半導体素子の上に第２の半導体素子を積層する工程と、
前記第２の半導体素子の電極端子と前記第１の半導体素子の実装領域の周囲の前記半導体キャリア上に形成された第２の電極とをボンディングワイヤを介して電気接続する工程と、
前記第１の半導体素子、前記第２の半導体素子および前記ボンディングワイヤを覆うように封止樹脂でモールドする工程とからなる半導体装置の製造方法。 The element mounting area of the semi-conductor carrier comprising the steps of placing the thermosetting resin sheet of insulation,
A step of deforming the concave mold pressurizes the thermosetting resin sheet,
The bump electrode of the first semiconductor element and the first electrode of the semiconductor carrier are aligned, heated and pressurized to electrically connect the first semiconductor element and the semiconductor carrier, and Deforming and curing the thermosetting resin sheet interposed in the gap between the first semiconductor element and the semiconductor carrier and resin-sealing the gap;
Laminating a second semiconductor element over the first semiconductor element,
Electrically connecting an electrode terminal of the second semiconductor element and a second electrode formed on the semiconductor carrier around a mounting region of the first semiconductor element via a bonding wire ;
A method of manufacturing a semiconductor device, comprising: molding with a sealing resin so as to cover the first semiconductor element , the second semiconductor element, and the bonding wire. 第２の半導体素子の電極端子と半導体キャリア上の第２の電極とをボンディングワイヤを介して電気接続する工程の後に、
最上層の半導体素子の上に別途の半導体素子を積層する工程と、前記別途の半導体素子の電極端子と第１の半導体素子の実装領域の周囲の前記半導体キャリア上に予め形成された所定の電極とをボンディングワイヤを介して電気接続する工程とを、所望回数だけ行い、
その後に、積層された各半導体素子と前記ボンディングワイヤとを覆うように封止樹脂でモールドする工程を行なう請求項１記載の半導体装置の製造方法。 After the step of electrically connecting the electrode terminal of the second semiconductor element and the second electrode on the semiconductor carrier via a bonding wire,
A step of laminating a separate semiconductor element on the uppermost semiconductor element, and a predetermined electrode formed in advance on the semiconductor carrier around the electrode terminal of the separate semiconductor element and the mounting region of the first semiconductor element And the step of electrically connecting the two through a bonding wire, a desired number of times,
The method of manufacturing a semiconductor device according to claim 1, wherein a step of molding with a sealing resin is performed so as to cover each of the stacked semiconductor elements and the bonding wire.
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