JP3950854B2 - 低電気抵抗を有する金属含有薄層の製造方法 - Google Patents
低電気抵抗を有する金属含有薄層の製造方法 Download PDFInfo
- Publication number
- JP3950854B2 JP3950854B2 JP2003586916A JP2003586916A JP3950854B2 JP 3950854 B2 JP3950854 B2 JP 3950854B2 JP 2003586916 A JP2003586916 A JP 2003586916A JP 2003586916 A JP2003586916 A JP 2003586916A JP 3950854 B2 JP3950854 B2 JP 3950854B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- layer
- grain size
- conductor
- heating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
Description
Claims (10)
- 低電気抵抗を有する微細パターニング導体路を製造する方法であって、
該方法は、
a)第1のグレインサイズを有する金属含有の微細にパターニングされた導体路(5A)をキャリア材料(1,2,3,4)上に形成する工程
を包含し、
b)該第1のグレインサイズより大きい第2のグレインサイズを有する導体路(5C)を生成することを目的として該導体路(5A)の再結晶化が実行されるように、該金属含有の微細にパターニングされた導体路(5A)において、摂氏150度から摂氏450度の温度を有する局所限定加熱領域(W)を生成および移動させる工程をさらに包含することを特徴とする、方法。 - 前記微細にパターニングされた導体路(5,5A,5C)は、0.2μmより小さい特徴寸法を有することを特徴とする、請求項1に記載の方法。
- 前記工程a)において、前記導体路(5)が第1の方向(x)および/または該第1の方向と実質的に垂直な第2の方向(y)に形成され、
前記工程b)において、前記加熱領域(W)の移動が、実質的に該第1の方向(x)および/または該第2の方向(y)に、あるいは該第1および第2の方向(x,y)に対して45度の角度で実行されることを特徴とする、請求項1または2に記載の方法。 - 前記工程b)が繰り返し実行されることを特徴とする、請求項1から3のいずれか一項に記載の方法。
- 前記工程b)において、前記局所限定加熱領域(W)は、扇形レーザ光、熱気体、複数の加熱ランプおよび/または加熱ワイヤによって生成されることを特徴とする、請求項1から4のいずれか一項に記載の方法。
- 前記局所限定加熱領域(W)は、ストライプ形状、あるいは点形状に形成されていることを特徴とする、請求項1から5のいずれか一項に記載の方法。
- 前記工程a)において、前記導体路(5)は、5%未満の不純物率を有する金属合金あるいはドープされた金属を有することを特徴とする、請求項1から6のいずれか一項に記載の方法。
- 前記キャリア材料は、拡散バリア層(3)および/またはシード層(4)を有することを特徴とする、請求項1から7のいずれか一項に記載の方法。
- 前記工程a)において、ダマシン法が実行されることを特徴とする、請求項1から8のいずれか一項に記載の方法。
- 前記再結晶化が保護ガス雰囲気中で実行されることを特徴とする、請求項1からの9いずれか一項に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10217876A DE10217876A1 (de) | 2002-04-22 | 2002-04-22 | Verfahren zur Herstellung dünner metallhaltiger Schichten mit geringem elektrischen Widerstand |
PCT/DE2003/001205 WO2003090257A2 (de) | 2002-04-22 | 2003-04-10 | Verfahren zur herstellung dünner metallhaltiger schichten mit geringem elektrischen widerstand |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005532675A JP2005532675A (ja) | 2005-10-27 |
JP3950854B2 true JP3950854B2 (ja) | 2007-08-01 |
Family
ID=28798664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003586916A Expired - Fee Related JP3950854B2 (ja) | 2002-04-22 | 2003-04-10 | 低電気抵抗を有する金属含有薄層の製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20060005902A1 (ja) |
EP (1) | EP1497859B1 (ja) |
JP (1) | JP3950854B2 (ja) |
CN (1) | CN100367487C (ja) |
DE (2) | DE10217876A1 (ja) |
TW (1) | TWI237345B (ja) |
WO (1) | WO2003090257A2 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101273929B1 (ko) * | 2005-03-31 | 2013-06-11 | 글로벌파운드리즈 인크. | 감소된 일렉트로 및 스트레스 이주 및/또는 저항성을 갖는상호 연결 구조를 형성하기 위한 열 처리 |
US7375031B2 (en) | 2005-04-29 | 2008-05-20 | Advanced Micro Devices, Inc. | Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity |
DE102005020061B4 (de) * | 2005-03-31 | 2016-12-01 | Globalfoundries Inc. | Technik zur Herstellung von Verbindungsstrukturen mit reduzierter Elektro- und Stressmigration und/oder geringerem Widerstand |
US7335611B2 (en) * | 2005-08-08 | 2008-02-26 | Applied Materials, Inc. | Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer |
KR100881716B1 (ko) | 2007-07-02 | 2009-02-06 | 주식회사 하이닉스반도체 | 낮은 시트저항의 텅스텐막을 갖는 텅스텐배선 제조 방법 및그를 이용한 반도체소자의 게이트 제조 방법 |
JP5326386B2 (ja) * | 2008-07-10 | 2013-10-30 | 富士通株式会社 | 半導体装置およびその製造方法 |
US9230292B2 (en) * | 2012-11-08 | 2016-01-05 | Uber Technologies, Inc. | Providing on-demand services through use of portable computing devices |
US8492753B2 (en) * | 2010-09-28 | 2013-07-23 | Empire Technology Development Llc | Directionally recrystallized graphene growth substrates |
JP6163714B2 (ja) * | 2012-08-27 | 2017-07-19 | 富士通株式会社 | 半導体装置の製造方法および半導体装置 |
CA2896758C (en) * | 2012-12-31 | 2022-12-13 | Telvent Dtn Llc | Dynamic aircraft threat controller manager apparatuses, methods and systems |
US10417727B2 (en) * | 2016-09-26 | 2019-09-17 | Uber Technologies, Inc. | Network system to determine accelerators for selection of a service |
KR102540839B1 (ko) | 2018-08-20 | 2023-06-08 | 삼성전자주식회사 | 반도체 소자 및 그의 제조 방법 |
CN110265406A (zh) * | 2019-06-06 | 2019-09-20 | 深圳市华星光电技术有限公司 | 阵列基板及制作方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3585088A (en) * | 1968-10-18 | 1971-06-15 | Ibm | Methods of producing single crystals on supporting substrates |
US4059461A (en) * | 1975-12-10 | 1977-11-22 | Massachusetts Institute Of Technology | Method for improving the crystallinity of semiconductor films by laser beam scanning and the products thereof |
US4214918A (en) * | 1978-10-12 | 1980-07-29 | Stanford University | Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam |
US4309225A (en) * | 1979-09-13 | 1982-01-05 | Massachusetts Institute Of Technology | Method of crystallizing amorphous material with a moving energy beam |
US4680855A (en) * | 1984-10-29 | 1987-07-21 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device manufacturing methods |
JPH0793258B2 (ja) * | 1985-12-04 | 1995-10-09 | 富士通株式会社 | 導電体膜の再結晶化方法 |
US4758533A (en) * | 1987-09-22 | 1988-07-19 | Xmr Inc. | Laser planarization of nonrefractory metal during integrated circuit fabrication |
US4976809A (en) * | 1989-12-18 | 1990-12-11 | North American Philips Corp, Signetics Division | Method of forming an aluminum conductor with highly oriented grain structure |
JPH04271125A (ja) * | 1991-01-30 | 1992-09-28 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
JPH04280425A (ja) * | 1991-03-07 | 1992-10-06 | Sony Corp | 配線形成方法 |
JPH06310500A (ja) * | 1993-01-22 | 1994-11-04 | Toshiba Corp | 半導体装置の製造方法 |
TW281786B (ja) * | 1993-05-26 | 1996-07-21 | Handotai Energy Kenkyusho Kk | |
JP3517802B2 (ja) * | 1995-09-01 | 2004-04-12 | 富士通株式会社 | 埋め込み導電層の形成方法 |
US5882958A (en) * | 1997-09-03 | 1999-03-16 | Wanlass; Frank M. | Damascene method for source drain definition of silicon on insulator MOS transistors |
JPH11214387A (ja) * | 1998-01-22 | 1999-08-06 | Matsushita Electron Corp | 半導体装置およびその製造方法 |
JP3955386B2 (ja) * | 1998-04-09 | 2007-08-08 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6297154B1 (en) * | 1998-08-28 | 2001-10-02 | Agere System Guardian Corp. | Process for semiconductor device fabrication having copper interconnects |
-
2002
- 2002-04-22 DE DE10217876A patent/DE10217876A1/de not_active Ceased
-
2003
- 2003-04-09 TW TW092108174A patent/TWI237345B/zh not_active IP Right Cessation
- 2003-04-10 DE DE50313093T patent/DE50313093D1/de not_active Expired - Lifetime
- 2003-04-10 EP EP03722271A patent/EP1497859B1/de not_active Expired - Fee Related
- 2003-04-10 WO PCT/DE2003/001205 patent/WO2003090257A2/de active Application Filing
- 2003-04-10 CN CNB038089823A patent/CN100367487C/zh not_active Expired - Fee Related
- 2003-04-10 US US10/512,016 patent/US20060005902A1/en not_active Abandoned
- 2003-04-10 JP JP2003586916A patent/JP3950854B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO2003090257A3 (de) | 2004-01-15 |
DE50313093D1 (de) | 2010-10-28 |
JP2005532675A (ja) | 2005-10-27 |
TW200306644A (en) | 2003-11-16 |
WO2003090257A2 (de) | 2003-10-30 |
CN1647264A (zh) | 2005-07-27 |
CN100367487C (zh) | 2008-02-06 |
US20060005902A1 (en) | 2006-01-12 |
EP1497859B1 (de) | 2010-09-15 |
TWI237345B (en) | 2005-08-01 |
WO2003090257B1 (de) | 2004-03-04 |
DE10217876A1 (de) | 2003-11-06 |
EP1497859A2 (de) | 2005-01-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11348832B2 (en) | Self-aligned via interconnect structures | |
US20220115505A1 (en) | Copper-filled trench contact for transistor performance improvement | |
US7875977B2 (en) | Barrier layers for conductive features | |
KR100339179B1 (ko) | 상호 접속 구조 및 그 형성 방법 | |
US9679810B1 (en) | Integrated circuit having improved electromigration performance and method of forming same | |
JP3950854B2 (ja) | 低電気抵抗を有する金属含有薄層の製造方法 | |
US9754885B1 (en) | Hybrid metal interconnects with a bamboo grain microstructure | |
JP2004524684A (ja) | 多層の銅が超大規模集積回路に相互接続するための方法 | |
US20050170642A1 (en) | Methods for improving metal-to-metal contact in a via, devices made according to the methods, and systems including the same | |
US10811353B2 (en) | Sub-ground rule e-Fuse structure | |
US10008446B2 (en) | Advanced E-fuse structure with enhanced electromigration fuse element | |
US9893012B2 (en) | Advanced e-fuse structure with hybrid metal controlled microstructure | |
WO2022105639A1 (en) | Topological semi-metal interconnects | |
US11410926B2 (en) | E-fuse enhancement by underlayer layout design | |
US6756303B1 (en) | Diffusion barrier and method for its production | |
US20170154816A1 (en) | Amorphous metal interconnections by subtractive etch | |
US20220375859A1 (en) | E-Fuse Enhancement By Underlayer Layout Design | |
KR20090075501A (ko) | 반도체 소자의 금속배선 및 그 형성방법 | |
US20050224980A1 (en) | Interconnect adapted for reduced electron scattering | |
JPH1083980A (ja) | 半導体装置の製造方法 | |
US9761529B2 (en) | Advanced metallization for damage repair | |
KR100792408B1 (ko) | 싱글 다마신공정을 이용한 금속배선 형성 방법 | |
KR20110020484A (ko) | 반도체 소자의 금속배선 형성방법 | |
KR20050006468A (ko) | 반도체 소자의 구리 배선 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20061206 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20061211 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070307 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20070330 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20070423 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 3950854 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100427 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110427 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120427 Year of fee payment: 5 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130427 Year of fee payment: 6 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140427 Year of fee payment: 7 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |