JP3925319B2 - Semiconductor element - Google Patents

Semiconductor element Download PDF

Info

Publication number
JP3925319B2
JP3925319B2 JP2002173991A JP2002173991A JP3925319B2 JP 3925319 B2 JP3925319 B2 JP 3925319B2 JP 2002173991 A JP2002173991 A JP 2002173991A JP 2002173991 A JP2002173991 A JP 2002173991A JP 3925319 B2 JP3925319 B2 JP 3925319B2
Authority
JP
Japan
Prior art keywords
layer
parallel
conductivity type
region
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2002173991A
Other languages
Japanese (ja)
Other versions
JP2004022716A (en
Inventor
高広 佐藤
進 岩本
達司 永岡
泰彦 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2002173991A priority Critical patent/JP3925319B2/en
Publication of JP2004022716A publication Critical patent/JP2004022716A/en
Application granted granted Critical
Publication of JP3925319B2 publication Critical patent/JP3925319B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はオン状態では電流を流すとともに、オフ状態では空乏化する並列ｐｎ層からなる構造を備える半導体素子に関し、特にＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）等のソース、ドレイン間に等価的に内蔵されたダイオードを有する半導体素子に関する。
【０００２】
【従来の技術】
一般的にＭＯＳＦＥＴのソース、ドレイン間に等価的にダイオードが内蔵されており、そのダイオードの一方の例えばアノード電極は、一方の主表面のうち電流制御が行われる活性部にしか形成されないにもかかわらず、他方のカソード電極は活性部と耐圧構造部との主表面全体に形成されるため、内蔵ダイオードに順バイアスが印加された場合、耐圧構造部にも蓄積キャリアが存在する。
【０００３】
ダイオードの順方向バイアス状態から逆方向バイアス状態に遷移する過程において、逆回復過程を通る。これは内蔵ダイオードが順方向バイアス状態の時にドリフト領域中にキャリアが蓄積するため、逆バイアスにしても蓄積されたキャリアが消滅するまで短時間ではあるが、逆方向に電流が流れる現象である。
この逆回復過程において逆回復破壊が起きることがある。逆回復破壊は一般的に活性部と耐圧構造部との境界部分で発生し、破壊の原因は前記境界部分で発生する電界集中と電流集中による熱的破壊である。
【０００４】
電界集中は、アノード領域の終端部分に形成される円筒状態或いは球面状態のｐｎ接合が原因となっており、電流集中は、耐圧構造部に存在するキャリアが逆回復時にアノード電極に向かって流れることが原因である。
【０００５】
【発明が解決しようとする課題】
ＭＯＳＦＥＴの内蔵ダイオードの逆回復過程の問題は、ｎ型領域とｐ型領域とを交互に配置した並列ｐｎ層をもつ半導体素子で重大である。特に、特開２００１−２９８１９０号公報に開示されたような耐圧構造部にもｎ型領域とｐ型領域とを交互に配置した並列ｐｎ層をもつ半導体素子では、非常に大きな問題となる。
【０００６】
以下でｎまたはｐを冠した層や領域はそれぞれ電子、正孔を多数キャリアとする層や領域を意味している。また+ は比較的高不純物濃度の、- は比較的低不純物濃度の領域を意味している。
図１３は、ｎドリフト領域１およびｐ仕切り領域２からなる並列ｐｎ層２０を備えるＭＯＳＦＥＴの電流制御が行われる活性部５０と耐圧を維持する耐圧構造部６０とを示す部分断面図である。耐圧構造部６０にもｎドリフト領域２１およびｐ仕切り領域２２からなる並列ｐｎ層２３が形成されている。耐圧構造部６０のｎドリフト領域２１にはドリフト電流は殆ど流れないが、活性部５０の並列ｐｎ層２０との比較上仮にこのように呼ぶことにする。左端がチップの端である。但し図の煩雑化を避けるため、並列ｐｎ層２０、２３のｎドリフト領域およびｐ仕切り領域の数は減らしてある。
【０００７】
活性部５０では、低抵抗のｎ++ドレイン層１２の上にｎドリフト領域１およびｐ仕切り領域２とを交互に配置した並列ｐｎ層２０があり、そのｐ仕切り領域２の上にｐウェル領域３が形成され、そのｐウェル領域３の表面層に選択的にｎ+ソース領域６とｐ+コンタクト領域５とが形成されている。ｎドリフト領域１およびｐ仕切り領域２とは、例えば共に縦型層状であり、紙面に垂直方向に伸びている。
【０００８】
ｎドリフト領域１の上には不純物濃度の高いｎ表面ドリフト領域４が形成されている。ｎ表面ドリフト領域４とｎ+ソース領域６とに挟まれたｐウェル領域３の表面上にはゲート絶縁膜７を介してゲート電極層８が設けられている。ｎ+ソース領域６とｐ+コンタクト領域５との表面に共通に接触してソース電極１０が設けられ、ｎ++ドレイン層１２の裏面に接してドレイン電極１３が設けられている。９はゲート電極層８とソース電極１０とを絶縁する絶縁膜である。
【０００９】
耐圧構造部６０においてもｎ++ドレイン層１２の上にｎドリフト領域２１およびｐ仕切り領域２２とを交互に配置した並列ｐｎ構造部23があり、その上にフィールド絶縁膜１５が形成されている。ソース電極１０がフィールド絶縁膜１５上に延ばされて、フィールドプレート構造をなしている。チップの端にはｎチャネルストッパ領域14が形成されその表面に周縁電極１６が設けられている。ソース電極１０は内蔵ダイオードのアノード電極となり、ドレイン電極１３はカソード電極となる。
【００１０】
例えば６００ＶクラスのＭＯＳＦＥＴの場合、各部の基準的な寸法および不純物濃度は次のような値を取る。ｎ++ドレイン層１２の不純物濃度１×１０18ｃｍ-3、厚さ５μｍ、活性部５０のｎドリフト領域１およびｐ仕切り領域２の不純物濃度２．５７×１０15ｃｍ-3、厚さ４２μｍ、幅８μｍ、耐圧構造部６０の並列ｐｎ層２３の不純物濃度５×１０14ｃｍ-3である。
【００１１】
活性部５０と耐圧構造部６０の並列ｐｎ層２０、２３では、耐圧構造部６０の方が不純物濃度を低くして空乏層が広がり易くしているが、ほぼ同じでも良い。ｎドリフト領域1 、21およびｐ仕切り領域２、２２の領域幅は等しく、そのピッチは等しい（Ｐ１）。
図１３のような従来のＭＯＳＦＥＴ構造の場合、活性部50の並列ｐｎ構造部20では５０Ｖ程度の逆バイアスで完全に空乏化し、内蔵ダイオードの順バイアス時に蓄積されたキャリアは、逆回復過程にある時、ソース電極（アノード電極）１０から瞬時に掃き出される。
【００１２】
一方、耐圧構造部６０でのキャリアの掃き出しは逆電圧の増加とともに徐々に行われ、キャリアの掃き出しによる逆回復電流は、耐圧構造部６０の並列ｐｎ層２３のｐ仕切り領域22をソース電極１０側に流れ、電極が無いためさらに並列ｐｎ層２３の表面を流れる。そしてソース電極（アノード電極）１０が接触している部分（Ｅ部）に電流が集中し破壊する。
【００１３】
図１４（ａ）、（ｂ）はそれぞれこの時の逆回復時のキャリア電流密度とキャリア密度とのシミュレーション結果を、密度が高い程濃く示した濃淡図である。逆回復電流が最大の時点での密度を示している。
図１４より、耐圧構造部６０にキャリアが多く残り、ソース電極１０接触部（Ｅ部）付近に１×１０4Ａ／ｃｍ2程度の電流が集中することがわかる。尚、図の１ｅ4Ａ／ｃｍ2は、１×１０4Ａ／ｃｍを意味している。
【００１４】
同様の問題は、ゲートパッドの近傍でも起きる。図１５は従来のＭＯＳＦＥＴのゲートパッド１８近傍の部分断面図である。
ゲートパッド１８直下の並列ｐｎ層２７にもダイオードが内蔵されており、この内蔵ダイオードから逆回復過程で掃き出されるキャリアは行き場がなくなり、ゲートパッド１８直下の両側に形成されたｐウェル領域３に集中し、ときには破壊を招く。
【００１５】
このような問題に鑑み本発明の目的は、並列ｐｎ構造を備えるＭＯＳＦＥＴ等において内蔵ダイオードからの電流集中を防ぎ、逆回復耐量を向上させた半導体素子を提供することにある。
【００１６】
【課題を解決するための手段】
上記課題解決のため本発明の半導体素子は、第一と第二の主面と、第一と第二の主面にそれぞれ設けられた第一と第二の電極と、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層とを有し、並列ｐｎ層の第二の主面側の表面層に高濃度の第二導電型領域を含む活性領域と該活性領域を取り囲む耐圧構造部が形成され、その高濃度の第二導電型領域に第二の電極が接している半導体素子において、前記第一導電型低抵抗層と並列ｐｎ層との間に、第一導電型バッファ層を有し、前記第一導電型バッファ層は、前記第一導電型低抵抗層よりも高抵抗層であり、かつ並列ｐｎ層に比べ低抵抗層であるものとする。
【００１７】
そのようにすれば、内蔵ダイオードの順バイアス時に第一導電型バッファ層に蓄積されたキャリアが、電界分布により活性部の並列ｐｎ層の第二導電型仕切り領域に供給される。並列ｐｎ層の第二導電型仕切り領域にはキャリアが存在するため、耐圧構造部からのキャリア吐き出しによる逆回復電流は並列ｐｎ層と第二導電型ウェル領域の接合付近に集中することなく、第一導電型バッファ層、および活性部並列ｐｎ層の第二導電型仕切り領域を通して流れる。このため、ＭＯＳＦＥＴ等に内蔵されるダイオードの逆回復過程におけるアノード電極付近での電流集中を緩和し、破壊耐量を向上することができる。
【００１８】
また、並列ｐｎ層がキャリアライフタイムが異なる少なくとも二つの領域からなり、素子活性部の外側の耐圧構造部にライフタイムの短い領域を配置するものとする。
【００１９】
ライフタイムが、少なくとも二種類以上になるように制御された領域を有することにより、耐圧構造部を含むライフタイムの短い領域でのキャリア蓄積量が減少し、耐圧構造部からのキャリア吐き出しによる逆回復電流を低減することができる。このため、ＭＯＳＦＥＴ等に内蔵される内蔵ダイオードの逆回復過程におけるアノード電極付近での電流集中を緩和し、破壊耐量を向上することができる。
【００２０】
つまり、活性領域の外側の並列ｐｎ層のキャリアライフタイムが、活性領域の並列ｐｎ層のキャリアライフタイムより短く制御されていることが大事である。更に耐圧構造部に第一のピッチで配置した並列ｐｎ層の第一の部分と、第一のピッチより小さい第二のピッチで配置した並列ｐｎ層の第二の部分とを有していることがよい。
【００２１】
小さいピッチの部分は、空乏層が広がり易いので蓄積キャリアが分散され電流集中が起きにくくなる。耐圧構造部の外側に第一導電型のチャネルストッパ領域を配置すれば、表面の反転を防止するチャネルストッパとなる。更に、並列ｐｎ層の第二の部分の表面が厚い絶縁膜で覆われているものとする。
【００２２】
耐圧構造部は、厚い絶縁膜で覆われていることが多い。第一導電型のチャネルストッパ領域が、並列ｐｎ層の下方に形成されている第一導電型低抵抗層と連続させることにより、チップの側面もすべてドレイン電極１３と同電位にすることができるので、これにより素子の絶縁耐圧は安定化し、品質も向上する。
【００２３】
【発明の実施の形態】
以下に本発明の実施の形態を説明する。
〔実施例１〕
図３は本発明にかかる実施例１の超接合ＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。但し図の煩雑化を避けるため、並列ｐｎ構造２０、２３は減らしてある。以後も同様である。
【００２４】
図３において、図１３と同じ機能をもつ部分には同じ記号を付している。図１３と重複するが説明する。
１１は低抵抗のｎ+バッファ層、１２は低抵抗のｎ++ドレイン層、１は第一導電型ドリフト領域、２は第二導電型仕切り領域とからなる並列ｐｎ層２０である。表面層にはｐ仕切り領域２に連続してｐウェル領域３が形成されている。ｐウェル領域３の内部にｐ+コンタクト領域５及びｎ+ソース領域６が形成されている。ｎ+ソース領域６とｎドリフト領域１とに挟まれたｐウェル領域３の表面上にはゲート絶縁膜７を介して多結晶シリコンのゲート電極層８が、またｎ+ソース領域６とｐ+コンタクト領域５の表面に共通に接触するソース電極１０が設けられている。ｎ++ドレイン層１２の裏面にはドレイン電極１３が設けられている。１５は表面保護及び安定化のための酸化膜であり、例えば、熱酸化膜と燐シリカガラス（ＰＳＧ）からなる。ソース電極１０は図３のように層間絶縁膜９を介してゲート電極層８の上に延長されることが多い。図示しない部分でゲート電極層８上に金属膜のゲート電極が設けられる。
【００２５】
耐圧構造部６０の並列ｐｎ層２３のピッチは、活性部５０のものと同じピッチで形成されている。
ＭＯＳＦＥＴに内蔵されたダイオードの場合、ＭＯＳＦＥＴのソース電極１０がアノード電極に、ドレイン電極13がカソード電極となる。またＭＯＳＦＥＴのゲート電極はアノード電極に接続することが多い。
【００２６】
ｎドリフト領域１とｐ仕切り領域２との平面的な形状は、例えばともにストライプ状とする。ｎドリフト領域１とｐ仕切り領域２との平面的な形状は、他に一方が格子状や網状であり、他方がその中に挟まれた形状でもよい。
本実施例１での耐圧構造は、通常行われるフィールドプレート構造を備えているが、勿論ガードリング構造でもよい。
【００２７】
図３において、耐圧構造部６０の並列ｐｎ層２３に隣接して低抵抗のｎチャネルストッパ領域１４が配置されており、ｎチャネルストッパ領域１４はまた、ｎ+バッファ層１１を介してｎ++ドレイン層１２とつながっている。そして、半導体チップ側面全てがこのｎチャネルストッパ領域１４で覆われており、その表面に接触して周縁電極１６が設けられている。
【００２８】
このｎチャネルストッパ領域１４は、表面の反転を防止するチャネルストッパとなるだけでなく、チップの側面もすべてドレイン電極１３と同電位にすることができるので、これにより素子の絶縁耐圧は安定化し、品質も向上する。
但し、ｎチャネルストッパ領域１４が必ずチップの側面でなければならないわけではなく、ｎチャネルストッパ領域１４をはさんで反対側の半導体領域に別の半導体素子や半導体領域を形成することもできる。
【００２９】
本実施例ではｎ++ドレイン層１２上にｎ+バッファ層１１を形成することでＭＯＳＦＥＴの内蔵ダイオードの逆回復耐量を向上させることが可能となった。これは次のように説明できる。
内蔵ダイオードに順バイアスが印加されると活性部５０および耐圧構造部６０にはキャリアが蓄積する。逆回復過程に入ると蓄積していたキャリアが内蔵ダイオードへの逆バイアス印加により掃き出される。
【００３０】
このとき活性部は５０Ｖ程度の逆バイアスで完全に空乏化してしまうが、ｎ+バッファ層１１があることで順バイアス時にｎ+バッファ層１１に蓄積されたキャリアが電界分布により、活性部５０と耐圧構造部６０境界近傍の活性部５０の並列ｐｎ層２０のｐ型仕切り領域２に分散される。
このため、耐圧構造部６０からのキャリア掃き出しによる逆回復電流は、活性部50の並列ｐｎ層２０の端のｐ仕切り領域２付近に集中することなく、ｎ+バッファ層１１から活性部並列ｐｎ層２０のｐ仕切り領域２に分散されて流れる。従ってｐウェル領域３の接合付近での電流集中が抑えられ、逆回復耐量が向上する。
【００３１】
なお、例えば６００ＶクラスのＭＯＳＦＥＴの場合、各部の基準的な寸法および不純物濃度は次のような値を取る。ｎ++ドレイン層１２の不純物濃度１×１０18ｃｍ-3、厚さ５μｍ、ｎ+バッファ層１１の不純物濃度４×１０15ｃｍ-3、厚さ３０μｍ、ｎドリフト領域１およびｐ仕切り領域２の不純物濃度２．５７×１０15ｃｍ-3、厚さ４２μｍ、幅８μｍ、耐圧構造部60の並列ｐｎ層２３の不純物濃度５×１０14ｃｍ-3である。
【００３２】
ｎ+バッファ層11の不純物濃度は、ｎ++ドレイン層１２のそれより低く、並列ｐｎ層のそれより高い。なお、ｎ+バッファ層１１は、例えばエピタキシャル成長法により形成できる。図４は本実施例１のＭＯＳＦＥＴのゲートパッド近傍の部分断面図である。
本実施例では、ゲートパッド18の下方にもｎ+バッファ層１１が設けられている。これにより、内蔵ダイオードの逆回復過程において掃き出されたキャリアがｎ+バッファ層１１を通じて分散されるため、ゲートパッド１８直下の両側に形成されたｐウェル領域３への逆回復電流集中を緩和し、逆回復耐量を向上できる。
【００３３】
本実施例では、ゲートパッド１８直下にｐウェル領域３を設けていないが、ｐウェル領域３を設けてもよい。また、ゲートパッド１８直下の並列ｐｎ層は、活性部の並列ｐｎ層のピッチよりも狭くしたり、正味の不純物濃度を低くなるようにしても良い。
〔実施例２〕
図１は本発明にかかる実施例２のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００３４】
図３の第一の実施例との違いは、耐圧構造部６０の一部の並列ｐｎ層２３のピッチ（Ｐ２）が活性部50のそれ（Ｐ１）より小さいピッチで形成されている点である。具体的にはＰ２をＰ１の１／２とした。この部分は製造時にマスクの寸法を変えるだけで、他のｐｎ層部分と全く同様にして形成できる。
小さいピッチの部分は、フィールド絶縁膜１５上にソース電極１０が延びている付近までとした。耐圧構造部６０ではピッチが狭いので空乏層が広がり易いので蓄積キャリアが分散され電流集中が起きにくくなる。
【００３５】
この場合も実施例１と同様にｎ+バッファ層１１の不純物濃度は、ｎ++ドレイン層１２のそれより低く、並列ｐｎ層のそれより高い。そしてｎ+バッファ層１１の存在により、内蔵ダイオードの蓄積キャリアの吐き出しによる電流が活性部50の並列ｐｎ層２３のｐ仕切り領域２に分散され、電流集中が緩和される。
図２（ａ）、（ｂ）はそれぞれこの時の逆回復時のキャリア電流密度とキャリア密度とのシミュレーション結果を、密度が高い程濃く示した濃淡図でる。
【００３６】
図２より、ｎ+バッファ層１１の存在により内蔵ダイオードの蓄積キャリアが分散されていることおよび、キャリアの掃き出しによる電流が活性部５０の並列ｐｎ層２０のｐ型仕切り領域２に分散され、アノード電極１０の接触部（Ｅ部）付近への電流集中は、１×１０Ａ／ｃｍ2程度であり、電流集中が緩和されていることがわかる。
【００３７】
実際に試作した素子は、従来のＭＯＳＦＥＴの８倍以上の耐量を示した。〔実施例３〕
図５は本発明にかかる実施例３のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
図１の実施例２との違いは、耐圧構造部６０の並列ｐｎ層２３のピッチ（Ｐ２）が活性部５０のｐウェル領域３まで全部、活性部５０のそれ（Ｐ１）より小さいピッチで形成されている点である。
【００３８】
これにより、ｐウェル領域３の端付近で空乏層が広がり易いので蓄積キャリアが分散され電流集中が起きにくくなる。
この場合も実施例２と同様の効果が得られる。
〔実施例４〕
図６は本発明にかかる実施例４のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００３９】
図５の実施例３との違いは、耐圧構造部６０の表面側のみに活性部５０のそれ（Ｐ１）より小さいピッチ（Ｐ２）の並列ｐｎ層２３が形成されている点である。耐圧構造部６０ではピッチが狭いので空乏層が広がり易いので蓄積キャリアが分散され電流集中が起きにくくなる。
この場合も実施例３と同様の効果が得られる。
〔実施例５〕
図７は本発明にかかる実施例５のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００４０】
耐圧横造部６０の並列ｐｎ層２３の接合が波うっている場合である。例えば、ｐ型不純物の埋め込み拡散とエピタキシャル成長、熱処理を繰り返すなど、並列ｐｎ層２３の製造方法によってはｐｎ層２３の接合がこのようになることがある。
この場合も、実施例１と同様の効果が得られる。
〔実施例６〕
図８は本発明にかかる実施例６のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００４１】
耐圧構造部６０の並列ｐｎ層２３のｐ仕切り領域22が深さ方向に連続していない場合である。耐圧構造部６０の並列ｐｎ層２３のｎドリフト領域２１、ｐ仕切り領域２２については、一定電圧で空乏化するという条件の下にさまざまな不純物濃度、形状の組み合わせを取りうるので、このようなケースも考えられる。
〔参考例〕
図９は本発明にかかる参考例のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００４２】
実施例３との違いはｎ+バッファ層１１がない点である。このためこれまでの例のようなｎ+バッファ層１１を通じての内蔵ダイオードの逆回復電流の分散は起きない。
しかし、本実施例では、耐圧構造部６０の並列ｐｎ層２３のピッチ（Ｐ２）が活性部５０の並列ｐｎ層２０のピッチ（Ｐ１）より狭いため、耐圧構造部６０での並列ｐｎ層２３は活性部５０の並列ｐｎ層２０に対し正味の不純物濃度が低いことになる。
【００４３】
このため、活性部５０と耐圧構造部６０との境界部の並列ｐｎ層の電界が緩和され、電流集中の緩和により逆回復耐量が向上する。
図１０（ａ）、（ｂ）はそれぞれこの時の逆回復時のキャリア電流密度とキャリア密度とのシミュレーション結果を、密度が高い程濃く示した濃淡図でる。
図１０より、内蔵ダイオードの蓄積キャリアは広い範囲に分散されていることおよび、キャリアの掃き出しによるアノード電極付近（Ｅ部）への電流集中が緩和されていることがわかる。電流集中は、２×１０Ａ／ｃｍ2程度であったので、電流集中が緩和されていることがわかる。
【００４４】
実際に試作した素子は、従来のＭＯＳＦＥＴの５倍以上の耐量を示した。〔実施例７〕
図１１は本発明にかかる実施例７のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
この実施例７のＭＯＳＦＥＴでは、耐圧構造部６０の並列ｐｎ層２３内に、ライフタイムが短く制御されたライフタイム調整領域２４が設けられている点が特徴であり、ハッチングで示されている。
【００４５】
このライフタイムが短い調整領域２４は、耐圧構造部６０の並列ｐｎ層２３と活性部５０の最外周部のｐウェル領域３との接合領域及び、活性部５０の最外周部のｐウェル領域３とアノード電極１０とが接する領域を含む領域に、形成されている。
内蔵ダイオードの逆回復電流が集中するのは、図１４に示したように、活性部50の最外周部のｐウェル領域３と隣接する耐圧構造部６０の並列ｐｎ層２３のｐ仕切り領域２２であった。
【００４６】
従って、この領域をライフタイムの短い領域とすれば、逆回復時に耐圧構造部から吐き出されるキャリアは、そのライフタイムの短い領域中で再結合し、電流集中が緩和され逆回復耐量が向上する。
このようなライフタイムの短い領域は、電子線照射、ヘリウムイオン照射やプロトン照射のような粒子線を利用した結晶欠陥導入法を用いることで、容易に形成できる。本実施例ではｎ++ドレイン層１２側から、電子線を加速電圧４．８ＭｅＶ、約１６０キログレイ（ｋｇｒｙ）照射した。条件により１００〜５００ｋｇｒｙの範囲で調節すると良い。
【００４７】
すなわち、ヘリウムイオンやプロトンの阻止能力のある材料（例えば、アルミニウム金属、厚いレジスト膜）を用いて、ライフタイムを短くしたい部分に窓が開けられた構造のマスクを作製する。そして、このマスク上部に対して垂直な方向から粒子線を照射する。
本実施例のように並列ｐｎ層の深さ全体にライフタイムの短い領域を形成する場合は、照射深さを並列ｐｎ層の厚さよりも深い部分にして、ヘリウムイオンあるいはプロトンを通過させても良いし、照射深さを変えて数回に分けて照射を分けて行うことにより結晶欠陥を導入しても良い。
【００４８】
実際に試作した素子は、従来のＭＯＳＦＥＴの８倍以上の逆回復耐量を示した。
なお、このようなライフタイムを短く制御した領域２４は、活性領域５０を含まず耐圧構造部６０のみであるため、順電圧（オン電圧）の上昇はない。〔実施例８〕
図１２は本発明にかかる実施例８のＭＯＳＦＥＴの部分断面図であり、図の左側が耐圧構造部である。
【００４９】
実施例７では耐圧構造部６０の一部にライフタイムの短い領域２４を形成したが、図１２のように耐圧構造部６０全体にわたってライフタイムの短い領域２４にしてもよい。
また以上の実施例の方法を組み合わせることにより、複合効果が得られ、逆回復耐量を向上できることはもちろんである。
【００５０】
なお、本実施例はＭＯＳＦＥＴの内蔵ダイオードで記載されているが、フリーホィールダイオード、ショットキーダイオード等でも同様な効果が得られる。
【００５１】
【発明の効果】
以上説明したように本発明によれば、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層と、並列ｐｎ層の第二の主面側の表面層に第二導電型領域を含む活性領域と該活性領域を取り囲む耐圧構造部が形成され、その第二導電型領域に第二の電極が接している半導体素子において、第一導電型低抵抗層と並列ｐｎ層との間に、第一導電型低抵抗層よりも高抵抗層でありかつ並列ｐｎ層に比べ低抵抗層である第一導電型バッファ層を設け、或いは、耐圧構造部に第一のピッチで配置した並列ｐｎ層の第一の部分とピッチの異なる並列ｐｎ層の第二の部分を設け、若しくは、耐圧構造部の並列ｐｎ層のキャリアライフタイムを、活性領域の並列ｐｎ層のキャリアライフタイムより短くする等の手段で、ＭＯＳＦＥＴ等に内蔵されるダイオードの逆回復過程におけるアノード電極付近での電流集中を緩和し、破壊耐量を向上することができる。
【００５２】
いずれも従来の技術の応用で実行可能であり、かつ破壊耐量が６倍以上と効果も大きいことが実証された非常に有効な発明である。
【図面の簡単な説明】
【図１】 本発明実施例２のＭＯＳＦＥＴの模式的部分断面図
【図２】 （ａ）、（ｂ）は実施例２のＭＯＳＦＥＴにおける内蔵ダイオードの逆回復過程におけるキャリア電流密度、キャリア密度のシミュレーション結果を濃淡で表した図
【図３】 本発明実施例１のＭＯＳＦＥＴの模式的部分断面図
【図４】 実施例１のＭＯＳＦＥＴのゲートパッド部の部分断面図
【図５】 本発明実施例３のＭＯＳＦＥＴの模式的部分断面図
【図６】 本発明実施例４のＭＯＳＦＥＴの模式的部分断面図
【図７】 本発明実施例５のＭＯＳＦＥＴの模式的部分断面図
【図８】 本発明実施例６のＭＯＳＦＥＴの模式的部分断面図
【図９】 本発明参考例のＭＯＳＦＥＴの模式的部分断面図
【図１０】 （ａ）、（ｂ）は参考例のＭＯＳＦＥＴにおける内蔵ダイオードの逆回復過程におけるキャリア電流密度、キャリア密度のシミュレーション結果を濃淡で表した図
【図１１】 本発明実施例７のＭＯＳＦＥＴの模式的部分断面図
【図１２】 本発明実施例８のＭＯＳＦＥＴの模式的部分断面図
【図１３】 従来のＭＯＳＦＥＴのＭＯＳＦＥＴの部分断面図
【図１４】 （ａ）、（ｂ）は従来のＭＯＳＦＥＴにおける内蔵ダイオードの逆回復過程におけるキャリア電流密度、キャリア密度のシミュレーション結果を濃淡で表した図
【図１５】 従来のＭＯＳＦＥＴのゲートパッド部部分断面図
【符号の説明】
１ ｎドリフト領域
２ ｐ仕切り領域
３ ｐウェル領域
４ 表面ｎドリフト領域
５ ｐ+コンタクト領域
６ ｎ+ソース領域
７ ゲート絶縁膜
８ ゲート電極層
９ 層間絶縁膜
１０ ソース電極、内蔵ダイオードのアノード電極
１１ ｎ+バッファ層
１２ ｎ++ドレイン層
１３ ドレイン電極、内蔵ダイオードのカソード電極
１４ ｎチャネルストッパ領域
１５ フィールド絶縁膜
１６ 周縁電極
１７ 絶縁膜
１８ ゲートパッド
２０ 並列ｐｎ層（活性部）
２１ ｎドリフト領域
２２ ｐ仕切り領域
２３ 並列ｐｎ層（耐圧構造部）
２４ ライフタイム制御領域
５０ 活性部
６０ 耐圧構造部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a structure including a parallel pn layer that allows current to flow in an on state and to be depleted in an off state, and in particular, equivalence between a source and a drain of a MOSFET (insulated gate field effect transistor) or the like. The present invention relates to a semiconductor device having a formed diode.
[0002]
[Prior art]
In general, a diode is equivalently built in between the source and drain of a MOSFET, and one of the diodes, for example, the anode electrode is formed only in the active portion of one main surface where current control is performed. However, since the other cathode electrode is formed over the entire main surface of the active part and the breakdown voltage structure part, when a forward bias is applied to the built-in diode, accumulated carriers also exist in the breakdown voltage structure part.
[0003]
In the process of transition from the forward bias state of the diode to the reverse bias state, a reverse recovery process is performed. This is a phenomenon in which a current flows in the reverse direction for a short time until the accumulated carriers disappear even if the reverse bias is applied, since carriers accumulate in the drift region when the built-in diode is in the forward bias state.
In this reverse recovery process, reverse recovery destruction may occur. Reverse recovery breakdown generally occurs at the boundary portion between the active portion and the pressure-resistant structure portion, and the cause of the breakdown is thermal breakdown due to electric field concentration and current concentration generated at the boundary portion.
[0004]
The electric field concentration is caused by a cylindrical or spherical pn junction formed at the end portion of the anode region, and the current concentration is such that carriers existing in the breakdown voltage structure flow toward the anode electrode during reverse recovery. Is the cause.
[0005]
[Problems to be solved by the invention]
The problem of the reverse recovery process of the MOSFET built-in diode is serious in a semiconductor device having parallel pn layers in which n-type regions and p-type regions are alternately arranged. In particular, a semiconductor device having a parallel pn layer in which n-type regions and p-type regions are alternately arranged in the breakdown voltage structure as disclosed in Japanese Patent Application Laid-Open No. 2001-298190 is a very big problem.
[0006]
In the following, a layer or region bearing n or p means a layer or region having majority carriers of electrons and holes, respectively. Also + Is a relatively high impurity concentration, - Means a region with a relatively low impurity concentration.
FIG. 13 is a partial cross-sectional view showing an active portion 50 in which current control of a MOSFET including a parallel pn layer 20 composed of an n drift region 1 and a p partition region 2 is performed, and a breakdown voltage structure portion 60 that maintains a breakdown voltage. A parallel pn layer 23 including an n drift region 21 and a p partition region 22 is also formed in the breakdown voltage structure 60. Although almost no drift current flows in the n drift region 21 of the breakdown voltage structure portion 60, this is tentatively referred to as compared with the parallel pn layer 20 of the active portion 50. The left end is the end of the chip. However, in order to avoid complication of the figure, the number of n drift regions and p partition regions of the parallel pn layers 20 and 23 is reduced.
[0007]
In the active part 50, the low resistance n ++ Parallel p in which n drift regions 1 and p partition regions 2 are alternately arranged on the drain layer 12 n A p-well region 3 is formed on the p-partition region 2, and a surface layer of the p-well region 3 is selectively n + Source region 6 and p + A contact region 5 is formed. Both the n drift region 1 and the p partition region 2 are, for example, vertical layers, and extend in a direction perpendicular to the paper surface.
[0008]
An n surface drift region 4 having a high impurity concentration is formed on the n drift region 1. n surface drift region 4 and n + A gate electrode layer 8 is provided on the surface of the p-well region 3 sandwiched between the source region 6 via a gate insulating film 7. n + Source region 6 and p + A source electrode 10 is provided in common contact with the surface of the contact region 5 and n ++ A drain electrode 13 is provided in contact with the back surface of the drain layer 12. An insulating film 9 insulates the gate electrode layer 8 from the source electrode 10.
[0009]
In the breakdown voltage structure 60, n ++ On the drain layer 12, there is a parallel pn structure portion 23 in which n drift regions 21 and p partition regions 22 are alternately arranged, and a field insulating film 15 is formed thereon. The source electrode 10 is extended on the field insulating film 15 to form a field plate structure. An n-channel stopper region 14 is formed at the end of the chip, and a peripheral electrode 16 is provided on the surface thereof. The source electrode 10 becomes an anode electrode of the built-in diode, and the drain electrode 13 becomes a cathode electrode.
[0010]
For example, in the case of a 600V class MOSFET, the standard dimension and impurity concentration of each part take the following values. n ++ Impurity concentration of drain layer 12 is 1 × 10 18 cm -3 , Thickness 5 μm, impurity concentration of active region 50 n drift region 1 and p partition region 2 2.57 × 10 15 cm -3 , Thickness 42 μm, width 8 μm, impurity concentration of the parallel pn layer 23 of the breakdown voltage structure 60 is 5 × 10 14 cm -3 It is.
[0011]
In the parallel pn layers 20 and 23 of the active part 50 and the withstand voltage structure part 60, the withstand voltage structure part 60 has a lower impurity concentration and the depletion layer is easier to spread. The n drift regions 1 and 21 and the p partition regions 2 and 22 have the same region width and the same pitch (P1).
In the case of the conventional MOSFET structure as shown in FIG. 13, the parallel pn structure portion 20 of the active portion 50 is completely depleted with a reverse bias of about 50 V, and the carriers accumulated during the forward bias of the built-in diode are in the reverse recovery process. At this time, the source electrode (anode electrode) 10 is instantaneously swept out.
[0012]
On the other hand, the carrier sweep-out in the breakdown voltage structure 60 is gradually performed as the reverse voltage increases, and the reverse recovery current due to the carrier sweep out causes the p partition region 22 of the parallel pn layer 23 of the breakdown voltage structure 60 to be on the source electrode 10 side. Since there is no electrode, it further flows on the surface of the parallel pn layer 23. And current concentrates on the part (E part) which the source electrode (anode electrode) 10 is contacting, and it destroys.
[0013]
FIGS. 14A and 14B are shading diagrams showing the simulation results of the carrier current density and the carrier density at the time of reverse recovery at this time as the density is higher. The density at the time when the reverse recovery current is maximum is shown.
As shown in FIG. 14, many carriers remain in the breakdown voltage structure 60, and 1 × 10 10 near the contact portion (E portion) of the source electrode 10. Four A / cm 2 It can be seen that a certain amount of current is concentrated. In the figure, 1e4A / cm 2 Is 1 × 10 Four It means A / cm.
[0014]
A similar problem occurs near the gate pad. FIG. 15 is a partial cross-sectional view in the vicinity of a gate pad 18 of a conventional MOSFET.
A diode is also incorporated in the parallel pn layer 27 immediately below the gate pad 18, and carriers swept out from the built-in diode in the reverse recovery process have no place to go, and the p-well region 3 formed on both sides immediately below the gate pad 18 Concentrate and sometimes cause destruction.
[0015]
In view of such a problem, an object of the present invention is to provide a semiconductor element that prevents current concentration from a built-in diode in a MOSFET or the like having a parallel pn structure and improves reverse recovery tolerance.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the semiconductor element of the present invention includes first and second main surfaces, first and second electrodes provided on the first and second main surfaces, and first and second electrodes, respectively. A first conductivity type low-resistance layer in contact with the first electrode between the main surfaces; a parallel pn layer in which the first conductivity type drift region and the second conductivity type partition region are alternately arranged; second Active region containing a high-concentration second conductivity type region in the surface layer on the main surface side And a pressure-resistant structure surrounding the active region In the semiconductor element formed and having the second electrode in contact with the high-concentration second conductivity type region, a first conductivity type buffer layer is provided between the first conductivity type low resistance layer and the parallel pn layer. And The first conductivity type buffer layer is a higher resistance layer than the first conductivity type low resistance layer, and is a lower resistance layer than a parallel pn layer. Shall.
[0017]
By doing so, the carriers accumulated in the first conductivity type buffer layer at the time of forward bias of the built-in diode are supplied to the second conductivity type partition region of the parallel pn layer of the active part by electric field distribution. Since carriers exist in the second conductivity type partition region of the parallel pn layer, the reverse recovery current due to the carrier discharge from the breakdown voltage structure portion is not concentrated near the junction between the parallel pn layer and the second conductivity type well region. It flows through the first conductivity type buffer layer and the second conductivity type partition region of the active portion parallel pn layer. For this reason, current concentration in the vicinity of the anode electrode in the reverse recovery process of the diode incorporated in the MOSFET or the like can be relaxed, and the breakdown tolerance can be improved.
[0018]
Also , Parallel pn layers from at least two regions with different carrier lifetimes The element Outside the active part Pressure resistant structure An area with a short lifetime is assumed to be arranged.
[0019]
By having a region in which the lifetime is controlled to be at least two types, the amount of carrier accumulation in the region with a short lifetime including the breakdown voltage structure portion is reduced, and reverse recovery by discharging carriers from the breakdown voltage structure portion The current can be reduced. For this reason, current concentration in the vicinity of the anode electrode in the reverse recovery process of the built-in diode incorporated in the MOSFET or the like can be relaxed, and the breakdown tolerance can be improved.
[0020]
That is It is important that the carrier lifetime of the parallel pn layer outside the active region is controlled to be shorter than the carrier lifetime of the parallel pn layer of the active region. More From the first pitch of the parallel pn layers arranged at the first pitch in the breakdown voltage structure, and the first pitch It is preferable to have a second portion of the parallel pn layers arranged at a small second pitch.
[0021]
In a portion having a small pitch, the depletion layer easily spreads, so that the accumulated carriers are dispersed and current concentration hardly occurs. Pressure resistant structure If the channel stopper region of the first conductivity type is arranged outside the surface, it becomes a channel stopper that prevents the surface from being reversed. Furthermore, The surface of the second part of the parallel pn layer is thick It is assumed that it is covered with an insulating film.
[0022]
Withstand pressure structure Thick insulating film so Often covered. Since the first conductivity type channel stopper region is made continuous with the first conductivity type low resistance layer formed below the parallel pn layer, all the side surfaces of the chip can have the same potential as the drain electrode 13. This stabilizes the breakdown voltage of the device and improves the quality.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[Example 1]
FIG. 3 is a partial cross-sectional view of the superjunction MOSFET according to the first embodiment of the present invention, and the left side of the figure is a breakdown voltage structure. However, in order to avoid complication of the figure, the parallel pn structures 20 and 23 are reduced. The same applies thereafter.
[0024]
3, parts having the same functions as those in FIG. 13 are given the same symbols. Although it overlaps with FIG. 13, it demonstrates.
11 is a low resistance n + Buffer layer 12 is a low resistance n ++ The drain layer 1 is a first conductivity type drift region, and 2 is a parallel pn layer 20 composed of a second conductivity type partition region. A p-well region 3 is formed on the surface layer continuously to the p-partition region 2. p inside the p-well region 3 + Contact region 5 and n + A source region 6 is formed. n + On the surface of the p well region 3 sandwiched between the source region 6 and the n drift region 1, a polycrystalline silicon gate electrode layer 8 is formed via a gate insulating film 7, and n + Source region 6 and p + A source electrode 10 that is in common contact with the surface of the contact region 5 is provided. n ++ A drain electrode 13 is provided on the back surface of the drain layer 12. Reference numeral 15 denotes an oxide film for surface protection and stabilization, which is made of, for example, a thermal oxide film and phosphor silica glass (PSG). The source electrode 10 is often extended on the gate electrode layer 8 through the interlayer insulating film 9 as shown in FIG. A gate electrode made of a metal film is provided on the gate electrode layer 8 at a portion not shown.
[0025]
The pitch of the parallel pn layers 23 of the breakdown voltage structure 60 is formed at the same pitch as that of the active part 50.
In the case of a diode built in the MOSFET, the source electrode 10 of the MOSFET is the anode electrode and the drain electrode 13 is the cathode electrode. In many cases, the gate electrode of the MOSFET is connected to the anode electrode.
[0026]
The planar shapes of the n drift region 1 and the p partition region 2 are both striped, for example. The planar shape of the n drift region 1 and the p partition region 2 may be such that one is a lattice shape or a net shape and the other is sandwiched therebetween.
The breakdown voltage structure according to the first embodiment includes a field plate structure that is normally performed, but may of course be a guard ring structure.
[0027]
In FIG. 3, a low-resistance n-channel stopper region 14 is disposed adjacent to the parallel pn layer 23 of the breakdown voltage structure portion 60. + N through the buffer layer 11 ++ The drain layer 12 is connected. The entire side surface of the semiconductor chip is covered with the n-channel stopper region 14, and the peripheral electrode 16 is provided in contact with the surface.
[0028]
This n-channel stopper region 14 not only serves as a channel stopper for preventing surface inversion, but also the side surface of the chip can be set to the same potential as the drain electrode 13, thereby stabilizing the breakdown voltage of the device. Quality is also improved.
However, the n-channel stopper region 14 does not necessarily have to be the side surface of the chip, and another semiconductor element or semiconductor region can be formed in the semiconductor region on the opposite side across the n-channel stopper region 14.
[0029]
In this embodiment, n ++ N on the drain layer 12 + By forming the buffer layer 11, it is possible to improve the reverse recovery tolerance of the built-in diode of the MOSFET. This can be explained as follows.
When a forward bias is applied to the built-in diode, carriers accumulate in the active portion 50 and the breakdown voltage structure portion 60. In the reverse recovery process, the accumulated carriers are swept out by applying a reverse bias to the built-in diode.
[0030]
At this time, the active part is completely depleted by a reverse bias of about 50 V, but n + N due to the presence of the buffer layer 11 when forward biased + Carriers accumulated in the buffer layer 11 are dispersed by the electric field distribution in the p-type partition region 2 of the parallel pn layer 20 of the active part 50 in the vicinity of the boundary between the active part 50 and the breakdown voltage structure part 60.
Therefore, the reverse recovery current due to the carrier sweep from the breakdown voltage structure 60 is not concentrated in the vicinity of the p partition region 2 at the end of the parallel pn layer 20 of the active part 50, and n + The buffer layer 11 flows in a distributed manner to the p partition region 2 of the active portion parallel pn layer 20. Therefore, current concentration in the vicinity of the junction of the p-well region 3 is suppressed, and the reverse recovery tolerance is improved.
[0031]
For example, in the case of a 600V class MOSFET, the standard dimension and impurity concentration of each part take the following values. n ++ Impurity concentration of drain layer 12 is 1 × 10 18 cm -3 , Thickness 5μm, n + Impurity concentration of buffer layer 11 4 × 10 15 cm -3 , Thickness 30 μm, n drift region 1 and p partition region 2 impurity concentration 2.57 × 10 15 cm -3 Impurity concentration 5 × 10 of the parallel pn layer 23 of the thickness 42 μm, the width 8 μm, and the breakdown voltage structure 60 14 cm -3 It is.
[0032]
n + The impurity concentration of the buffer layer 11 is n ++ It is lower than that of the drain layer 12 and higher than that of the parallel pn layer. N + The buffer layer 11 can be formed by, for example, an epitaxial growth method. FIG. 4 is a partial cross-sectional view in the vicinity of the gate pad of the MOSFET according to the first embodiment.
In this embodiment, n is also provided below the gate pad 18. + A buffer layer 11 is provided. As a result, the carriers swept out in the reverse recovery process of the built-in diode are n + Since it is distributed through the buffer layer 11, the concentration of reverse recovery current in the p-well region 3 formed on both sides immediately below the gate pad 18 can be relaxed, and the reverse recovery tolerance can be improved.
[0033]
In this embodiment, the p-well region 3 is not provided immediately below the gate pad 18, but the p-well region 3 may be provided. Further, the parallel pn layer directly under the gate pad 18 may be narrower than the pitch of the parallel pn layer of the active part, or the net impurity concentration may be lowered.
[Example 2]
FIG. 1 is a partial sectional view of a MOSFET according to a second embodiment of the present invention, and the left side of the figure is a breakdown voltage structure.
[0034]
The difference from the first embodiment of FIG. 3 is that the pitch (P2) of a part of the parallel pn layers 23 of the breakdown voltage structure 60 is formed with a pitch smaller than that (P1) of the active part 50. . Specifically, P2 is set to 1/2 of P1. This portion can be formed in exactly the same manner as other pn layer portions by simply changing the dimensions of the mask during manufacture.
The portion with a small pitch is up to the vicinity where the source electrode 10 extends on the field insulating film 15. In the breakdown voltage structure 60, since the pitch is narrow, the depletion layer easily spreads, so that the accumulated carriers are dispersed and current concentration is less likely to occur.
[0035]
In this case, n is the same as in the first embodiment. + The impurity concentration of the buffer layer 11 is n ++ It is lower than that of the drain layer 12 and higher than that of the parallel pn layer. And n + Due to the presence of the buffer layer 11, the current due to the discharge of the accumulated carriers of the built-in diode is distributed to the p partition region 2 of the parallel pn layer 23 of the active unit 50, and current concentration is relaxed.
FIGS. 2 (a) and 2 (b) are density diagrams showing the simulation results of the carrier current density and the carrier density at the time of reverse recovery at this time as the density increases.
[0036]
From FIG. 2, n + Due to the presence of the buffer layer 11, the accumulated carriers in the built-in diode are dispersed, and the current generated by the carrier sweep is dispersed in the p-type partition region 2 of the parallel pn layer 20 of the active portion 50, and the contact portion ( Current concentration in the vicinity of E part) is 1 × 10 A / cm 2 It can be seen that the current concentration is relaxed.
[0037]
The actually fabricated device showed a withstand capability of 8 times or more that of a conventional MOSFET. Example 3
FIG. 5 is a partial cross-sectional view of a MOSFET according to a third embodiment of the present invention, and the left side of the figure is a breakdown voltage structure.
The difference from the second embodiment of FIG. 1 is that the pitch (P2) of the parallel pn layers 23 of the breakdown voltage structure 60 is entirely formed up to the p-well region 3 of the active part 50 at a pitch smaller than that (P1) of the active part 50. It is a point that has been.
[0038]
As a result, the depletion layer tends to spread near the end of the p-well region 3, so that the accumulated carriers are dispersed and current concentration is less likely to occur.
In this case, the same effect as in the second embodiment can be obtained.
Example 4
FIG. 6 is a partial cross-sectional view of a MOSFET according to a fourth embodiment of the present invention, and the left side of the figure is a breakdown voltage structure.
[0039]
The difference from the third embodiment in FIG. 5 is that the parallel pn layer 23 having a pitch (P2) smaller than that (P1) of the active portion 50 is formed only on the surface side of the breakdown voltage structure portion 60. In the breakdown voltage structure 60, since the pitch is narrow, the depletion layer easily spreads, so that the accumulated carriers are dispersed and current concentration is less likely to occur.
In this case, the same effect as in the third embodiment can be obtained.
Example 5
FIG. 7 is a partial cross-sectional view of a MOSFET of Example 5 according to the present invention, and the left side of the figure is a breakdown voltage structure.
[0040]
This is a case where the junction of the parallel pn layer 23 of the withstand voltage lateral structure 60 undulates. For example, depending on the method of manufacturing the parallel pn layer 23, the junction of the pn layer 23 may become like this, such as repeating p-type impurity buried diffusion, epitaxial growth, and heat treatment.
In this case, the same effect as that of the first embodiment can be obtained.
Example 6
FIG. 8 is a partial cross-sectional view of the MOSFET according to the sixth embodiment of the present invention, and the left side of the figure is the breakdown voltage structure.
[0041]
This is a case where the p partition regions 22 of the parallel pn layers 23 of the pressure-resistant structure 60 are not continuous in the depth direction. Since the n drift region 21 and the p partition region 22 of the parallel pn layer 23 of the breakdown voltage structure 60 can take various combinations of impurity concentrations and shapes under the condition of depletion at a constant voltage, such a case Is also possible.
[ Reference example ]
FIG. 9 is related to the present invention. Reference example 2 is a partial cross-sectional view of the MOSFET, and the left side of the figure is a breakdown voltage structure portion.
[0042]
The difference from Example 3 is n + There is no buffer layer 11. Therefore, n as in the previous examples + Dispersion of the reverse recovery current of the built-in diode through the buffer layer 11 does not occur.
However, in this embodiment, since the pitch (P2) of the parallel pn layers 23 of the breakdown voltage structure 60 is narrower than the pitch (P1) of the parallel pn layers 20 of the active portion 50, the parallel pn layers 23 in the breakdown voltage structure 60 are The net impurity concentration is lower than the parallel pn layer 20 of the active part 50.
[0043]
For this reason, the electric field of the parallel pn layer at the boundary between the active part 50 and the breakdown voltage structure part 60 is relaxed, and the reverse recovery resistance is improved by the relaxation of current concentration.
FIGS. 10A and 10B are shading diagrams showing the simulation results of the carrier current density and the carrier density at the time of reverse recovery at this time as the density is higher.
From FIG. 10, it can be seen that the accumulated carriers in the built-in diode are dispersed in a wide range, and the current concentration near the anode electrode (E portion) due to the carrier sweeping is reduced. Current concentration is 2 × 10A / cm 2 It was found that the current concentration was relaxed.
[0044]
The actually fabricated device showed a withstand capability of 5 times or more that of a conventional MOSFET. 〔Example 7 ]
FIG. 11 shows an embodiment according to the present invention. 7 2 is a partial cross-sectional view of the MOSFET, and the left side of the figure is a breakdown voltage structure portion.
This example 7 This MOSFET is characterized in that a lifetime adjustment region 24 whose lifetime is controlled to be short is provided in the parallel pn layer 23 of the breakdown voltage structure 60, and is indicated by hatching.
[0045]
The adjustment region 24 with a short lifetime is a junction region between the parallel pn layer 23 of the breakdown voltage structure 60 and the p-well region 3 in the outermost periphery of the active portion 50 and the p-well region 3 in the outermost periphery of the active portion 50. Is formed in a region including a region where the anode electrode 10 is in contact with the anode electrode 10.
As shown in FIG. 14, the reverse recovery current of the built-in diode is concentrated in the p partition region 22 of the parallel pn layer 23 of the breakdown voltage structure portion 60 adjacent to the p well region 3 in the outermost peripheral portion of the active portion 50. there were.
[0046]
Therefore, if this region is a region having a short lifetime, carriers ejected from the breakdown voltage structure portion during reverse recovery are recombined in the region having a short lifetime, current concentration is relaxed, and reverse recovery tolerance is improved.
Such a region having a short lifetime can be easily formed by using a crystal defect introduction method using a particle beam such as electron beam irradiation, helium ion irradiation, or proton irradiation. In this embodiment, n ++ From the drain layer 12 side, an electron beam was irradiated at an acceleration voltage of 4.8 MeV and about 160 kilogray (kgry). It is good to adjust in the range of 100-500 kgry according to conditions.
[0047]
That is, using a material capable of blocking helium ions and protons (for example, aluminum metal, thick resist film), a mask having a structure in which a window is opened at a portion where the lifetime is desired to be shortened is manufactured. Then, the particle beam is irradiated from a direction perpendicular to the upper part of the mask.
When forming a region having a short lifetime in the entire depth of the parallel pn layer as in this embodiment, irradiation is performed. depth May be made deeper than the thickness of the parallel pn layer to allow helium ions or protons to pass through, or even if crystal defects are introduced by changing the irradiation depth and dividing the irradiation several times. good.
[0048]
The actually fabricated device exhibited a reverse recovery tolerance of 8 times or more that of a conventional MOSFET.
Since the region 24 in which the lifetime is controlled to be short does not include the active region 50 and is only the breakdown voltage structure 60, the forward voltage (ON voltage) does not increase. 〔Example 8 ]
FIG. 12 shows an embodiment according to the present invention. 8 2 is a partial cross-sectional view of the MOSFET, and the left side of the figure is a breakdown voltage structure portion.
[0049]
Example 7 Then, the region 24 with a short lifetime is formed in a part of the pressure-resistant structure 60, but the region 24 with a short lifetime may be formed over the entire pressure-resistant structure 60 as shown in FIG.
Further, by combining the methods of the above embodiments, it is a matter of course that a composite effect can be obtained and reverse recovery tolerance can be improved.
[0050]
Although this embodiment is described with a built-in diode of a MOSFET, a similar effect can be obtained with a free wheel diode, a Schottky diode, or the like.
[0051]
【The invention's effect】
As described above, according to the present invention, the first conductivity type low resistance layer in contact with the first electrode between the first and second main surfaces, the first conductivity type drift region, and the second conductivity type partition region, Of parallel pn layers and parallel pn layers arranged alternately second Active region including second conductivity type region in surface layer on main surface side of And a pressure-resistant structure surrounding the active region In the semiconductor element formed and in contact with the second electrode in the second conductivity type region, between the first conductivity type low resistance layer and the parallel pn layer, Higher resistance layer than the first conductivity type low resistance layer and lower resistance layer than the parallel pn layer Providing a first conductivity type buffer layer, or A first portion of a parallel pn layer disposed at a first pitch in the voltage withstanding structure portion; Providing a second portion of parallel pn layers of different pitch, or Pressure resistant structure The current lifetime in the vicinity of the anode electrode during the reverse recovery process of the diode built in the MOSFET is alleviated by means such as making the carrier lifetime of the parallel pn layer shorter than the carrier lifetime of the parallel pn layer in the active region. , Can improve the breakdown tolerance.
[0052]
Both are very effective inventions that have been demonstrated to be feasible by applying conventional techniques and have a large effect with a breakdown tolerance of 6 times or more.
[Brief description of the drawings]
FIG. 1 is a schematic partial cross-sectional view of a MOSFET according to Embodiment 2 of the present invention.
FIGS. 2A and 2B are graphs showing simulation results of carrier current density and carrier density in the reverse recovery process of the built-in diode in the MOSFET of Example 2 in shades of gray.
FIG. 3 is a schematic partial cross-sectional view of a MOSFET of Example 1 of the present invention.
4 is a partial cross-sectional view of a gate pad portion of the MOSFET of Example 1. FIG.
FIG. 5 is a schematic partial sectional view of a MOSFET according to Example 3 of the present invention.
FIG. 6 is a schematic partial sectional view of a MOSFET according to Example 4 of the present invention.
FIG. 7 is a schematic partial cross-sectional view of a MOSFET according to Example 5 of the present invention.
FIG. 8 is a schematic partial sectional view of a MOSFET according to Example 6 of the present invention.
FIG. 9 Reference example Schematic partial cross-sectional view of MOSFET
FIG. 10 (a), (b) Reference example A graph showing the simulation results of carrier current density and carrier density in the reverse recovery process of the built-in diode in the MOSFET in grayscale.
FIG. 11: Example of the present invention 7 Schematic partial cross-sectional view of MOSFET
FIG. 12 shows an example of the present invention. 8 Schematic partial cross-sectional view of MOSFET
FIG. 13 is a partial sectional view of a MOSFET of a conventional MOSFET.
FIGS. 14A and 14B are diagrams showing simulation results of carrier current density and carrier density in a reverse recovery process of a built-in diode in a conventional MOSFET in light and shade.
FIG. 15 is a partial sectional view of a gate pad portion of a conventional MOSFET.
[Explanation of symbols]
1 n drift region
2p partition area
3 p-well region
4 Surface n drift region
5 p + Contact area
6 n + Source area
7 Gate insulation film
8 Gate electrode layer
9 Interlayer insulation film
10 Source electrode, anode electrode of built-in diode
11 n + Buffer layer
12 n ++ Drain layer
13 Drain electrode, built-in diode cathode electrode
14 n-channel stopper region
15 Field insulating film
16 Perimeter electrode
17 Insulating film
18 Gate pad
20 parallel pn layers (active part)
21 n drift region
22p partition area
23 Parallel pn layer (withstand voltage structure)
24 Lifetime control area
50 Active part
60 Pressure resistant structure

Claims (7)

第一と第二の主面と、第一と第二の主面にそれぞれ設けられた第一と第二の電極と、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層とを有し、並列ｐｎ層の第二の主面側の表面層に第二導電型領域を含む活性領域と該活性領域を取り囲む耐圧構造部が形成され、前記第二導電型領域に第二の電極が接している半導体素子において、前記第一導電型低抵抗層と並列ｐｎ層との間に、第一導電型バッファ層を有し、前記第一導電型バッファ層は、前記第一導電型低抵抗層よりも高抵抗層であり、かつ並列ｐｎ層に比べ低抵抗層であることを特徴とする半導体素子。The first and second main surfaces, the first and second electrodes provided on the first and second main surfaces, respectively, and the first electrode in contact with the first electrode between the first and second main surfaces A conductive type low-resistance layer; and a parallel pn layer in which first conductivity type drift regions and second conductivity type partition regions are alternately arranged, and a second main surface side surface layer of the parallel pn layer has a second voltage withstanding structure portion surrounding the active region and the active region including a conductive type region is formed, the second conductive type region in a semiconductor device which the second electrode is in contact, parallel pn and the first conductivity type low-resistance layer A first conductivity type buffer layer between the layers, the first conductivity type buffer layer being a higher resistance layer than the first conductivity type low resistance layer, and a lower resistance layer than the parallel pn layer; semiconductor device characterized by at. 半導体素子が絶縁ゲート型電界効果トランジスタであることを特徴とする請求項１に記載の半導体素子。The semiconductor device of claim 1, the semiconductor device is characterized in that an insulated gate field effect transistor. 第一と第二の主面と、第一と第二の主面にそれぞれ設けられた第一と第二の電極と、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層とを有し、並列ｐｎ層の第二の主面側の表面層に第二導電型領域を含む活性領域と該活性領域を取り囲む耐圧構造部が形成され、前記第二導電型領域に第二の電極が接している半導体素子において、並列ｐｎ層がキャリアライフタイムが異なる少なくとも二つの領域からなり、耐圧構造部の並列ｐｎ層のキャリアライフタイムが、活性領域の並列ｐｎ層のキャリアライフタイムより短く制御されていることを特徴とする半導体素子。The first and second main surfaces, the first and second electrodes provided on the first and second main surfaces, respectively, and the first electrode in contact with the first electrode between the first and second main surfaces A conductive type low-resistance layer; and a parallel pn layer in which first conductivity type drift regions and second conductivity type partition regions are alternately arranged, and a second main surface side surface layer of the parallel pn layer has a second voltage withstanding structure portion surrounding the active region and the active region including a conductive type region is formed, the semiconductor device has the second electrode in contact with the second conductivity type region, the parallel pn layer carrier lifetimes are at least two A semiconductor element comprising two regions , wherein the carrier lifetime of the parallel pn layer of the breakdown voltage structure portion is controlled to be shorter than the carrier lifetime of the parallel pn layer of the active region . 第一と第二の主面にそれぞれ設けられた第一と第二の電極と、第一と第二の主面間に第一の電極と接する第一導電型低抵抗層と、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層とを有し、並列ｐｎ層の第二の主面側の表面層に高濃度の第二導電型領域を含む活性領域と該活性領域を取り囲む耐圧構造部が形成されている半導体素子において、耐圧構造部に第一のピッチで配置した並列ｐｎ層の第一の部分と、異なる第二のピッチで配置した並列ｐｎ層の第二の部分とを有していることを特徴とする半導体素子。First and second electrodes respectively provided on the first and second main surfaces; a first conductivity type low resistance layer in contact with the first electrode between the first and second main surfaces; Active region including a high-concentration second conductivity type region in a surface layer on the second main surface side of the parallel pn layer, having parallel pn layers in which type drift regions and second conductivity type partition regions are alternately arranged In the semiconductor element in which the breakdown voltage structure part surrounding the active region is formed , the first part of the parallel pn layer arranged at the first pitch in the breakdown voltage structure part and the parallel pn layer arranged at a different second pitch And a second portion of the semiconductor element. 耐圧構造部の外側に第一導電型のチャネルストッパ領域を配置したことを特徴とする請求項４に記載の半導体素子。The semiconductor element according to claim 4 , wherein a channel stopper region of the first conductivity type is disposed outside the breakdown voltage structure portion . 耐圧構造部の表面が厚い絶縁膜で覆われていることを特徴とする請求項４に記載の半導体素子。The semiconductor element according to claim 4 , wherein the surface of the pressure-resistant structure portion is covered with a thick insulating film. 第一導電型のチャネルストッパ領域が、並列ｐｎ層の下方に形成されている第一導電型低抵抗層と連続していることを特徴とする請求項５に記載の半導体素子。6. The semiconductor device according to claim 5 , wherein the first conductivity type channel stopper region is continuous with the first conductivity type low resistance layer formed below the parallel pn layer.
JP2002173991A 2002-06-14 2002-06-14 Semiconductor element Expired - Lifetime JP3925319B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002173991A JP3925319B2 (en) 2002-06-14 2002-06-14 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002173991A JP3925319B2 (en) 2002-06-14 2002-06-14 Semiconductor element

Publications (2)

Publication Number Publication Date
JP2004022716A JP2004022716A (en) 2004-01-22
JP3925319B2 true JP3925319B2 (en) 2007-06-06

Family

ID=31173068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002173991A Expired - Lifetime JP3925319B2 (en) 2002-06-14 2002-06-14 Semiconductor element

Country Status (1)

Country Link
JP (1) JP3925319B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9437727B2 (en) 2013-01-16 2016-09-06 Fuji Electric Co., Ltd. Semiconductor element including active region, low resistance layer and vertical drift portion

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7577636B2 (en) 2003-05-28 2009-08-18 Fernandez Dennis S Network-extensible reconfigurable media appliance
CN1823421B (en) 2003-08-20 2010-04-28 株式会社电装 Vertical semiconductor device
JP4967236B2 (en) 2004-08-04 2012-07-04 富士電機株式会社 Semiconductor element
JP4940546B2 (en) 2004-12-13 2012-05-30 株式会社デンソー Semiconductor device
JP2006186145A (en) * 2004-12-28 2006-07-13 Toshiba Corp Semiconductor device and manufacturing method thereof
JP2006287127A (en) * 2005-04-04 2006-10-19 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method
US7541643B2 (en) 2005-04-07 2009-06-02 Kabushiki Kaisha Toshiba Semiconductor device
JP5015488B2 (en) 2005-09-07 2012-08-29 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5342752B2 (en) * 2006-05-16 2013-11-13 株式会社東芝 Semiconductor device
JP2009004668A (en) * 2007-06-25 2009-01-08 Toshiba Corp Semiconductor device
KR101614565B1 (en) 2008-09-01 2016-04-21 로무 가부시키가이샤 Semiconductor device and manufacturing method thereof
JP5901003B2 (en) 2010-05-12 2016-04-06 ルネサスエレクトロニクス株式会社 Power semiconductor device
DE102011079747A1 (en) 2010-07-27 2012-02-02 Denso Corporation Semiconductor device with switching element and freewheeling diode, and control method therefor
JP6197294B2 (en) * 2013-01-16 2017-09-20 富士電機株式会社 Semiconductor element
JP6221436B2 (en) * 2013-07-10 2017-11-01 富士電機株式会社 Superjunction MOSFET, manufacturing method thereof, and composite semiconductor device in which diodes are connected in parallel
JP2015018951A (en) * 2013-07-11 2015-01-29 株式会社東芝 Semiconductor device
CN105122458B (en) * 2013-09-18 2018-02-02 富士电机株式会社 Semiconductor device and its manufacture method
WO2016002963A1 (en) 2014-07-04 2016-01-07 富士電機株式会社 Semiconductor device
JP2017117882A (en) * 2015-12-22 2017-06-29 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of the same
JP2017076803A (en) * 2016-11-11 2017-04-20 株式会社東芝 Semiconductor element
CN109713041B (en) * 2018-12-27 2022-05-24 四川立泰电子有限公司 Improved structure suitable for super junction DMOS device
JP7443702B2 (en) 2019-09-10 2024-03-06 富士電機株式会社 semiconductor equipment

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4447065B2 (en) * 1999-01-11 2010-04-07 富士電機システムズ株式会社 Superjunction semiconductor device manufacturing method
JP4843843B2 (en) * 2000-10-20 2011-12-21 富士電機株式会社 Super junction semiconductor device
JP3908572B2 (en) * 2002-03-18 2007-04-25 株式会社東芝 Semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9437727B2 (en) 2013-01-16 2016-09-06 Fuji Electric Co., Ltd. Semiconductor element including active region, low resistance layer and vertical drift portion

Also Published As

Publication number Publication date
JP2004022716A (en) 2004-01-22

Similar Documents

Publication Publication Date Title
JP3925319B2 (en) Semiconductor element
US7432135B2 (en) Semiconductor device and method of manufacturing the same
JP4774580B2 (en) Super junction semiconductor device
KR102204272B1 (en) Power semiconductor devices and related methods with gate trenches and buried termination structures
JP4412344B2 (en) Semiconductor device and manufacturing method thereof
US9653595B2 (en) Semiconductor device and semiconductor device fabrication method
JP4289123B2 (en) Semiconductor device
WO2015145929A1 (en) Semiconductor device
JP5783893B2 (en) Semiconductor device
US9437727B2 (en) Semiconductor element including active region, low resistance layer and vertical drift portion
JP2002134748A (en) Superjunction semiconductor device
JP2007103770A (en) Insulated gate bipolar transistor
US20180240866A1 (en) Semiconductor device with low lifetime region
WO2017098547A1 (en) Silicon carbide semiconductor device
CN106057888B (en) Semiconductor device and method for manufacturing semiconductor device
JP2001298191A (en) Semiconductor device
US20210043765A1 (en) Silicon carbide semiconductor device and manufacturing method of same
US11158630B2 (en) Semiconductor device
JP4483001B2 (en) Semiconductor element
JP4910894B2 (en) Semiconductor device manufacturing method and semiconductor device
CA2918848A1 (en) Mos-bipolar device
JP2006324432A (en) Semiconductor device and its manufacturing method
JP2008263217A (en) Semiconductor device
JP2005136092A (en) Semiconductor device and its manufacturing method
JP4802430B2 (en) Semiconductor element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041014

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060703

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060704

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060911

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060919

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061120

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070206

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070219

R150 Certificate of patent or registration of utility model

Ref document number: 3925319

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100309

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100309

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110309

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110309

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120309

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120309

Year of fee payment: 5

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120309

Year of fee payment: 5

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120309

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130309

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130309

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140309

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term