JP3867875B2 - Semiconductor device - Google Patents

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Publication number
JP3867875B2
JP3867875B2 JP25169697A JP25169697A JP3867875B2 JP 3867875 B2 JP3867875 B2 JP 3867875B2 JP 25169697 A JP25169697 A JP 25169697A JP 25169697 A JP25169697 A JP 25169697A JP 3867875 B2 JP3867875 B2 JP 3867875B2
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Japan
Prior art keywords
electrodes
electrode
semiconductor chip
interposer
wiring board
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JP25169697A
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Japanese (ja)
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JPH1197571A (en
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功高 吉野
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【目次】
以下の順序で本発明を説明する。
【０００２】
発明の属する技術分野
従来の技術
発明が解決しようとする課題
課題を解決するための手段（図１〜図６）
発明の実施の形態（図１〜図６）
発明の効果
【０００３】
【発明の属する技術分野】
本発明は半導体装置に関し、例えば電極間隔が狭ピツチ化された半導体チツプの電極配列を再配列する変換基板及び当該変換基板上に半導体チツプが実装されてなる半導体装置に適用して好適なものである。
【０００４】
【従来の技術】
従来、半導体チツプにおいては、シリコン（Si）等の半導体材料からなる基板の一面側に所定の回路パターンと、複数の電極とが形成されてなることにより構成されている。
【０００５】
そしてこのような半導体チツプをマザー基板に実装する実装方法の１つとしてフリツプチツプ実装法がある。
【０００６】
このフリツプチツプ実装法は、半導体チツプの回路面に設けられた各電極上にそれぞれ突起電極でなるバンプを形成し、当該半導体チツプをマザー基板の実装面上にフエースダウンで直接実装する実装方法であり、半導体チツプを高密度で実装できる利点を有している。
【０００７】
ところが近年、エレクトロニクス機器は軽薄短小傾向を強め、高機能集積化及び信号処理の高速化が進んでおり、これに伴つて半導体チツプの電極間ピツチも益々狭ピツチ化が進んでいる。
【０００８】
そしてこのように狭ピツチ化された半導体チツプの各電極に対応させて、ランド及び配線パターンをマザー基板上に複数形成することは高度な技術を要し、またコストアツプにもつながつていた。
【０００９】
このため近年では、既存の実装技術を用いて半導体チツプをマザー基板上に実装する方法として、半導体チツプの電極配列を所望状態に再配列するためのインターポーザと呼ばれる変換基板を用いて半導体チツプの電極間ピツチを拡げた後、当該半導体チツプをインターポーザと一体にマザー基板上に実装する手法が広く用いられている。
【００１０】
実際上インターポーザは、半導体チツプとほぼ同形状で一回り程度大きく形成されたガラスエポキシ樹脂やセラミツク等からなる絶縁基板の一面側に半導体チツプの各バンプと同じ位置関係で複数の第１の電極が形成されると共に、絶縁基板の他面側（すなわち、マザー基板の実装面と向かい合う側）に各第１の電極にそれぞれ対応させて第１の電極の電極間ピツチよりも広い間隔で複数の第２の電極が形成され、これら対応する第１及び第２の電極間が配線パターン及びスルーホールを順次介して電気的に接続されることにより構成されている。
【００１１】
そしてこのインターポーザを用いた半導体チツプのマザー基板への実装は、半導体チツプをインターポーザの一面側にフリツプチツプ実装した後、当該インターポーザをマザー基板上に実装するようにして行われる。
【００１２】
従つてこのようなインターポーザを用いた方法によれば、マザー基板の電極パターンをインターポーザの第２の電極の電極パターンに応じて形成すれば良い分、マザー基板の電極間ピツチを広くでき、その分容易にかつ安価にマザー基板を形成し得る利点がある。
【００１３】
【発明が解決しようとする課題】
ところが既存の技術では、インターポーザに半導体チツプの狭ピツチ化する電極間隔の配線パターンを形成する上でエツチング精度（すなわち、配線パターンを露光現像等により形成する技術精度）を良くし難い問題があつた。
【００１４】
これは、ガラスエポキシ樹脂やセラミツクに対する微細加工技術の限界がシリコンからなる半導体チツプの基板に対する微細加工技術の限界よりも低いため、これに伴つてインターポーザの微細加工技術が半導体チツプの微細加工技術に追随できないことや、微細加工ができたとしても歩留りが悪いうえにコストアツプにもつながる問題であつた。
【００１５】
このことは半導体チツプの電極間隔が狭ピツチ化したときに、これに応じた間隔でインターポーザ上に電極を形成し得ず、この結果半導体チツプの電極間隔の狭ピツチ化に実用上十分に対応し得ないことを意味する。
【００１６】
本発明は以上の点を考慮してなされたもので、半導体チツプの電極間隔の狭ピツチ化に実用上十分に対応し得る半導体装置を提案しようとするものである。
【００１７】
【課題を解決するための手段】
かかる課題を解決するため本発明においては、一面側に複数の電極が形成された半導体チツプと、シリコンからなる絶縁基板の一面側に、半導体チツプの各電極と同じ位置関係で複数の第１の電極が形成されると共に、当該各第１の電極にそれぞれ対応させて複数の第２の電極が形成され、対応する各第１の電極及び各第２の電極同士が第１の導通接続手段により導通接続されてなる変換基板と、凹型の絶縁基板の開口部が設けられた一面側に、変換基板の各第２の電極と同じ位置関係で複数の第３の電極が形成されると共に、凹型の絶縁基板の他面側に各第３の電極にそれぞれ対応させて複数の第４の電極が形成され、対応する各第３の電極及び各第４の電極同士が第２の導通接続手段により導通接続されてなる凹型プリント配線板とを設けるようにして、各電極を対応する各第１の電極と導通接続するようにして変換基板の一面に半導体チツプを実装し、各第２の電極を対応する各第３の電極と導通接続するようにして凹型プリント配線板の一面に変換基板を実装するようにした。
【００１８】
この結果この半導体装置では、半導体チツプの各電極を形成する際に利用する加工技術と同じ加工技術を用いて変換基板に各第１の電極を形成することができ、かくして半導体チツプの各電極と同じピツチで変換基板に各第１の電極を形成することができる。
【００２１】
【発明の実施の形態】
以下図面について、本発明の一実施の形態を詳述する。
【００２２】
（１）第１の実施の形態
図１において１は全体として本実施の形態による半導体装置を示し、シリコン基板の一面側に所定の回路パターンと複数の電極とが形成されてなる半導体チツプ２をインターポーザ３上にフリツプチツプ実装した後、当該半導体チツプ２をエポキシ樹脂等の封止樹脂材４により封止することにより構成されている。
【００２３】
この場合インターポーザ３は、図１との対応部分に同一符号を付した図２に示すように、半導体チツプ２とほぼ同形状で一回り程度大きく形成されたシリコンからなる絶縁基板３Ａの一面側に半導体チツプ２の各バンプ２Ａと同じ位置関係で複数の第１の電極３Ｂが形成されると共に、絶縁基板３Ａの他面側に各第１の電極３Ｂにそれぞれ対応させて第１の電極３Ｂの電極間ピツチよりも広い間隔で複数の第２の電極３Ｃが形成され、これら対応する第１及び第２の電極３Ｂ、３Ｃ間が配線ライン３Ｄ及びスルーホール３Ｅを順次介して電気的に接続されることにより構成されている。
【００２４】
これによりこの半導体装置１においては、半導体チツプ２の電極間ピツチよりも広い間隔のインターポーザ３の第２の電極３Ｃを外部電極としてマザー基板上に実装することができるようになされている。
【００２５】
以上の構成において、この半導体装置１では、インターポーザ３の絶縁基板３Ａが半導体チツプ２の基板と同じシリコンで形成されているため、半導体チツプ２の各電極を形成する際に用いる微細加工技術と同じ微細加工技術を用いてインターポーザ３の各第１の電極３Ｂを形成することができる。
【００２６】
従つてこの半導体装置１では、半導体チツプ２の電極間隔の狭ピツチ化に追随してインターポーザ３の各第１の電極３Ｂを狭ピツチで形成することができ、半導体チツプ２の電極間隔の狭ピツチ化に実用上十分に対応することができる。
【００２７】
以上の構成によれば、半導体装置１においてインターポーザ３の絶縁基板３Ａをシリコンを用いて形成するようにしたことにより、半導体チツプ２と同様の微細加工技術を用いてインターポーザ３に第１の電極３Ｂを形成することができ、かくして半導体チツプ２の電極間隔の狭ピツチ化に実用上十分に対応し得るインターポーザ３及び半導体装置１を実現できる。
【００２８】
（２）第２の実施の形態
図１との対応部分に同一符号を付した図３は第２の実施の形態による半導体装置１０を示すものであり、プリント配線板１２の一面上にインターポーザ１１が固着されると共に、当該インターポーザ１１上に半導体チツプ２がフリツプチツプ実装されている。
【００２９】
この場合インターポーザ１１は、図３との対応部分に同一符号を付した図４に示すように、半導体チツプ２とほぼ同形状で一回り程度大きく形成されたシリコンからなる絶縁基板１１Ａの一面側の中央部に半導体チツプ２の各バンプ２Ａと同じ位置関係で複数の第１の電極１１Ｂが形成されると共に、当該絶縁基板１１Ａの一面側の周辺部に各第１の電極１１Ｂにそれぞれ対応させて第１の電極１１Ｂの電極間ピツチよりも広い間隔で複数の第２の電極１１Ｃが形成され、これら対応する第１及び第２の電極１１Ｂ、１１Ｃ間が配線ライン１１Ｄを介して電気的に接続されることにより構成されている。
【００３０】
またプリント配線板１２は、例えばガラスエポキシ樹脂からなる絶縁基板１２Ａの一面側にインターポーザ１１の各第２の電極１１Ｃとそれぞれ対応させて第１の電極１２Ｂが形成されると共に、当該絶縁基板１２Ａの他面側に各第１の電極１２Ｂにそれぞれ対応させて第２の電極１２Ｃが形成され、これら第１及び第２の電極１２Ｂ、１２Ｃがスルーホール１２Ｄを介して導通接続されることにより構成されている。
【００３１】
さらにインターポーザ１１の各第２の電極１１Ｃはそれぞれプリント配線板１２の対応する第１の電極１２Ｂと金ワイヤ１４を介して導通接続されると共に、半導体チツプ２、インターポーザ１１及び各金ワイヤ１４がエポキシ樹脂等の封止樹脂材により一体に封止されている。
【００３２】
これによりこの半導体装置１０においては、半導体チツプ２の電極間ピツチよりも広い間隔のプリント配線板１２の第２の電極１２Ｃを外部電極としてマザー基板上に実装することができるようになされている。
【００３３】
以上の構成において、半導体装置１０では、インターポーザ１１の絶縁基板１１Ａが半導体チツプ２と同じシリコンで形成されているため、半導体チツプ２の各電極を形成する際に用いる微細加工技術と同じ微細加工技術を用いてインターポーザ１１の各第１の電極１１Ｂを形成することができる。
【００３４】
従つてこの半導体装置１０では、半導体チツプ２の電極間隔の狭ピツチ化に追随してインターポーザ１１の各第１の電極１１Ｂを狭ピツチで形成することができ、半導体チツプ２の電極間隔の狭ピツチ化に実用上十分に対応することができる。
【００３５】
以上の構成によれば、半導体装置１０においてインターポーザ１１の絶縁基板１１Ａをシリコンを用いて形成するようにしたことにより、半導体チツプ２と同様の微細加工技術を用いてインターポーザ１１に第１の電極１１Ｂを形成することができ、かくして半導体チツプ２の電極間隔の狭ピツチ化に実用上十分に対応し得るインターポーザ１１及び半導体装置１０を実現できる。
【００３６】
（３）第３の実施の形態
図３との対応部分に同一符号を付した図５は第３の実施の形態による半導体装置２０を示すものであり、半導体チツプ２がインターポーザ１１を介して凹型プリント配線板２１の一面側に実装されている。
【００３７】
この場合凹型プリント配線板２１は、図５との対応部分に同一符号を付した図６に示すように、例えばガラスエポキシ樹脂等の絶縁材からなる平板状の第１の絶縁基板２１Ａの一面側に、その中央部に半導体チツプ２よりも一回り程度大きい開口部２２が設けられた平板状の第２の絶縁基板２１Ｂが貼り付けられることにより構成されている。
【００３８】
また第２の絶縁基板２１Ｂの一面側には、インターポーザ１１の各第２の電極１１Ｃとそれぞれ対応させてこれらインターポーザ１１の各第２の電極１１Ｃと同じ位置関係で複数の第１の電極２１Ｃが形成されると共に、第１の絶縁基板２１Ａの他面側には各第１の電極２１Ｃとそれぞれ対応させて複数の第２の電極２１Ｄが形成され、これら第１及び第２の電極２１Ｃ、２１Ｄが第１及び第２の絶縁基板２１Ａ、２１Ｂを一体に貫通するように設けられたスルーホール２１Ｅを介して導通接続されている。
【００３９】
そしてインターポーザ１１は、この凹型プリント配線板２１上に、各第２の電極１１Ｃがそれぞれ凹型プリント配線板２１の対応する第１の電極２１Ｃとバンプ２３を介して導通接続されるようにして実装されている。
【００４０】
これによりこの半導体装置２０においては、半導体チツプ２の電極間ピツチよりも広い間隔の凹型プリント配線板２１の各第２の電極２１Ｄをそれぞれ外部電極としてマザー基板上に実装することができるようになされている。
【００４１】
以上の構成において、半導体装置２０では、インターポーザ１１の絶縁基板１１Ａが半導体チツプ２と同じシリコンで形成されているため、半導体チツプ２の各電極を形成する際に用いる微細加工技術と同じ微細加工技術を用いてインターポーザ１１の各第１の電極１１Ｂを形成することができる。
【００４２】
従つてこの半導体装置２０では、半導体チツプ２の電極間隔の狭ピツチ化に追随してインターポーザ１１の各第１の電極１１Ｂを狭ピツチで形成することができ、半導体チツプ２の電極間隔の狭ピツチ化に実用上十分に対応することができる。
【００４３】
以上の構成によれば、半導体装置２０においてインターポーザ１１の絶縁基板１１Ａをシリコンを用いて形成するようにしたことにより、半導体チツプ２と同様の微細加工技術を用いてインターポーザ１１に第１の電極１１Ｂを形成することができ、かくして半導体チツプ２の電極間隔の狭ピツチ化に実用上十分に対応し得るインターポーザ１１及び半導体装置２０を実現できる。
【００４４】
（４）他の実施の形態
なお上述の第１〜第３の実施の形態においては、インターポーザ３、１１の対応する第１及び第２の電極３Ｂ、１１Ｂ、及び３Ｃ、１１Ｃの間を導通接続する導通接続手段として配線ライン３Ｄ、１１Ｄとスルーホール３Ｅとを用いるようにした場合について述べたが、本発明はこれに限らず、インターポーザ３、１１の外周を沿つて第１の電極３Ｂ、１１Ｂから第２の電極３Ｃ、１１Ｃに到る配線ライン３Ｄにより導通接続手段を形成するようにしても良く、要は、インターポーザ３、１１の対応する第１及び第２の電極３Ｂ、１１Ｂ及び３Ｃ、１１Ｃ間を導通接続することができるのであれば導通接続手段の構成としてはこの他種々の構成を適用できる。
【００４５】
また上述の第１及び第２の実施の形態においては、半導体チツプ２及びインターポーザ３、１１を一体に封止する封止樹脂材４、１３としてエポキシ樹脂材を使用するようにした場合について述べたが、本発明はこれに限らず、他の種々の絶縁材を使用するようにしても良い。
【００４６】
さらに上述の第２の実施の形態においては、インターポーザ１１の各第２の電極１１Ｃとプリント配線板１２の対応する第１の電極１２Ｂとの間の導通をそれぞれ金ワイヤ１４を用いてとるようにした場合について述べたが、本発明はこれに限らず、他の種々の方法を用いてインターポーザ１１の各第２の電極１１Ｃとプリント配線板１２の対応する第１の電極１２Ｂとの間の導通をとるようにしても良い。
【００４７】
さらに上述の第３の実施の形態においては、凹型プリント配線板２１を図６のように形成された第１及び第２の絶縁基板２１Ａ、２１Ｂを貼り付けることにより形成するようにした場合について述べたが、本発明はこれに限らず、ビルドアツプ法等この他種々の方法を用いて凹型プリント配線板２１を形成するようにしても良い。
【００４８】
さらに上述の第１〜第３の実施の形態においては、マザー基板の電極に対応する外部電極としてインターポーザ３の第２の電極３Ｃ、プリント配線板１２の第２の電極１２Ｃ及び凹型プリント配線板２１の第２の電極２１Ｄをそれぞれ各電極３Ｃ、１２Ｃ、２１Ｄが形成された絶縁基板３Ａ、１２Ａ、２１Ａ上の周辺部に再配列するようにした場合について述べたが、本発明はこれに限らず、例えばこれら各外部電極３Ｃ、１２Ｃ、２１Ｄから新たな配線ラインを引き回して当該各絶縁基板３Ａ、１２Ａ、２１Ａ上の全面にアレイ状に再配列するようにしても良い。またプリント配線板１２の絶縁基板１２Ａ及び凹型プリント配線板２１の第１の絶縁基板２１Ａを多層積層し、その中の何層かを用いて再配列しても良い。
【００４９】
さらに上述の第１〜第３の実施の形態においては、インターポーザ３、１１の各第２の電極３Ｃ、１１Ｃはそれぞれ対応する各第１の電極３Ｂ、１１Ｂの電極間ピツチを広くするようにした場合について述べたが、本発明はこれに限らず、要は、半導体チツプ２の電極配列を所望状態に再配列するようにインターポーザ３、１１に第２の電極３Ｃ、１１Ｃを形成すれば良い。
【００５０】
さらに上述の第２及び第３の実施の形態においては、プリント配線板１２の絶縁基板１２Ａ及び凹型プリント配線板２１の絶縁基板２１Ａ、２１Ｂを、ガラスエポキシ樹脂を用いて形成するようにした場合について述べたが、本発明はこれに限らず、他の種々の絶縁材を用いて形成するようにしても良い。
【００５１】
さらに上述の第２及び第３の実施の形態においては、インターポーザ１１の各第２の電極１１Ｃに対応するプリント配線板１２及び凹型プリント配線板２１の第１の電極１２Ｂ、２１Ｃと各第２の電極１２Ｃ、２１Ｄとをスルーホール１２Ｄ、２１Ｅを介して導通接続するようにした場合について述べたが、本発明はこれに限らず、例えばプリント配線板１２及び凹型プリント配線板２１の外周を沿つて各第１の電極１２Ｂ、２１Ｃから各第２の電極１２Ｃ、２１Ｄにそれぞれ配線ラインを引き回して導通接続するようにしても良い。
【００５２】
さらに上述の第１〜第３の実施の形態においては、インターポーザ３、１１の絶縁基板３Ａ、１１Ａを半導体チツプ２の基板と同じシリコンを用いて形成するようにした場合について述べたが、本発明はこれに限らず、要は、インターポーザ３、１１の絶縁基板３Ａ、１１Ａを、例えば半導体チツプ２の基板と同じ又はほぼ同じ組成の材料を用いるなど半導体チツプ２の各電極を形成する際に用いる加工技術と同じ加工技術を用いて各第１の電極３Ｂ、１１Ｂを形成することができる材料を用いて形成するのであれば、当該絶縁基板の組成としてはこの他種々の組成を広く適用できる。
【００５３】
【発明の効果】
上述のように本発明によれば、一面側に複数の電極が形成された半導体チツプと、シリコンからなる絶縁基板の一面側に、半導体チツプの各電極と同じ位置関係で複数の第１の電極が形成されると共に、当該各第１の電極にそれぞれ対応させて複数の第２の電極が形成され、対応する各第１の電極及び各第２の電極同士が第１の導通接続手段により導通接続されてなる変換基板と、凹型の絶縁基板の開口部が設けられた一面側に、変換基板の各第２の電極と同じ位置関係で複数の第３の電極が形成されると共に、凹型の絶縁基板の他面側に各第３の電極にそれぞれ対応させて複数の第４の電極が形成され、対応する各第３の電極及び各第４の電極同士が第２の導通接続手段により導通接続されてなる凹型プリント配線板とを設けるようにして、各電極を対応する各第１の電極と導通接続するようにして変換基板の一面に半導体チツプを実装し、各第２の電極を対応する各第３の電極と導通接続するようにして凹型プリント配線板の一面に変換基板を実装するようにしたことにより、半導体チツプの各電極と同じピツチで変換基板に各第１の電極を形成することができ、かくして半導体チツプの電極間隔の狭ピツチ化に実用上十分に対応し得る半導体装置を実現することができる。
【図面の簡単な説明】
【図１】第１の実施の形態による半導体装置の構成を示す断面図である。
【図２】第１の実施の形態によるインターポーザの構成を示す平面図である。
【図３】第２の実施の形態による半導体装置の構成を示す断面図である。
【図４】第２及び第３の実施の形態によるインターポーザの構成を示す平面図である。
【図５】第３の実施の形態による半導体装置の構成を示す断面図である。
【図６】凹型プリント配線板の形成方法の説明に供する斜視図である。
【符号の説明】
１、１０、２０……半導体装置、２……半導体チツプ、２Ａ、２３……バンプ、３、１１……インターポーザ、３Ａ、１１Ａ……絶縁基板、３Ｂ、３Ｃ、１１Ｂ、１１Ｃ、１２Ｂ、１２Ｃ、２１Ｃ、２１Ｄ……電極、３Ｅ、１２Ｄ、２１Ｅ……スルーホール、３Ｄ、１１Ｄ……配線ライン、４、１３……封止樹脂材、１２、２１Ａ、２１Ｂ……プリント配線板、１４……金ワイヤ、２１……凹型プリント配線板、２２……開口部。[0001]
【table of contents】
The present invention will be described in the following order.
[0002]
[Technical field to which the invention pertains] Means for solving the problems to be solved by the prior art invention (FIGS. 1 to 6)
BEST MODE FOR CARRYING OUT THE INVENTION (FIGS. 1 to 6)
Effects of the Invention
BACKGROUND OF THE INVENTION
The present invention relates to a semi-conductor device, such as those electrode spacing suitably applied to a semiconductor device in which a semiconductor chip is implemented on converter boards and the conversion on the substrate rearranging electrode array of a narrow pitch of semiconductor chips It is.
[0004]
[Prior art]
Conventionally, a semiconductor chip is configured by forming a predetermined circuit pattern and a plurality of electrodes on one side of a substrate made of a semiconductor material such as silicon (Si).
[0005]
One of the mounting methods for mounting such a semiconductor chip on a mother board is a flip chip mounting method.
[0006]
This flip chip mounting method is a mounting method in which bumps made of protruding electrodes are formed on each electrode provided on the circuit surface of the semiconductor chip, and the semiconductor chip is directly mounted on the mounting surface of the mother substrate in a face-down manner. The semiconductor chip has an advantage that it can be mounted at a high density.
[0007]
However, in recent years, electronic devices have become increasingly light and thin, and high-function integration and high-speed signal processing have progressed. Along with this, the pitch between electrodes of semiconductor chips has been increasingly narrowed.
[0008]
Forming a plurality of lands and wiring patterns on the mother substrate so as to correspond to each electrode of the semiconductor chip narrowed in this way requires a high level of technology and leads to a cost increase.
[0009]
Therefore, in recent years, as a method of mounting a semiconductor chip on a mother substrate using existing mounting technology, an electrode of the semiconductor chip is used by using a conversion substrate called an interposer for rearranging the electrode arrangement of the semiconductor chip to a desired state. A method of mounting the semiconductor chip on a mother substrate integrally with an interposer after expanding the gap is widely used.
[0010]
In practice, the interposer has a plurality of first electrodes in the same positional relationship as each bump of the semiconductor chip on one surface side of an insulating substrate made of glass epoxy resin, ceramic or the like, which is substantially the same shape as the semiconductor chip and formed approximately one size larger. The plurality of first electrodes are formed at intervals wider than the inter-electrode pitches of the first electrodes, corresponding to the first electrodes on the other surface side of the insulating substrate (that is, the side facing the mounting surface of the mother substrate). Two electrodes are formed, and the corresponding first and second electrodes are electrically connected through a wiring pattern and a through hole in sequence.
[0011]
The semiconductor chip using the interposer is mounted on the mother board by mounting the semiconductor chip on one surface side of the interposer and then mounting the interposer on the mother board.
[0012]
Therefore, according to the method using such an interposer, the pitch between the electrodes of the mother substrate can be widened because the electrode pattern of the mother substrate may be formed according to the electrode pattern of the second electrode of the interposer. There is an advantage that a mother substrate can be formed easily and inexpensively.
[0013]
[Problems to be solved by the invention]
However, in the existing technology, there is a problem that it is difficult to improve the etching accuracy (that is, the technology accuracy of forming the wiring pattern by exposure and development) in forming the wiring pattern of the electrode interval that narrows the pitch of the semiconductor chip on the interposer. .
[0014]
This is because the limit of microfabrication technology for glass epoxy resins and ceramics is lower than the limit of microfabrication technology for semiconductor chip substrates made of silicon, and as a result, the microfabrication technology of interposers has become the microfabrication technology of semiconductor chips. It was a problem that could not be followed, and even if microfabrication was possible, the yield was poor and the cost was increased.
[0015]
This means that when the semiconductor chip electrode spacing is narrowed, electrodes cannot be formed on the interposer at intervals corresponding to this, and as a result, it is practically adequate for narrowing the semiconductor chip electrode spacing. It means not getting.
[0016]
The present invention has been made in view of the above, it is intended to propose a semi conductor device that obtained with practically sufficiently correspond to a narrow pitch of the electrode spacing of the semiconductor chip.
[0017]
[Means for Solving the Problems]
In the present invention for solving the above problems, a semiconductor chip having a plurality of electrodes are formed on one side, on one surface of the insulating base plate made of silicon, the double speed in the same positional relationship as the respective electrodes of the semiconductor chip with first electrode is formed, it is respectively correspond to allowed by the second electrode of the multiple formed on the respective first electrodes, conducting the first electrode and the second electrodes of the corresponding the first A plurality of third electrodes are formed in the same positional relationship as each of the second electrodes of the conversion substrate on one side of the conversion substrate that is conductively connected by the connecting means and the opening of the concave insulating substrate. In addition, a plurality of fourth electrodes are formed on the other surface side of the concave insulating substrate so as to correspond to the respective third electrodes, and the corresponding third electrodes and the respective fourth electrodes are in the second conduction state. setting a concave printed wiring board formed by conductively connected by a connection means In the so that, to each electrode to be electrically connected with each corresponding first electrode of the semiconductor chip mounted on one surface of the conversion substrate and conductively connected with each third electrode corresponding to each of the second electrode In this way, the conversion board is mounted on one surface of the concave printed wiring board .
[0018]
As a result, in this semiconductor device , each first electrode can be formed on the conversion substrate using the same processing technique as that used when forming each electrode of the semiconductor chip. Each first electrode can be formed on the conversion substrate with the same pitch.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0022]
(1) First Embodiment In FIG. 1, reference numeral 1 denotes a semiconductor device according to the present embodiment as a whole, and a semiconductor chip 2 in which a predetermined circuit pattern and a plurality of electrodes are formed on one side of a silicon substrate. After the flip chip is mounted on the interposer 3, the semiconductor chip 2 is sealed with a sealing resin material 4 such as an epoxy resin.
[0023]
In this case, the interposer 3 is formed on the one surface side of the insulating substrate 3A made of silicon, which is substantially the same shape as the semiconductor chip 2 and is slightly larger than the semiconductor chip 2, as shown in FIG. A plurality of first electrodes 3B are formed in the same positional relationship as the respective bumps 2A of the semiconductor chip 2, and the first electrodes 3B are formed on the other surface side of the insulating substrate 3A so as to correspond to the first electrodes 3B. A plurality of second electrodes 3C are formed at a wider interval than the pitch between the electrodes, and the corresponding first and second electrodes 3B, 3C are electrically connected through the wiring line 3D and the through hole 3E sequentially. It is constituted by.
[0024]
As a result, in the semiconductor device 1, the second electrode 3C of the interposer 3 that is wider than the inter-electrode pitch of the semiconductor chip 2 can be mounted on the mother substrate as an external electrode.
[0025]
In the above configuration, in this semiconductor device 1, since the insulating substrate 3 </ b> A of the interposer 3 is formed of the same silicon as the substrate of the semiconductor chip 2, the same microfabrication technique as used when forming each electrode of the semiconductor chip 2 is used. Each first electrode 3B of the interposer 3 can be formed by using a fine processing technique.
[0026]
Therefore, in this semiconductor device 1, each electrode 3 B of the interposer 3 can be formed with a narrow pitch following the narrowing of the electrode pitch of the semiconductor chip 2, and the narrow pitch of the electrode pitch of the semiconductor chip 2 can be achieved. It is possible to respond sufficiently to practical use.
[0027]
According to the above configuration, since the insulating substrate 3A of the interposer 3 is formed using silicon in the semiconductor device 1, the first electrode 3B is applied to the interposer 3 using the same fine processing technique as that of the semiconductor chip 2. Thus, the interposer 3 and the semiconductor device 1 that can sufficiently cope with narrowing of the pitch of the electrode of the semiconductor chip 2 can be realized.
[0028]
(2) Second Embodiment FIG. 3 with the same reference numerals as those in FIG. 1 shows a semiconductor device 10 according to the second embodiment, and an interposer 11 on one surface of a printed wiring board 12. The semiconductor chip 2 is flip-chip mounted on the interposer 11.
[0029]
In this case, the interposer 11 is provided on the one surface side of the insulating substrate 11A made of silicon, which is substantially the same shape as the semiconductor chip 2 and is slightly larger than the semiconductor chip 2, as shown in FIG. A plurality of first electrodes 11B are formed in the central portion with the same positional relationship as the respective bumps 2A of the semiconductor chip 2, and a peripheral portion on one surface side of the insulating substrate 11A is associated with each first electrode 11B. A plurality of second electrodes 11C are formed at intervals wider than the inter-electrode pitch of the first electrode 11B, and the corresponding first and second electrodes 11B, 11C are electrically connected via the wiring line 11D. Is configured.
[0030]
The printed wiring board 12 is formed with a first electrode 12B corresponding to each of the second electrodes 11C of the interposer 11 on one surface side of an insulating substrate 12A made of, for example, glass epoxy resin. A second electrode 12C is formed corresponding to each first electrode 12B on the other side, and the first and second electrodes 12B and 12C are electrically connected through the through hole 12D. ing.
[0031]
Furthermore, each second electrode 11C of the interposer 11 is electrically connected to the corresponding first electrode 12B of the printed wiring board 12 via the gold wire 14, and the semiconductor chip 2, the interposer 11 and each gold wire 14 are epoxy. It is sealed integrally with a sealing resin material such as resin.
[0032]
As a result, in the semiconductor device 10, the second electrodes 12C of the printed wiring board 12 having a wider interval than the inter-electrode pitch of the semiconductor chip 2 can be mounted on the mother substrate as external electrodes.
[0033]
In the above configuration, in the semiconductor device 10, since the insulating substrate 11 </ b> A of the interposer 11 is formed of the same silicon as the semiconductor chip 2, the same microfabrication technique as that used when forming each electrode of the semiconductor chip 2. The first electrodes 11B of the interposer 11 can be formed using
[0034]
Therefore, in this semiconductor device 10, each electrode 11 B of the interposer 11 can be formed with a narrow pitch following the narrowing of the electrode spacing of the semiconductor chip 2, and the narrow pitch of the electrode spacing of the semiconductor chip 2 can be achieved. It is possible to respond sufficiently to practical use.
[0035]
According to the above configuration, since the insulating substrate 11A of the interposer 11 is formed using silicon in the semiconductor device 10, the first electrode 11B is applied to the interposer 11 using the same microfabrication technology as that of the semiconductor chip 2. Thus, it is possible to realize the interposer 11 and the semiconductor device 10 which can practically sufficiently cope with the narrowing of the electrode interval of the semiconductor chip 2.
[0036]
(3) Third Embodiment FIG. 5, in which the same reference numerals are assigned to the parts corresponding to those in FIG. 3, shows the semiconductor device 20 according to the third embodiment, and the semiconductor chip 2 is recessed via the interposer 11. It is mounted on one side of the printed wiring board 21.
[0037]
In this case, the concave printed wiring board 21 is provided on the one surface side of the flat first insulating substrate 21A made of an insulating material such as glass epoxy resin as shown in FIG. In addition, a flat plate-like second insulating substrate 21B provided with an opening 22 that is slightly larger than the semiconductor chip 2 at its center is attached.
[0038]
A plurality of first electrodes 21C are provided on one surface side of the second insulating substrate 21B so as to correspond to the second electrodes 11C of the interposer 11 and have the same positional relationship as the second electrodes 11C of the interposer 11. A plurality of second electrodes 21D are formed on the other surface side of the first insulating substrate 21A so as to correspond to the respective first electrodes 21C, and these first and second electrodes 21C, 21D are formed. Are electrically connected through a through hole 21E provided so as to penetrate the first and second insulating substrates 21A and 21B integrally.
[0039]
The interposer 11 is mounted on the concave printed wiring board 21 such that each second electrode 11C is electrically connected to the corresponding first electrode 21C of the concave printed wiring board 21 via the bumps 23. ing.
[0040]
As a result, in the semiconductor device 20, the second electrodes 21D of the concave printed wiring board 21 having a wider interval than the inter-electrode pitch of the semiconductor chip 2 can be mounted on the mother board as external electrodes. ing.
[0041]
In the above configuration, in the semiconductor device 20, since the insulating substrate 11 </ b> A of the interposer 11 is formed of the same silicon as the semiconductor chip 2, the same microfabrication technique as that used when forming each electrode of the semiconductor chip 2. The first electrodes 11B of the interposer 11 can be formed using
[0042]
Therefore, in this semiconductor device 20, each first electrode 11 B of the interposer 11 can be formed with a narrow pitch following the narrowing of the electrode pitch of the semiconductor chip 2, and the narrow pitch of the electrode pitch of the semiconductor chip 2. It is possible to respond sufficiently to practical use.
[0043]
According to the above configuration, since the insulating substrate 11A of the interposer 11 is formed using silicon in the semiconductor device 20, the first electrode 11B is applied to the interposer 11 using the same microfabrication technology as that of the semiconductor chip 2. Thus, the interposer 11 and the semiconductor device 20 that can sufficiently cope with the narrowing of the electrode spacing of the semiconductor chip 2 can be realized.
[0044]
(4) Other Embodiments In the first to third embodiments described above, the first and second electrodes 3B, 11B, 3C, 11C corresponding to the interposers 3, 11 are electrically connected. The case where the wiring lines 3D and 11D and the through hole 3E are used as the conductive connection means is described. However, the present invention is not limited to this, and the first electrodes 3B and 11B along the outer periphery of the interposers 3 and 11 are described. The conductive connection means may be formed by the wiring line 3D extending from the first electrode 3C to the second electrode 3C. In short, the first and second electrodes 3B, 11B and 3C corresponding to the interposers 3 and 11, Various other configurations can be applied as the configuration of the conductive connection means as long as the conductive connection can be established between the 11Cs.
[0045]
In the first and second embodiments described above, the case where an epoxy resin material is used as the sealing resin materials 4 and 13 for integrally sealing the semiconductor chip 2 and the interposers 3 and 11 has been described. However, the present invention is not limited to this, and other various insulating materials may be used.
[0046]
Further, in the above-described second embodiment, conduction between each second electrode 11 </ b> C of the interposer 11 and the corresponding first electrode 12 </ b> B of the printed wiring board 12 is obtained using the gold wire 14. However, the present invention is not limited to this, and the continuity between each second electrode 11C of the interposer 11 and the corresponding first electrode 12B of the printed wiring board 12 using various other methods. You may make it take.
[0047]
Furthermore, in the above-described third embodiment, the case where the concave printed wiring board 21 is formed by attaching the first and second insulating substrates 21A and 21B formed as shown in FIG. 6 will be described. However, the present invention is not limited to this, and the concave printed wiring board 21 may be formed using various other methods such as a build-up method.
[0048]
Furthermore, in the first to third embodiments described above, the second electrode 3C of the interposer 3, the second electrode 12C of the printed wiring board 12, and the concave printed wiring board 21 as external electrodes corresponding to the electrodes of the mother board. The case where the second electrodes 21D are rearranged in the peripheral portions on the insulating substrates 3A, 12A, 21A on which the respective electrodes 3C, 12C, 21D are formed has been described. However, the present invention is not limited to this. For example, a new wiring line may be routed from the external electrodes 3C, 12C, and 21D and rearranged in an array on the entire surface of the insulating substrates 3A, 12A, and 21A. Alternatively, the insulating substrate 12A of the printed wiring board 12 and the first insulating substrate 21A of the concave printed wiring board 21 may be laminated in multiple layers and rearranged using several of them.
[0049]
Furthermore, in the first to third embodiments described above, the second electrodes 3C and 11C of the interposers 3 and 11 are made to widen the inter-electrode pitches of the corresponding first electrodes 3B and 11B, respectively. Although the case has been described, the present invention is not limited to this. In short, the second electrodes 3C and 11C may be formed on the interposers 3 and 11 so as to rearrange the electrode arrangement of the semiconductor chip 2 to a desired state.
[0050]
Furthermore, in the second and third embodiments described above, the insulating substrate 12A of the printed wiring board 12 and the insulating substrates 21A and 21B of the concave printed wiring board 21 are formed using glass epoxy resin. As described above, the present invention is not limited to this, and other various insulating materials may be used.
[0051]
Further, in the second and third embodiments described above, the printed wiring board 12 corresponding to the second electrodes 11C of the interposer 11 and the first electrodes 12B and 21C of the concave printed wiring board 21 and the second electrodes. The case where the electrodes 12C and 21D are conductively connected to each other through the through holes 12D and 21E has been described. However, the present invention is not limited to this, for example, along the outer periphery of the printed wiring board 12 and the concave printed wiring board 21. A wiring line may be drawn from each of the first electrodes 12B and 21C to each of the second electrodes 12C and 21D to be conductively connected.
[0052]
Further, in the above first to third embodiments, the case where the insulating substrates 3A and 11A of the interposers 3 and 11 are formed using the same silicon as the substrate of the semiconductor chip 2 has been described. However, the present invention is not limited to this, and the point is that the insulating substrates 3A and 11A of the interposers 3 and 11 are used when forming the respective electrodes of the semiconductor chip 2 such as using a material having the same or substantially the same composition as the substrate of the semiconductor chip 2. As long as the first electrodes 3B and 11B are formed using a material that can be formed using the same processing technique as the processing technique, various other compositions can be widely applied as the composition of the insulating substrate.
[0053]
【The invention's effect】
According to the present invention as described above, a semiconductor chip having a plurality of electrodes are formed on one side, on one surface of the insulating base plate made of silicon, the double speed in the same positional relationship as the respective electrodes of the semiconductor chip 1 with the electrode is formed, the respectively corresponding to each first electrode is formed a second electrode of the multiple, corresponding each first electrode and each second electrode between which the first conductive connection A plurality of third electrodes are formed in the same positional relationship as each of the second electrodes of the conversion substrate on the one surface side where the conversion substrate that is conductively connected by the means and the opening of the concave insulating substrate are provided. A plurality of fourth electrodes are formed on the other surface side of the concave insulating substrate so as to correspond to the respective third electrodes, and the corresponding third electrodes and the respective fourth electrodes are connected to the second conductive connection. It is provided a concave printed wiring board formed by conductively connected by means The semiconductor chip is mounted on one surface of the conversion substrate so that each electrode is electrically connected to each corresponding first electrode, and the concave print is formed so that each second electrode is electrically connected to each corresponding third electrode. By mounting the conversion board on one surface of the wiring board , each first electrode can be formed on the conversion board with the same pitch as each electrode of the semiconductor chip, and thus the pitch between the electrodes of the semiconductor chip is narrowed. Therefore, it is possible to realize a semiconductor device that can sufficiently cope with practical use.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment.
FIG. 2 is a plan view showing a configuration of an interposer according to the first embodiment.
FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment.
FIG. 4 is a plan view showing a configuration of an interposer according to second and third embodiments.
FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment.
FIG. 6 is a perspective view for explaining a method for forming a concave printed wiring board.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 10, 20 ... Semiconductor device, 2 ... Semiconductor chip, 2A, 23 ... Bump, 3, 11 ... Interposer, 3A, 11A ... Insulating substrate, 3B, 3C, 11B, 11C, 12B, 12C, 21C, 21D ... Electrode, 3E, 12D, 21E ... Through hole, 3D, 11D ... Wiring line, 4, 13 ... Sealing resin material, 12, 21A, 21B ... Printed wiring board, 14 ... Gold Wire, 21 ... concave printed wiring board, 22 ... opening.

Claims (2)

一面側に複数の電極が形成された半導体チツプと、
シリコンからなる絶縁基板の一面側に、上記半導体チツプの各上記電極と同じ位置関係で複数の第１の電極が形成されると共に、当該各第１の電極にそれぞれ対応させて複数の第２の電極が形成され、対応する各上記第１の電極及び各上記第２の電極同士が第１の導通接続手段により導通接続されてなる変換基板と、
凹型の絶縁基板の開口部が設けられた一面側に、上記変換基板の各上記第２の電極と同じ位置関係で複数の第３の電極が形成されると共に、上記凹型の絶縁基板の他面側に各上記第３の電極にそれぞれ対応させて複数の第４の電極が形成され、対応する各上記第３の電極及び各上記第４の電極同士が第２の導通接続手段により導通接続されてなる凹型プリント配線板と
を具え、上記半導体チツプは、各上記電極を対応する各上記第１の電極と導通接続するようにして上記変換基板の上記一面に実装され、上記変換基板は、各上記第２の電極を対応する各上記第３の電極と導通接続するようにして上記凹型プリント配線板の上記一面に実装される
ことを特徴とする半導体装置。A semiconductor chip in which a plurality of electrodes are formed on one side;
A plurality of first electrodes are formed on the one surface side of the insulating substrate made of silicon with the same positional relationship as each of the electrodes of the semiconductor chip, and a plurality of second electrodes are respectively associated with the first electrodes. A conversion substrate in which electrodes are formed, and each of the corresponding first electrodes and each of the second electrodes are conductively connected by a first conductive connection means;
A plurality of third electrodes are formed in the same positional relationship as each of the second electrodes of the conversion substrate on the one surface side provided with the opening of the concave insulating substrate, and the other surface of the concave insulating substrate. A plurality of fourth electrodes are formed on the side corresponding to the third electrodes, and the corresponding third electrodes and the fourth electrodes are conductively connected by the second conductive connecting means. The semiconductor chip is mounted on the one surface of the conversion board so as to electrically connect each of the electrodes to the corresponding first electrode. The semiconductor device, wherein the second electrode is mounted on the one surface of the concave printed wiring board so as to be conductively connected to the corresponding third electrode. 各上記第２の電極は、各上記第１の電極の電極間ピツチを広くするように形成された
ことを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1 , wherein each of the second electrodes is formed so as to widen an inter-electrode pitch of each of the first electrodes.
JP25169697A 1997-09-17 1997-09-17 Semiconductor device Expired - Fee Related JP3867875B2 (en)

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Publication number Priority date Publication date Assignee Title
US6617681B1 (en) * 1999-06-28 2003-09-09 Intel Corporation Interposer and method of making same
JP2001257307A (en) 2000-03-09 2001-09-21 Sharp Corp Semiconductor device

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