JP3701242B2 - Connection system - Google Patents

Connection system Download PDF

Info

Publication number
JP3701242B2
JP3701242B2 JP2001577610A JP2001577610A JP3701242B2 JP 3701242 B2 JP3701242 B2 JP 3701242B2 JP 2001577610 A JP2001577610 A JP 2001577610A JP 2001577610 A JP2001577610 A JP 2001577610A JP 3701242 B2 JP3701242 B2 JP 3701242B2
Authority
JP
Japan
Prior art keywords
circuit
package
connection system
circuit board
chip package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001577610A
Other languages
Japanese (ja)
Other versions
JP2003531496A (en
Inventor
ピー パネラ アウグスト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Molex LLC
Original Assignee
Molex LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/548,636 external-priority patent/US6362972B1/en
Priority claimed from US09/548,940 external-priority patent/US6612852B1/en
Application filed by Molex LLC filed Critical Molex LLC
Publication of JP2003531496A publication Critical patent/JP2003531496A/en
Application granted granted Critical
Publication of JP3701242B2 publication Critical patent/JP3701242B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
  • Connecting Device With Holders (AREA)

Abstract

A contactless interconnecting system is provided between a computer chip package and a circuit board. The chip package has a substantially planar lower surface with a pattern of discrete terminal lands. The circuit board has a substantially planar upper surface spaced from and generally parallel to the lower surface of the chip package. A pattern of discrete circuit pads on the upper surface are aligned with the terminal lands. A plurality of discrete interposer members are disposed between the terminal lands and the circuit pads and are in a pattern corresponding to and aligned with the aligned patterns of the terminal lands and circuit pads. The interposer members are preferably of a material having a higher dielectric constant that of the material filling the gaps between interposer members.

Description

【０００１】
【発明の属する技術分野】
本発明は、接点を用いることなしに得られるコンピュータチップパッケージと回路基板との間の接続一般に関する。
【０００２】
【従来の技術】
半導体デバイスがより複雑になるにつれ、シリコンウェーハ即ちダイと適切な回路ハードウェア間の接続は進化し続けており、より複雑になってきている。これは、機械的な接続が困難なためである。機械的な接続が困難なのは、電子回路の小型化と高集積化にも起因している。高周波アプリケーションの場合、電子部品内の信号は、より高い速度で伝送され、半導体パッケージはより薄く、より小さくなってきている。いくつかの高周波アプリケーションでは、金属接点や端子に依存する従来の接続を使用するのが困難である。
【０００３】
【発明が解決しようとする課題】
既知の機械的接続は、従来型の端子ピンとソケット若しくはその他のオス・メス構造、又は相互係合式スプリング接続を使用する。これらの金属対金属の接続では、汚染物質や酸化物質を取り除くために端子間で拭き取り動作（wiping action ）を行わせることが欠かせない。小型の半導体の接続においては、端子が非常に小さいため、必要とされる拭き取り動作を行って相対する端子または接点の間で確実な接触力を得るのが困難である。伝統的なはんだ接続は、仮にそれを用いることが可能であったとしても、半導体の接続システムの小型化され間隔が狭められた部品のために必要となるハードツーリング（hard tooling）が極めて複雑となり、はんだ接続の使用は困難である。
【０００４】
従って、本発明は、機械的な接触に依存することなく、電界結合又は磁界結合を用いて、二つの端子又は接点の間で信号を伝達するコネクタに関する。
【０００５】
従って、本発明の全般的な目的は、コンピュータチップパッケージと回路基板との間の接続を提供するのに特に適した新規で改良された無接点接続システムを提供することである。
【０００６】
本発明の別の目的は、接続を提供するために金属対金属の接触を用いるのではなく、誘電性の材料によって分離された第一と第二の端子列間の容量結合を利用した接続構造を提供することである。
【０００７】
【課題を解決するための手段】
本発明の一実施形態においては、コンピュータチップパッケージが、平坦な支持体に取り付けられている。この支持体上には複数のコンタクトパッド又はトレース（trace ）が形成され、チップの出力とコンタクトパッドを接続するためにリード線又はその他の接続が提供されている。コンタクトパッドは支持体の一方の面に取り付けられ、支持体のコンタクトパッドが回路基板上の対応する相手側のコンタクトパッド又はトレースと位置が整合されて対向するように支持体が回路基板上で位置決めされる。容量結合を利用して二個の対向するコンタクトパッドの間で信号を伝達する。
【０００８】
別の実施形態においては、複数のコンタクトを所定のパターンで両面に配置した平坦な支持体にコンピュータチップパッケージが取り付けられている。これらのコンタクトはビアによって相互に接続されており、その結果、パッケージは一連の分離した端子ランドをその下面に持つ。また、回路基板が提供されるが、この回路基板の上面には、コンピュータチップパッケージの下面上の端子ランドと位置が整合された複数の分離した回路パッドが設けられている。１個以上の分離した誘電性中間部材がチップパッケージの端子ランドと回路基板上の回路パッドとの間に設けられている。この中間部材は、端子ランドと回路パッドのパターンに対応したパターンで配置されており、さらに、端子ランドと回路パッドと位置が整合され、それらの間に設けられている。前記中間部材は、誘電率が比較的高い（好ましくは２００以上）材料からなる。
【０００９】
中間部材は端子ランド又は回路パッドの何れかに接着されるか、別の実施形態に記載されている様に、中間部材はチップパッケージの下面と回路基板の上面との間に配置された平坦なキャリアによって支持される。この平坦なキャリアは誘電性のエラストマ材料で作ることができ、中間部材は平坦なキャリア部材中にオーバーモールドによって成形することができる。
【００１０】
本発明の他の目的、特徴及び利点は、添付の図に関連付けて行った以下の詳細な記載から明らかになるであろう。
【００１１】
新規であると考える本発明の特徴は添付の特許請求の範囲に詳細に記載されている。本発明及びその目的と利点は添付の図面と関連づけて行った下記の記載を参照することによって最も良く理解できるであろう。
【００１２】
【発明の実施の形態】
図１は無接点接続システムの第一の実施形態を示し、その全体が１０で示されている。該無接点接続システムは、コンピュータチップパッケージ１２に対して所定の位置に位置決めした状態で示され、コンピュータチップパッケージ１２と、その下側にあるプリント回路基板等の基板１４との間の接続を提供する。図２は無接点接続システムの第二の実施形態を示し、その全体が１０Ａで示されており、チップパッケージ１２と回路基板１４との間に使用されるものである。
【００１３】
両実施形態１０、１０Ａにおけるコンピュータチップパッケージ１２は、ハウジング２２の壁２０の上面１８に取り付けられ、ハウジング２２の中に配置されたシリコンウェーハ１６を含む。分離した導電性端子ランド２４のパターンが、壁２０の上面１８上に堆積によって形成されている。シリコンウェーハ１６は、複数のリード線２６によってこれらの導電性ランド２４に接続されている。本実施形態においては、分離した導電性端子ランド即ち接触パッド３０がチップパッケージ１２の支持壁１８の下面３２に配置されており、上記端子ランド２４は、端子ランド３０の対応するパターンに個々のビア２８により支持壁１８を通して接続されている。
【００１４】
接続システム１０、１０Ａの回路基板１４は、チップパッケージ１２の下面３２と平行に配置された略平坦な上面３４を有する。分離した回路パッド３６の各々がチップパッケージ支持壁の下面３２上の端子ランド３０の内の１つと位置が整合するように、分離した回路パッド３６のパターンが上面３４上に配置されている。回路パッド２８は、慣用の方法で回路基板１４上の各々の回路に電気的に接続されている。
【００１５】
複数の分離した中間部材３８が、支持壁２０の底の端子ランド３０と、回路基板１４の上面、即ち対向する面の上に設けられた回路パッド３６との間に配置されている。本実施形態の中間部材３８、３８’は、図１、図２では水平方向に離間されているものとして示されている中間ギャップ４０、４０’によって相互に離間されており、端子ランド３０と回路パッド３６の両方のパターンに対応し略位置が整合されたパターンになっている。中間部材３８は、斜め方向にあるか或いは隣接する端子ランド３０と回路パッド３６との間の結合を避けるために、ギャップ４０内の材料の誘電率よりも高い誘電率を有する材料で作るのが好ましい。中間部材３８、３８’の誘電率は、ギャップ４０、４０’内の材料（典型的には空気）よりも少なくとも一桁大きく、中間部材３８、３８’の誘電率は少なくとも２００であることが好ましい。しかしながら、信号周波数が高くなるに従って、中間部材が持つべき誘電率は低下するであろう。これらの実施形態においては、斜め方向又は隣接するランドやパッド間の望ましくない結合を生じさせることなく、所望のランドとパッドの組の間の容量結合を確保するために、端子ランドは回路基板パッド３６と同等か等しい寸法とし、回路基板パッド３６と位置を整合させることが好ましい。
【００１６】
図１の中間部材３８は、チップパッケージの下面３２と回路基板の上面３４との間に配置された平坦であることが好ましい面のキャリア部材４２によって支持されている。このキャリア部材４２は、図示の様にコンピュータチップパッケージ１２の全長及び全幅にわたって延在し、好ましくは、プラスチック等の誘電性材料、或いはゴムやエラストマー等の誘電性で可撓性のある材料から作られる。前記中間部材は、キャリア部材４２にオーバーモールド（over-mold ）によって設けることができ、キャリア部材４２はこのオーバーモールドプロセスに適応させるための一連の穴を含む。中間部材３８の誘電率は、望ましくない選択されていない斜め方向の結合を阻止するために、キャリア部材４２の誘電率よりも一桁以上大きいことが好ましい。
【００１７】
図２は無接点接続システム１０Ａの第二の実施形態を示し、図１の第一実施形態で使用されていたキャリア部材４２が取り除かれている。本実施形態においては、端子ランド３０と回路パッド３６内の何れか一方またはそれらの両方に中間部材３８’が接着されている。例えば、中間部材は、適切な印刷方法によって端子ランド３０又は回路パッド３６の何れかに形成できる。しかし、本実施形態においても中間部材の間にギャップ４０’が設けられている。中間部材３８’の誘電率は、斜め方向の結合を避けるために、ギャップ４０’を埋める材料（例えば空気）よりも一桁以上大きくすべきである。
【００１８】
図１と図２に示す無接点接続システム１０と１０Ａの実施形態においては、中間部材３８、３８’が分離した部材であり、上記したようにギャップ４０、４０’で離間されている。前記中間部材は、位置が整合された端子ランド３０及び回路パッド３６と略同じ大きさであるのが好ましい。電気信号は、端子ランド３０から中間部材３８、３８’を介して回路パッド３６に静電的に伝達される。中間部材よりも誘電率が低い中間部材間ギャップ４０、４０’は、斜め方向の端子ランド３０と回路パッド３６との間で絶縁破壊強度を規定する。電気信号は高誘電率の材料を介して結合しやすいため、電気信号は中間部材の間のギャップ４０、４０’を通り抜けようとはしない。なぜなら、中間部材は、ギャップ４０、４０’よりも誘電率が高い材料で作られているためである。従って、分離即ち離間された中間部材は、端子ランド３０と回路パッド３６の斜め方向の組の間のクロスカップリングやクロストークを大幅に減少させる。
【００１９】
明細書及び特許請求の範囲で使用される「上側」、「下側」、「上部」、「底部」、「垂直」等の語の使用は、本発明を限定することを意図するものではない。これらの語は、図に示した発明の記述と理解を明確かつ簡潔にするために用いられているにすぎない。従って、無接点接続システム１０と１０Ａは、いかなる向きでも使用又は適用できる。
【００２０】
図３に示す本発明の第三の実施形態では、無接点接続システム１１０がコンピュータチップパッケージ１１２と回路基板等の基板１１４との間に設けられている。
【００２１】
チップパッケージ１１２は、底部支持壁１１６を有するハウジング１１５を含み、シリコンウェーハ１１８は、支持壁１１６の略平坦な上面１２０に取り付けられている。支持壁１１６は、分離した端子ランド１２２のパターンを支持している。分離した端子ランド１２２は、支持壁１１６の上面１２０上に設けられ、個々のリード線１２４によってシリコンウェーハ１１８に接続されている。端子ランド１２２のパターンは、複数のギャップ１２３を端子ランド間に形成する。本実施形態における支持壁１１６は、図１と図２の実施形態で用いた該中間部材と同じ機能を提供する。
【００２２】
システム１１０の回路基板１１４は、チップパッケージ１１２の支持壁１１６の下側に略平行に配置される。回路基板１１４は、端子ランド１２２と位置が整合された分離回路パッド１２８のパターンが形成された平坦な上面１２６を有する。分離した回路パッド１２８のパターンは、分離した端子ランド１２２のパターンにより形成されたギャップ１２３と同様な空間１２９を回路パッド１２８間に形成する。回路パッド１２８は、回路基板１１４上の各回路に電気的に接続される。
【００２３】
本発明は、コンピュータチップパッケージ１１２の支持壁１１６が、チップパッケージの端子ランド１２２と回路基板１１４の回路パッド１２８との間に直接配置されることを想定している。本実施形態においては、壁１６の下面１２１が、回路パッド１２８上に直接取り付けられる。別の実施形態においては、隣接する端子ランド１２２間のクロスカップリング及び隣接する回路パッド間のクロスカップリングを避けるために、ギャップ１２３と空間１２９を埋める材料（例えば空気）に比べて誘電率の高い材料で壁が作られている。更に別の実施形態においては、前記壁は、少なくとも誘電率が２００の材料で作られる。もちろん、種々の材料や組成物を使用することにより、その様な所望の誘電率を得ることができる。しかし、信号周波数が高くなると、壁１１６のが持つべき誘電率の大きは低下するであろう。追加の実施形態においては、端子ランド１２２間のギャップ１２３及び回路パッド１２８間の空間１２９の幅に比べて壁１１６の厚さを薄くし、位置が合わされた端子ランド１２２と回路パッド１２８との間の結合を促進し、隣接する端子ランド１２２間又は隣接する回路パッド１２８間のクロスカップリングを防止している。
【００２４】
上記からわかるように、コンピュータチップパッケージの一部（例えば壁１１６）は、シリコンウェーハ１１８と回路基板１１４との間で電磁結合を提供するために効果的に使われる。本質的に、壁１６は支持構造を提供するとともに複数のコンデンサー内の中間誘電性媒体を提供する。端子パッド１２２と回路パッド１２８は、壁１１６によって提供された中間誘電性媒体の両側で半コンデンサーとして機能する。信号は、チップパッケージの端子ランド１２２と回路基板１１４の回路パッド１２８との間で静電的に伝えられる。従って、その他の外部接続部品は全て無くすことができ、回路基板１１４は回路パッド１２８と共に、チップパッケージの支持壁１１６の底面に隣接して接続した状態で取り付けることができる。
【００２５】
本発明は、本発明の精神又は主要な特徴から逸脱することなしに、他の特定の形態で実施できることは分かるであろう。従って、上記の本実施例及び実施形態は、いかなる点においても例示であり限定的でないと考えなければならず、本発明は本明細書に記載した細部に限定されるものではない。
【図面の簡単な説明】
【図１】本発明による無接点接続システムの一実施形態の断面図である。
【図２】本発明の第二の実施形態を示すコンピュータチップパッケージの断面図である。
【図３】本発明の第三の実施形態を示すコンピュータチップパッケージの断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates generally to connections between computer chip packages and circuit boards obtained without the use of contacts.
[0002]
[Prior art]
As semiconductor devices become more complex, the connections between silicon wafers or dies and appropriate circuit hardware continue to evolve and become more complex. This is because mechanical connection is difficult. The difficulty in mechanical connection is due to the miniaturization and high integration of electronic circuits. For high frequency applications, signals in electronic components are transmitted at higher speeds, and semiconductor packages are becoming thinner and smaller. In some high frequency applications, it is difficult to use conventional connections that rely on metal contacts or terminals.
[0003]
[Problems to be solved by the invention]
Known mechanical connections use conventional terminal pins and sockets or other male-female structures, or interengaging spring connections. In these metal-to-metal connections, it is essential to have a wiping action between the terminals to remove contaminants and oxides. In the connection of a small semiconductor, since the terminals are very small, it is difficult to obtain a reliable contact force between opposing terminals or contacts by performing a necessary wiping operation. Traditional solder connections, even if they can be used, are extremely complex in the hard tooling required for miniaturized and closely spaced components in semiconductor connection systems. The use of solder connections is difficult.
[0004]
Accordingly, the present invention relates to a connector that transmits a signal between two terminals or contacts using electric field coupling or magnetic field coupling without relying on mechanical contact.
[0005]
Accordingly, it is a general object of the present invention to provide a new and improved contactless connection system that is particularly suitable for providing a connection between a computer chip package and a circuit board.
[0006]
Another object of the invention is a connection structure that utilizes capacitive coupling between first and second terminal rows separated by a dielectric material, rather than using metal-to-metal contact to provide a connection. Is to provide.
[0007]
[Means for Solving the Problems]
In one embodiment of the invention, the computer chip package is attached to a flat support. A plurality of contact pads or traces are formed on the support, and leads or other connections are provided to connect the chip output to the contact pads. A contact pad is attached to one side of the support and the support is positioned on the circuit board so that the contact pad of the support is aligned and opposite to the corresponding mating contact pad or trace on the circuit board. Is done. A signal is transmitted between two opposing contact pads using capacitive coupling.
[0008]
In another embodiment, the computer chip package is attached to a flat support having a plurality of contacts arranged on both sides in a predetermined pattern. These contacts are interconnected by vias so that the package has a series of separate terminal lands on its underside. Also provided is a circuit board, on the top surface of which is provided with a plurality of separate circuit pads aligned with the terminal lands on the bottom surface of the computer chip package. One or more separate dielectric intermediate members are provided between the terminal lands of the chip package and the circuit pads on the circuit board. The intermediate members are arranged in a pattern corresponding to the pattern of the terminal lands and the circuit pads, and the positions of the terminal lands and the circuit pads are aligned and provided between them. The intermediate member is made of a material having a relatively high dielectric constant (preferably 200 or more).
[0009]
The intermediate member is bonded to either the terminal land or the circuit pad, or as described in another embodiment, the intermediate member is a flat surface disposed between the lower surface of the chip package and the upper surface of the circuit board. Supported by a carrier. The flat carrier can be made of a dielectric elastomer material and the intermediate member can be molded by overmolding into the flat carrier member.
[0010]
Other objects, features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.
[0011]
The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention and its objects and advantages may best be understood by referring to the following description taken in conjunction with the accompanying drawings.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a first embodiment of a contactless connection system, generally designated 10. The contactless connection system is shown positioned at a predetermined position relative to the computer chip package 12 and provides a connection between the computer chip package 12 and a substrate 14 such as a printed circuit board underlying the computer chip package 12. To do. FIG. 2 shows a second embodiment of the contactless connection system, which is indicated as a whole by 10A, and is used between the chip package 12 and the circuit board 14.
[0013]
The computer chip package 12 in both embodiments 10, 10A includes a silicon wafer 16 mounted on the top surface 18 of the wall 20 of the housing 22 and disposed within the housing 22. A pattern of separated conductive terminal lands 24 is formed on the upper surface 18 of the wall 20 by deposition. The silicon wafer 16 is connected to these conductive lands 24 by a plurality of lead wires 26. In the present embodiment, separated conductive terminal lands or contact pads 30 are arranged on the lower surface 32 of the support wall 18 of the chip package 12, and the terminal lands 24 are individually connected to the corresponding patterns of the terminal lands 30. 28 through the support wall 18.
[0014]
The circuit board 14 of the connection system 10, 10 </ b> A has a substantially flat upper surface 34 disposed in parallel with the lower surface 32 of the chip package 12. A pattern of separated circuit pads 36 is disposed on the upper surface 34 such that each of the separated circuit pads 36 is aligned with one of the terminal lands 30 on the lower surface 32 of the chip package support wall. The circuit pad 28 is electrically connected to each circuit on the circuit board 14 in a conventional manner.
[0015]
A plurality of separated intermediate members 38 are disposed between the terminal lands 30 at the bottom of the support wall 20 and the circuit pads 36 provided on the upper surface of the circuit board 14, that is, the opposing surface. The intermediate members 38, 38 'of the present embodiment are separated from each other by intermediate gaps 40, 40', which are shown as being horizontally spaced in FIGS. It corresponds to both patterns of the pad 36 and is a pattern whose approximate positions are aligned. The intermediate member 38 is made of a material having a dielectric constant that is higher than the dielectric constant of the material in the gap 40 in order to avoid coupling between the terminal land 30 and the circuit pad 36 that are oblique or adjacent to each other. preferable. The dielectric constant of the intermediate members 38, 38 'is preferably at least an order of magnitude greater than the material (typically air) in the gaps 40, 40', and the dielectric constant of the intermediate members 38, 38 'is preferably at least 200. . However, as the signal frequency increases, the dielectric constant that the intermediate member should have will decrease. In these embodiments, the terminal lands are circuit board pads to ensure capacitive coupling between the desired land and pad pair without causing undesired coupling between diagonal lands or adjacent lands or pads. Preferably, the dimensions are equal to or equal to 36 and aligned with the circuit board pads 36.
[0016]
The intermediate member 38 of FIG. 1 is supported by a carrier member 42 having a plane that is preferably flat and disposed between the lower surface 32 of the chip package and the upper surface 34 of the circuit board. The carrier member 42 extends over the entire length and width of the computer chip package 12 as shown, and is preferably made of a dielectric material such as plastic, or a dielectric and flexible material such as rubber or elastomer. It is done. The intermediate member may be provided to the carrier member 42 by over-molding, and the carrier member 42 includes a series of holes to accommodate this overmolding process. The dielectric constant of the intermediate member 38 is preferably an order of magnitude greater than the dielectric constant of the carrier member 42 to prevent unwanted unselected oblique coupling.
[0017]
FIG. 2 shows a second embodiment of the contactless connection system 10A, in which the carrier member 42 used in the first embodiment of FIG. 1 has been removed. In the present embodiment, an intermediate member 38 ′ is bonded to one or both of the terminal land 30 and the circuit pad 36. For example, the intermediate member can be formed on either the terminal land 30 or the circuit pad 36 by an appropriate printing method. However, also in this embodiment, a gap 40 ′ is provided between the intermediate members. The dielectric constant of the intermediate member 38 'should be an order of magnitude greater than the material (eg, air) that fills the gap 40' to avoid oblique coupling.
[0018]
In the embodiment of the contactless connection system 10 and 10A shown in FIGS. 1 and 2, the intermediate members 38 and 38 ′ are separate members and are separated by the gaps 40 and 40 ′ as described above. The intermediate member is preferably substantially the same size as the terminal land 30 and the circuit pad 36 whose positions are aligned. The electric signal is electrostatically transmitted from the terminal land 30 to the circuit pad 36 through the intermediate members 38 and 38 '. The gaps 40 and 40 ′ between the intermediate members having a dielectric constant lower than that of the intermediate member define the dielectric breakdown strength between the terminal land 30 and the circuit pad 36 in the oblique direction. Since the electrical signal is likely to couple through a high dielectric constant material, the electrical signal does not attempt to pass through the gap 40, 40 ′ between the intermediate members. This is because the intermediate member is made of a material having a higher dielectric constant than the gaps 40 and 40 '. Accordingly, the separated or spaced apart intermediate members significantly reduce cross coupling and crosstalk between the diagonally set of terminal lands 30 and circuit pads 36.
[0019]
The use of the terms “upper”, “lower”, “top”, “bottom”, “vertical”, etc. as used in the specification and claims is not intended to limit the invention. . These terms are only used to clarify and simplify the description and understanding of the invention shown in the figures. Accordingly, the contactless connection systems 10 and 10A can be used or applied in any orientation.
[0020]
In the third embodiment of the present invention shown in FIG. 3, a contactless connection system 110 is provided between a computer chip package 112 and a substrate 114 such as a circuit board.
[0021]
The chip package 112 includes a housing 115 having a bottom support wall 116, and a silicon wafer 118 is attached to the substantially flat top surface 120 of the support wall 116. The support wall 116 supports the pattern of the separated terminal lands 122. The separated terminal lands 122 are provided on the upper surface 120 of the support wall 116 and are connected to the silicon wafer 118 by individual lead wires 124. The pattern of the terminal lands 122 forms a plurality of gaps 123 between the terminal lands. The support wall 116 in this embodiment provides the same function as the intermediate member used in the embodiment of FIGS. 1 and 2.
[0022]
The circuit board 114 of the system 110 is disposed substantially parallel to the lower side of the support wall 116 of the chip package 112. The circuit board 114 has a flat upper surface 126 on which a pattern of the isolation circuit pads 128 aligned with the terminal lands 122 is formed. The pattern of the separated circuit pads 128 forms a space 129 between the circuit pads 128 similar to the gap 123 formed by the pattern of the separated terminal lands 122. The circuit pad 128 is electrically connected to each circuit on the circuit board 114.
[0023]
The present invention contemplates that the support wall 116 of the computer chip package 112 is disposed directly between the terminal lands 122 of the chip package and the circuit pads 128 of the circuit board 114. In the present embodiment, the lower surface 121 of the wall 16 is directly mounted on the circuit pad 128. In another embodiment, the dielectric constant relative to the material that fills the gap 123 and space 129 (eg, air) to avoid cross coupling between adjacent terminal lands 122 and cross coupling between adjacent circuit pads. The walls are made of high materials. In yet another embodiment, the wall is made of a material having a dielectric constant of at least 200. Of course, such a desired dielectric constant can be obtained by using various materials and compositions. However, the higher the signal frequency, the lower the dielectric constant that the wall 116 should have. In an additional embodiment, the wall 116 is thinner than the gap 123 between the terminal lands 122 and the width of the space 129 between the circuit pads 128, so that the aligned terminal lands 122 and the circuit pads 128 are aligned. And the cross coupling between adjacent terminal lands 122 or adjacent circuit pads 128 is prevented.
[0024]
As can be seen from the above, a portion of the computer chip package (eg, wall 116) is effectively used to provide electromagnetic coupling between the silicon wafer 118 and the circuit board 114. In essence, the wall 16 provides a support structure and an intermediate dielectric medium within the plurality of capacitors. Terminal pads 122 and circuit pads 128 function as half capacitors on both sides of the intermediate dielectric medium provided by wall 116. The signal is electrostatically transmitted between the terminal land 122 of the chip package and the circuit pad 128 of the circuit board 114. Therefore, all other external connection parts can be eliminated, and the circuit board 114 can be attached together with the circuit pads 128 while being connected adjacent to the bottom surface of the support wall 116 of the chip package.
[0025]
It will be appreciated that the invention may be embodied in other specific forms without departing from the spirit or key characteristics of the invention. Accordingly, the examples and embodiments described above are to be considered in all respects as illustrative and not restrictive, and the invention is not limited to the details described herein.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of an embodiment of a contactless connection system according to the present invention.
FIG. 2 is a cross-sectional view of a computer chip package showing a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of a computer chip package showing a third embodiment of the present invention.

Claims (10)

分離した端子ランドを配置した平坦な下面を持つコンピュータチップパッケージと、
チップパッケージの下面から離間され該下面と略平行な平坦な上面を備え、前記端子ランドと位置を整合させた分離した回路パッドを該上面に配置した回路基板とを有する、コンピュータチップパッケージと回路基板との間の接続システムにおいて、
複数の分離した別個の誘電性の中間部材が端子ランドと回路パッドとの間に配置され、更に、端子ランド及び回路パッドの位置が整合されたパターンに対応し且つ位置が整合されたパターンで該中間部材が配置されていることを特徴とする接続システム。A computer chip package having a flat bottom surface with separated terminal lands, and
A computer chip package and a circuit board, comprising: a circuit board having a flat upper surface spaced apart from the lower surface of the chip package and substantially parallel to the lower surface; and a circuit board on which the separated circuit pads are aligned with the terminal lands. In the connection system between
A plurality of separate and distinct dielectric intermediate members are disposed between the terminal lands and the circuit pads, and further, the terminal lands and the circuit pads are positioned in a pattern that corresponds to and is aligned. A connection system in which an intermediate member is arranged. 前記端子ランドはコンピュータチップパッケージの壁の下面上に配置され、壁を貫通するビアによりパッケージのシリコンウェーハからのリード線に接続されている、請求項１に記載の接続システム。  The connection system according to claim 1, wherein the terminal land is disposed on a lower surface of a wall of the computer chip package, and is connected to a lead wire from the silicon wafer of the package by a via penetrating the wall. 前記中間部材は、前記端子ランド又は回路パッドの何れか一方に接着されている、請求項１に記載の接続システム。  The connection system according to claim 1, wherein the intermediate member is bonded to either the terminal land or the circuit pad. 前記分離した中間部材はそれらの間にギャップを形成し、前記中間部材は該ギャップを満たしている材料よりも誘電率が高い材料によって形成されている、請求項１に記載の接続システム。  The connection system according to claim 1, wherein the separated intermediate members form a gap therebetween, and the intermediate member is formed of a material having a higher dielectric constant than a material filling the gap. 分離した端子ランドを配置した下面を持つコンピュータチップパッケージと、
チップパッケージの下面から離間され該下面と略平行な上面を備え、前記端子ランドと位置を整合させた分離した回路パッドを含む回路基板とを有する、コンピュータチップパッケージと回路基板との間の接続システムにおいて、
チップパッケージの下面と回路基板の上面との間に配置されたキャリア部材によって支持された複数の分離した誘電性の中間部材を有し、キャリア部材は、前記チップパッケージの下面と前記回路基板の上面との間で幅方向に延在し、中間部材は、前記端子ランドと回路パッドのパターンに対応し且つ略位置が整合されたパターンで前記キャリア部材上に配置され、前記キャリア部材よりも高い誘電率を有していることを特徴とする接続システム。A computer chip package having a bottom surface with separated terminal lands, and
A connection system between a computer chip package and a circuit board, comprising: a circuit board including a separated circuit pad aligned with the terminal land, the upper surface being spaced apart from the lower surface of the chip package and substantially parallel to the lower surface In
A plurality of separate dielectric intermediate members supported by a carrier member disposed between the lower surface of the chip package and the upper surface of the circuit board, wherein the carrier member is a lower surface of the chip package and the upper surface of the circuit board; The intermediate member is disposed on the carrier member in a pattern corresponding to the pattern of the terminal land and the circuit pad and having a substantially aligned position, and has a higher dielectric than the carrier member. A connection system characterized by having a rate. 前記端子ランドはコンピュータチップパッケージの壁の下面上に配置され、壁を貫通するビアによりパッケージのシリコンウェーハからのリード線に接続されている、請求項５に記載の接続システム。  6. The connection system according to claim 5, wherein the terminal land is disposed on a lower surface of a wall of the computer chip package, and is connected to a lead wire from the silicon wafer of the package by a via penetrating the wall. 前記中間部材は平坦なキャリア部材上にオーバーモールドによって成形されたものである、請求項５に記載の接続システム。  The connection system according to claim 5, wherein the intermediate member is formed by overmolding on a flat carrier member. 前記平坦なキャリア部材は誘電性エラストマ材料から作られたものである、請求項５に記載の接続システム。  6. A connection system according to claim 5, wherein the flat carrier member is made of a dielectric elastomer material. パッケージ内に配置されたコンピュータチップを有し、該コンピュータチップは、コンピュータチップの回路を他の回路に接続するためにコンピュータチップから延在する複数のリード線を備えている、コンピュータチップパッケージと回路基板との間の接続システムにおいて、
該パッケージは、所定の誘電率を持つ材料から形成された支持壁を備え、該支持壁はチップを支持するとともにパッケージを回路基板に取り付けるためのものであり、前記パッケージは、前記支持壁の上面に配置され前記チップのリード線に接続された複数の分離した導電性端子ランドを含んでおり、
前記パッケージの支持壁に近接して回路基板が配置され、この回路基板の実質的に平坦な上面には分離した回路パッドが設けられ、該回路パッドは誘電性材料を介して前記誘電性端子ランドと接続され、単一の回路パッドが前記パッケージの単一の端子ランドと位置が整合するように該回路パッドが配置されていることを特徴とする接続システム。A computer chip package and circuit having a computer chip disposed in the package, the computer chip comprising a plurality of leads extending from the computer chip to connect the circuit of the computer chip to another circuit In the connection system between boards,
The package includes a support wall formed of a material having a predetermined dielectric constant. The support wall supports a chip and attaches the package to a circuit board. The package is an upper surface of the support wall. A plurality of separate conductive terminal lands disposed on and connected to the lead wires of the chip,
A circuit board is disposed adjacent to the support wall of the package, and a separate circuit pad is provided on a substantially flat upper surface of the circuit board, and the circuit pad is connected to the dielectric terminal land via a dielectric material. And the circuit pad is arranged so that the single circuit pad is aligned with the single terminal land of the package. 前記支持壁は前記パッケージの外壁を形成する、請求項９に記載の接続システム。  The connection system according to claim 9, wherein the support wall forms an outer wall of the package.
JP2001577610A 2000-04-13 2001-04-12 Connection system Expired - Fee Related JP3701242B2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US09/548,636 US6362972B1 (en) 2000-04-13 2000-04-13 Contactless interconnection system
US09/548,636 2000-04-13
US09/548,940 US6612852B1 (en) 2000-04-13 2000-04-13 Contactless interconnection system
US09/548,940 2000-04-13
PCT/US2001/012020 WO2001080316A2 (en) 2000-04-13 2001-04-12 Contactless interconnection system

Publications (2)

Publication Number Publication Date
JP2003531496A JP2003531496A (en) 2003-10-21
JP3701242B2 true JP3701242B2 (en) 2005-09-28

Family

ID=27068917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001577610A Expired - Fee Related JP3701242B2 (en) 2000-04-13 2001-04-12 Connection system

Country Status (7)

Country Link
EP (1) EP1273040A2 (en)
JP (1) JP3701242B2 (en)
KR (1) KR20020090233A (en)
CN (1) CN1237612C (en)
AU (1) AU2001251588A1 (en)
TW (1) TW547773U (en)
WO (1) WO2001080316A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100336218C (en) * 2003-08-25 2007-09-05 威盛电子股份有限公司 High-frequency IC multi-bus knot tying structure and method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2902002A1 (en) * 1979-01-19 1980-07-31 Gerhard Krause Three=dimensional integrated circuits - mfd. by joining wafer stack with contacts through conductive adhesive
JPH0583011A (en) * 1991-09-25 1993-04-02 Sumitomo Electric Ind Ltd Input/output coupling device for package for semiconductor device
US6728113B1 (en) * 1993-06-24 2004-04-27 Polychip, Inc. Method and apparatus for non-conductively interconnecting integrated circuits
JPH0998005A (en) * 1995-09-29 1997-04-08 Nec Corp Printed circuit board
US6396712B1 (en) * 1998-02-12 2002-05-28 Rose Research, L.L.C. Method and apparatus for coupling circuit components

Also Published As

Publication number Publication date
JP2003531496A (en) 2003-10-21
WO2001080316A2 (en) 2001-10-25
CN1422440A (en) 2003-06-04
WO2001080316A3 (en) 2002-03-21
CN1237612C (en) 2006-01-18
KR20020090233A (en) 2002-11-30
AU2001251588A1 (en) 2001-10-30
EP1273040A2 (en) 2003-01-08
TW547773U (en) 2003-08-11

Similar Documents

Publication Publication Date Title
US6008534A (en) Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines
US6916181B2 (en) Remountable connector for land grid array packages
TW541670B (en) Semiconductor device
US7113408B2 (en) Contact grid array formed on a printed circuit board
EP1323340B1 (en) System and method for connecting a power converter to a land grid array socket
US6948943B2 (en) Shunting arrangements to reduce high currents in grid array connectors
US20060138630A1 (en) Stacked ball grid array packages
KR100543853B1 (en) Capacitor with extended surface lands and method of fabrication therefor
JP3927783B2 (en) Semiconductor parts
US6612852B1 (en) Contactless interconnection system
US6396710B1 (en) High density interconnect module
US20060141667A1 (en) Bare die socket
JP3701242B2 (en) Connection system
US6724077B2 (en) Semiconductor package having multi-signal bus bars
US6362972B1 (en) Contactless interconnection system
KR102578797B1 (en) Semiconductor package
WO1981003396A1 (en) Integrated circuit package with multi-contact pins
JP2011134789A (en) Semiconductor device, and printed circuit board
JP2935356B2 (en) Semiconductor device and substrate, and mounting structure of semiconductor device
WO2004093252A2 (en) Electrical connector and method for making
US20240063562A1 (en) Electrical connector with integrated ground plane
KR20230122783A (en) Electrical connector for signal transmission
JP2002124628A (en) Semiconductor device
JPH10326653A (en) Connector
JPH09270484A (en) Ic socket

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040913

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040921

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041213

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050125

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050330

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050426

R155 Notification before disposition of declining of application

Free format text: JAPANESE INTERMEDIATE CODE: R155

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050712

R150 Certificate of patent or registration of utility model

Ref document number: 3701242

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090722

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100722

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110722

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110722

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120722

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120722

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130722

Year of fee payment: 8

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees