JP3864229B2 - Method for producing nanogap electrode and device having nanogap electrode produced by the method - Google Patents
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- 238000000034 method Methods 0.000 title claims description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims description 21
- 238000007740 vapor deposition Methods 0.000 claims description 21
- 230000008021 deposition Effects 0.000 claims description 15
- 230000005684 electric field Effects 0.000 claims description 15
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- 238000005530 etching Methods 0.000 claims description 4
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- 238000010894 electron beam technology Methods 0.000 description 12
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- 229910052751 metal Inorganic materials 0.000 description 12
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000004380 ashing Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 239000002086 nanomaterial Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 239000002105 nanoparticle Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ion Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
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- 238000010438 heat treatment Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
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Description
本発明は、ナノメートル・オーダーの間隔幅を持つナノギャップ電極の製造方法及び該方法により製造されたナノギャップ電極を有する素子に関するものである。 The present invention relates to a method for producing a nanogap electrode having an interval width on the order of nanometers and a device having a nanogap electrode produced by the method.
現在電気素子の微細化が進み、有機分子やナノ微粒子などナノ構造の特性を直接利用したデバイスの作製が求められている。このようなデバイスの実現には、ナノ構造と同じサイズの間隙幅をもつナノギャップ電極が必要である。有機分子は近年分子の合成技術が向上し、現在１０ｎｍをやや超える大きさの分子の合成も可能となっている。しかし、そのような大きな合成有機分子は系の選択肢が限られるため、より小さなギャップ電極が望ましい。また、ナノ微粒子においても、室温で量子効果の発現を求めると、より小さい系（特に金属では２〜３ｎｍ以下）が必要になる。これらの理由によりナノスケール素子にとって、間隔幅がナノメートル・オーダー、特に５ｎｍ以下のナノギャップ電極の有効性は非常に高いと考えられる。 At present, miniaturization of electrical elements is progressing, and there is a demand for the production of devices that directly utilize the characteristics of nanostructures such as organic molecules and nanoparticles. Realization of such a device requires a nanogap electrode having a gap width the same size as the nanostructure. In recent years, organic molecules have been improved in molecular synthesis technology, and it is now possible to synthesize molecules with sizes slightly exceeding 10 nm. However, smaller gap electrodes are desirable because such large synthetic organic molecules have limited system choices. In addition, in the case of nano-particles, a smaller system (particularly, 2 to 3 nm or less for metals) is required when the quantum effect is to be expressed at room temperature. For these reasons, it is considered that the effectiveness of a nanogap electrode having an interval width of the order of nanometers, particularly 5 nm or less, is very high for a nanoscale device.
一方、ナノスケールの電極構造の作製は、一般的に電子ビーム露光に代表される、加工精度の高いパターニング手法により実現されている。しかし、電子ビーム露光はランニングコストが高く、実用化の段階で大きな障害になると考えられる。さらに、通常の電子ビーム露光は１０ｎｍ程度の加工精度しか有していない。この限界をクリアするため、他の手法と組み合わせる必要がある。これまで、間隙幅がナノメートル・オーダーの平面型ナノギャップ電極を作る手法として以下の手法が報告されている。 On the other hand, fabrication of a nanoscale electrode structure is realized by a patterning technique with high processing accuracy, typically represented by electron beam exposure. However, electron beam exposure has a high running cost and is considered to be a major obstacle at the stage of practical use. Furthermore, normal electron beam exposure has a processing accuracy of only about 10 nm. In order to clear this limit, it is necessary to combine with other methods. So far, the following methods have been reported as methods for producing planar nanogap electrodes with a gap width of the order of nanometers.
１）Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．７５（１９９９）３０１
この文献で紹介されている手法は、金の細線に電流を流すことにより、金の細線の特に細い部分を局所的に電界破断させ、ギャップ構造を作製する手法である。しかし、この手法では、ギャップが形成される位置はこの細い部分のランダムな個所で規定できない。また、この手法はランコストの高い電子ビーム露光による微細な加工を組み合わせており、光露光レベルの加工精度の細線では電界破断の有効性は確認されていない。（我々の実験では、光露光の範囲でうまく破断できなかった。）
1) Appl. Phys. Lett. 75 (1999) 301
The technique introduced in this document is a technique for producing a gap structure by causing an electric current to flow through a gold thin wire to locally break an electric field at a particularly thin portion of the gold thin wire. However, in this method, the position where the gap is formed cannot be defined by a random portion of this thin portion. In addition, this technique is combined with fine processing by electron beam exposure with high run cost, and the effectiveness of electric field breakage has not been confirmed for thin lines with processing accuracy at the light exposure level. (In our experiment, it was not possible to break well in the range of light exposure.)
２）Ｎａｎｏｔｅｃｈｎｏｌｏｇｙ １３，（２００２）６５９
この論文で紹介されている手法は、ほぼ点の状態で部分的に接続している電極パターンを電子ビーム露光により作製する方法である。この電子ビーム露光用のレジストが残っている電極パターンをリフトオフ段階で特別な溶液で超音波洗浄することにより、電極の金属も部分的に剥離させ、その結果ナノメートル・オーダーのギャップを高い再現性で作製する。しかし、この技術はランコストの高い電子ビーム露光の加工精度を必要とし、光露光での作製は不可能である。
2) Nanotechnology 13, (2002) 659
The technique introduced in this paper is a method of producing an electrode pattern that is partially connected in a substantially point state by electron beam exposure. The electrode pattern on which the resist for electron beam exposure remains is ultrasonically cleaned with a special solution at the lift-off stage, so that the metal of the electrode is also partially removed, resulting in high reproducibility of the nanometer-order gap. To make. However, this technique requires processing accuracy of electron beam exposure with a high run cost and cannot be manufactured by optical exposure.
このように電子ビーム露光を使用せずに間隙幅がナノメートル・オーダーのナノギャップ電極を実現した例はこれまでにない。 There has never been an example of realizing a nanogap electrode having a gap width of the order of nanometers without using electron beam exposure.
本発明は、このような従来技術の問題点を解決するためになされたもので、ランニングコストの高い電子ビーム露光を用いることなく、μｍ程度のパターニング精度の技術を用いて間隙幅がナノメートル・オーダー、特に５ｎｍ以下のナノギャップ電極を製造することができる方法及び該方法により製造されたナノギャップ電極を有する素子を提供することをその課題とする。 The present invention has been made in order to solve such problems of the prior art, and the gap width can be reduced to a nanometer by using a patterning accuracy technique of about μm without using an electron beam exposure with a high running cost. It is an object of the present invention to provide a method capable of producing a nanogap electrode of an order, particularly 5 nm or less, and a device having a nanogap electrode produced by the method.
本発明によれば、上記課題は下記の技術的手段により解決される。
（１）基板上に光露光により所定の水平方向幅のレジストパターンを形成する第１のレジストパターン形成工程と、
基板面に対して導電性材料を斜め蒸着し、電極エッジ角度θ １ （０°＜θ １ ＜９０°）を有する第１番目の電極層を設ける第１の蒸着工程と、
第１のリフトオフ処理工程と、
電極表面をエッチングして電極エッジを不均一化させる不均一化工程と、
再度光露光によりスリットを持つレジストパターンを、前記ギャップをまたいで両側に形成する第２のレジストパターン形成工程と、
前記蒸着方向とは反対の方向から基板面に対して蒸着角度θ ２ （０°＜θ ２ ＜θ １ ＜９０°）で導電性材料を斜め蒸着し、１０ｎｍ以下の幅のギャップが形成されるように第２番目の電極層を設ける第２の蒸着工程と、
第２のリフトオフ処理工程と、
電極間に電流を流し、電極間の短絡部分を電界破断させる電界破断工程と
からなることを特徴とするナノギャップ電極の製造方法。
（２）前記（１）の方法により製造されたナノギャップ電極を用いた素子。
According to the present invention, the above problem is solved by the following technical means.
(1) a first resist pattern forming step of forming a resist pattern having a predetermined horizontal width by light exposure on a substrate;
The conductive material is obliquely deposited to the substrate surface, a first deposition step of providing the first-th electrode layer having the electrode edge angle theta 1 a (0 ° <θ 1 <90 °),
A first lift-off process step;
A non-uniformization step of etching the electrode surface to make the electrode edge non-uniform,
A second resist pattern forming step of forming on both sides a resist pattern having a slit by a light exposure again, across said gap,
The conductive material is obliquely deposited at a deposition angle θ 2 (0 ° <θ 2 <θ 1 <90 ° ) with respect to the substrate surface from a direction opposite to the vapor deposition direction to form a gap having a width of 10 nm or less. A second vapor deposition step of providing a second electrode layer as follows:
A second lift-off process step;
A method for producing a nanogap electrode, comprising: an electric field breaking step in which an electric current is passed between electrodes, and a short-circuit portion between the electrodes is broken in an electric field.
(2) A device using a nanogap electrode manufactured by the method of (1).
本発明によれば、上記手法を用いたので、ランニングコストの高い電子ビーム露光を用いることなく、ナノメートル・オーダー、特に５ｎｍ以下の間隙幅のナノギャップ電極を容易に製造することが可能となる。 According to the present invention, since the above method is used, it is possible to easily manufacture a nanogap electrode having a gap width of nanometer order, particularly 5 nm or less, without using electron beam exposure with a high running cost. .
以下、本発明について詳述する。
本発明者らは、最近、ランニングコストの高い電子ビーム露光を用いずに、分子サイズの微小ギャップを有する電極構造を製造する方法を提案した（特願２００３−４５８６３号明細書）。この方法は、基板上に光露光により所定の水平方向幅のレジストパターンを形成する第１のレジストパターン形成工程と、基板面に対してθ １ （０°＜θ １ ＜９０°）の角度で導電性材料を斜め蒸着し、所定幅のギャップが形成されるように第１番目の電極層を設ける第１の蒸着工程と、第１のリフトオフ処理工程と、再度光露光によりスリットを持つレジストパターンを、記ギャップをまたいで両側に形成する第２のレジストパターン形成工程と、前記θ １ の方向とは反対の方向から基板面に対してθ ２ （０°＜θ ２ ＜θ １ ＜９０°）の角度で導電性材料を斜め蒸着し、１０〜４０ｎｍ幅のギャップが形成されるように第２番目の電極層を設ける第２の蒸着工程と、第２のリフトオフ処理工程とからなることを特徴とするものである。この方法により、１０〜４０ｎｍ程度のギャップを有する電極構造の提供が可能となった。
Hereinafter, the present invention will be described in detail.
The present inventors recently proposed a method of manufacturing an electrode structure having a minute gap of molecular size without using electron beam exposure with a high running cost (Japanese Patent Application No. 2003-45863). This method includes a first resist pattern forming step of forming a resist pattern having a predetermined horizontal width on a substrate by light exposure, and an angle θ 1 (0 ° <θ 1 <90 °) with respect to the substrate surface. A resist pattern having a slit formed by obliquely vapor-depositing a conductive material and providing a first electrode layer so as to form a gap having a predetermined width, a first lift-off process, and light exposure again and a second resist pattern forming step of forming on both sides across the serial gap, the theta 2 (0 ° to the substrate surface from a direction opposite to the theta 1 direction <θ 2 <θ 1 <90 ° ) With a second vapor deposition step in which a conductive material is obliquely vapor-deposited at an angle and a second electrode layer is provided so as to form a gap having a width of 10 to 40 nm, and a second lift-off treatment step. It is a feature. By this method, an electrode structure having a gap of about 10 to 40 nm can be provided.
本発明者らは、ナノ構造の特性を直接利用したデバイスの実現のために、さらなる微小ギャップ、すなわち間隙幅がナノメートル・オーダー、特に５ｎｍ以下のナノギャップ電極を実現すべく、上記提案の技術をさらに検討し鋭意研究を重ねた結果、本発明を完成するに至った。
すなわち、本発明の方法は、
（Ａ）基板上に光露光により所定の水平方向幅のレジストパターンを形成する第１のレジストパターン形成工程、
（Ｂ）基板面に対して導電性材料を斜め蒸着し、電極エッジ角度θ １ （０°＜θ １ ＜９０°）を有する第１番目の電極層を設ける第１の蒸着工程
（Ｃ）第１のリフトオフ処理工程、
（Ｄ）エッチングにより電極表面をエッチングして電極エッジを不均一化させる不均一化工程、
（Ｅ）再度光露光によりスリットを持つレジストパターンを、前記ギャップをまたいで両側に形成する第２のレジストパターン形成工程、
（Ｆ）前記蒸着方向とは反対の方向から基板面に対して蒸着角度θ ２ （０°＜θ ２ ＜θ １ ＜９０°）で導電性材料を斜め蒸着し、１０ｎｍ以下の幅のギャップが形成されるように第２番目の電極層を設ける第２の蒸着工程、
（Ｇ）第２のリフトオフ処理工程、
（Ｈ）電極間に電流を流し、電極間の短絡部分を電界破断させる電界破断工程
の各工程からなる。
In order to realize a device that directly utilizes the characteristics of nanostructures, the present inventors have proposed the above-described technique to realize a further minute gap, that is, a nanogap electrode having a gap width of the order of nanometers, particularly 5 nm or less. As a result of further examination and repeated earnest studies, the present invention has been completed.
That is, the method of the present invention comprises:
(A) a first resist pattern forming step of forming a resist pattern having a predetermined horizontal width by light exposure on a substrate;
(B) A first vapor deposition step in which a conductive material is obliquely vapor-deposited with respect to the substrate surface, and a first electrode layer having an electrode edge angle θ 1 (0 ° <θ 1 <90 °) is provided. 1 lift-off process,
(D) A non-uniformization step of etching the electrode surface by etching to make the electrode edge non-uniform,
(E) a resist pattern having slits again by light exposure, the second resist pattern forming step of forming on both sides across the gap,
(F) Conductive material is obliquely deposited at a deposition angle θ 2 (0 ° <θ 2 <θ 1 <90 ° ) with respect to the substrate surface from a direction opposite to the deposition direction, and a gap having a width of 10 nm or less is formed. A second vapor deposition step of providing a second electrode layer to be formed;
(G) a second lift-off process step,
(H) It consists of each process of the electric field fracture | rupture process which sends an electric current between electrodes and makes the electric field fracture of the short circuit part between electrodes.
以下、各工程に沿って詳述する。
本発明方法では、先ず、基板上に光露光（フォトリソグラフィー）を用いて水平方向幅Ｗを持つレジストパターンを形成する。ここで光露光は従来の方法を使用することができる。基板としては少なくとも表面が絶縁性を有している必要があり、通常、ＳｉＯ２膜で表面を被覆したシリコン基板や、ガラス基板等が使用される。
Hereinafter, it explains in full detail along each process.
In the method of the present invention, first, a resist pattern having a horizontal width W is formed on a substrate by using light exposure (photolithography). Here, a conventional method can be used for light exposure. As the substrate, at least the surface must have insulating properties, and a silicon substrate, a glass substrate, or the like whose surface is covered with a SiO 2 film is usually used.
次に、従来型の蒸着装置を用いて導電性材料を斜め蒸着する。この斜め蒸着は、基板面に形成される電極の電極エッジ角度θ １ が、基板面に対し０°＜θ １ ＜９０°となるように行う。θ １ は、上記条件を満足していればよいが、好ましくは４５〜８０°である。導電性材料としては、一般に電極に使用されている材料であれば適宜のものが使用可能であるが、Ｃｒ／Ａｕ、Ａｌ、Ｃｏ等の金属合金材料の使用が好ましい。この斜め蒸着により、ギャップが形成された状態で、第１番目の電極層が付着形成される。第１番目の電極層の膜厚は２５〜６０ｎｍ程度が好ましい。この斜め蒸着時には、蒸着する導電性材料が充分平行性を持って基板に到着するよう、基板と蒸着源（図示せず）の距離を離す必要があり、通常５００ｍｍ程度離間させることが望ましい。また、蒸着源と試料間の距離を離すことは、斜め蒸着した金属が輻射による加熱で拡散するのを抑制する効果もある。 Next, the conductive material is obliquely deposited using a conventional deposition apparatus. The oblique deposition, the electrode edge angle theta 1 of the electrodes formed on the substrate surface is performed so that against the base plate surface 0 ° <θ 1 <90 ° . θ 1 only needs to satisfy the above condition, but is preferably 45 to 80 °. As the conductive material, any appropriate material can be used as long as it is generally used for electrodes. However, it is preferable to use a metal alloy material such as Cr / Au, Al, or Co. By this oblique deposition, the first electrode layer is deposited and formed with the gap formed. The thickness of the first electrode layer is preferably about 25 to 60 nm. At the time of this oblique vapor deposition, it is necessary to increase the distance between the substrate and the vapor deposition source (not shown) so that the conductive material to be deposited arrives at the substrate with sufficient parallelism. Further, increasing the distance between the vapor deposition source and the sample also has an effect of suppressing diffusion of the obliquely vapor deposited metal due to heating by radiation.
次に、レジストパターンをリフトオフ処理により除去した後、電極エッジの不均一化処理を施す。この処理は本発明のポイントの一つであるので詳述する。
本発明者らが先に提案した電極製造方法は、光露光の加工範囲のみで微小間隙幅のギャップ電極を製造することができるが、この技術により、さらに微小な１０ｎｍ以下の間隙幅のナノギャップを形成した場合、間隙幅に合わせて１段目の電極高さを薄くせねばならず、電極としての耐久性の問題から間隙幅５ｎｍ以下のナノギャップ電極には実用的でない。また、間隙幅１０ｎｍ以下では再現性が５割、５ｎｍでは２割程度になり、安定して５ｎｍ以下のギャップ電極を作製することが困難である。その原因は、間隙形成のためのマスクとなる１回目の蒸着金属電極が部分的に均一ではないため、もしくは蒸着時に金属の回り込みが生じるため、部分的に間隙幅が狭くなり、場合により電極間が架橋され電気的に短絡してしまうからである。また、電極エッジの不均一化を施さない場合に生じる短絡部分には前述した電界破断を適用することができない。本発明者らは、この現象を逆手に捉え、１回目の蒸着金属電極を意図的に不均一なものにすることにより、上記の再現性低下の問題を解決することを確認した。具体的には、１段階目の蒸着を行い、従来法によるリフトオフを行った後、オゾンプラズマアッシャーをかけることにより電極の表面をエッチングし電極エッジに不均一性を出した。この不均一な金属電極は、部分的に電極が薄いところ、電極エッジ角度が浅いところを持ち、部分的に狭い間隙幅を実現することができた。図１にこの不均一性の効果のイメージ図を示す。左側の図は１回目蒸着金属電極が均一な場合で、右図の図は１回目蒸着金属電極が不均一な場合である。まず均一な場合、ギャップサイズＧは一回目蒸着金電極の高さＨ、１回目蒸着金属の電極エッジ角度θ１、２回目蒸着時の蒸着角度θ２の間にＧ＝Ｈ（ｃｏｔａｎθ２−ｃｏｔａｎθ１）の関係があり、均一なギャップ間隔が形成されるが、不均一の場合はＨとθ１がランダムな大きさを持つので、部分的に間隙幅を狭くすることができる。この手法により５ｎｍ以下の間隙を高い確率で達成することが可能になった。
ここで電極の「不均一性」とは、電極エッジの高さ、角度にナノスケールのばらつきが生じていることを意味する。
本発明で、電極の不均一化処理をする方法としては、プラズマアッシャーの他、ＵＶオゾン処理、アルゴンイオン照射、薬品処理等の方法を用いることができる。
Next, after removing the resist pattern by a lift-off process, an electrode edge non-uniformization process is performed. Since this process is one of the points of the present invention, it will be described in detail.
The electrode manufacturing method previously proposed by the present inventors can manufacture a gap electrode having a minute gap width only in the processing range of light exposure. By this technique, a nano gap having a gap width of 10 nm or less can be further reduced. When the electrode is formed, the height of the first electrode must be reduced in accordance with the gap width, and it is not practical for a nanogap electrode having a gap width of 5 nm or less due to the problem of durability as an electrode. Further, when the gap width is 10 nm or less, the reproducibility is 50%, and when the gap is 5 nm, the reproducibility is about 20%, and it is difficult to stably produce a gap electrode of 5 nm or less. The reason for this is that the first deposited metal electrode that serves as a mask for gap formation is not partially uniform, or metal wraparound occurs during deposition, so the gap width is partially narrowed. This is because they are cross-linked and electrically short-circuited. In addition, the above-described electric field rupture cannot be applied to a short-circuit portion that occurs when the electrode edge is not made nonuniform. The present inventors have confirmed that this problem can be solved by taking this phenomenon in reverse and intentionally making the first vapor-deposited metal electrode non-uniform. Specifically, after the first stage of vapor deposition was performed and lift-off was performed by a conventional method, the surface of the electrode was etched by applying an ozone plasma asher to give nonuniformity to the electrode edge. This non-uniform metal electrode has a portion where the electrode is partially thin and a portion where the electrode edge angle is shallow, and a partially narrow gap width can be realized. FIG. 1 shows an image of this non-uniformity effect. The figure on the left shows the case where the first vapor deposition metal electrode is uniform, and the figure on the right shows the case where the first vapor deposition metal electrode is non-uniform. When first uniform, the gap size G one time deposited gold electrode height H, 1 round electrode edge angle of evaporated metal theta 1, during the deposition angle theta 2 at the time of the second deposition G = H (cotanθ 2 -cotanθ 1) There is a relationship, but a uniform gap spacing is formed, in the case of non-uniform since H and theta 1 has a random size, it is possible to narrow the partially gap width. This technique makes it possible to achieve a gap of 5 nm or less with a high probability.
Here, “non-uniformity” of the electrode means that nanoscale variation occurs in the height and angle of the electrode edge.
In the present invention, as a method for performing electrode non-uniformization treatment, methods such as UV ozone treatment, argon ion irradiation, chemical treatment, etc. can be used in addition to plasma asher.
次に、ギャップをまたぐように両側の電極上に、再度光露光によりスリットを持つレジストパターンを形成する。レジストパターンの形成方法は上記と同様の方法であってもよく、必要により条件を変更しても構わない。スリットのレジストパターンの高さ（垂直方向厚み）は１μｍ以下が適当であり、スリット幅はマスクの位置あわせ精度等を考慮して決定する（１μｍ程度）。 Next, a resist pattern having slits is formed again on the electrodes on both sides so as to cross the gap by light exposure. The method of forming the resist pattern may be the same method as described above, and the conditions may be changed as necessary. The height (vertical thickness) of the resist pattern of the slit is suitably 1 μm or less, and the slit width is determined in consideration of the alignment accuracy of the mask (about 1 μm).
次に、に示すように、２度目の導電性材料の斜め蒸着を行う。この斜め蒸着は基板の表面に対し前記蒸着方向とは反対の方向から蒸着角度θ ２ （０°＜θ ２ ＜θ １ ＜９０°）で行う。θ ２ は、上記条件を満足していればよいが、好ましくは１５〜７５°である。導電性材料としては、上記と同様なものを使用することができる。この斜め蒸着により、第２番目の電極層が付着形成される。ギャップＧの幅は１０ｎｍ以下とする。 Next, a second oblique deposition of the conductive material is performed as shown in FIG. This oblique vapor deposition is performed at a vapor deposition angle θ 2 (0 ° <θ 2 <θ 1 <90 ° ) from the direction opposite to the vapor deposition direction with respect to the surface of the substrate. θ 2 only needs to satisfy the above condition, but is preferably 15 to 75 °. As the conductive material, the same materials as described above can be used. By this oblique vapor deposition, a second electrode layer is deposited and formed. The width of the gap G is 10 nm or less.
次に、再度従来法によるリフトオフ処理を行った後、電極間に電流を流し、電極間の短絡部分を電界破断させる電界破断処理を施す。
上記の電極エッジの不均一化処理に伴い電極間が架橋してしまい電気的に短絡する部分が多くなるが、前述した電界破断法（Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．７５（１９９９）３０１）を利用して、電極間に電流を流すことにより、この短絡部分を選択的に除去することが可能となる。図２に電界破断時の配線図を示す。図のように短絡している電極間に可変抵抗Ｒｔと固定抵抗Ｒｃをはさみ、電圧を印加した。破断に必要な電流量は数ｍＡ程度が適当で、電流量は可変抵抗により調節した。また、一瞬でも目的量以上の電流が流れると電界破断が短絡部分だけではなく、その周辺も大きく巻き込んで破断される。これを避けるため、固定抵抗Ｒｃを導入し、可変抵抗値が０Ωになっても電流量が目的量を超えないようにした。この抵抗の組み合わせにより、短絡部分の局所的な破断が実現される。
Next, after performing the lift-off process by the conventional method again, the electric field rupture process which makes an electric current flow between electrodes and ruptures the short circuit part between electrodes is performed.
With the above electrode edge non-uniformization treatment, the electrodes are cross-linked and there are many portions that are electrically short-circuited. However, the electric field breaking method (Appl. Phys. Lett. 75 (1999) 301) described above is used. Thus, this short-circuited portion can be selectively removed by passing a current between the electrodes. FIG. 2 shows a wiring diagram when the electric field is broken. As shown in the figure, a variable resistor Rt and a fixed resistor Rc were sandwiched between shorted electrodes, and a voltage was applied. The amount of current required for the breakage is suitably about several mA, and the amount of current is adjusted by a variable resistance. In addition, when a current exceeding the target amount flows even for a moment, the electric field breaks not only at the short-circuited portion but also at the periphery thereof and breaks. In order to avoid this, a fixed resistor Rc is introduced so that the current amount does not exceed the target amount even when the variable resistance value becomes 0Ω. By this combination of resistances, local breakage of the short-circuit portion is realized.
以上の各工程を経て所望の１０ｎｍ以下の間隙幅のナノギャップ電極を再現性よく製造することが可能となる。 Through the above steps, a nanogap electrode having a desired gap width of 10 nm or less can be manufactured with good reproducibility.
本発明によれば、上記で作製したナノギャップ電極を利用したナノ構造の素子（デバイス）の提供が可能となる。具体例として、作製した５ｎｍ以下のナノギャップ電極（最小電極幅２ｎｍ）を用いて、電極間に鎖長２．４ｎｍの合成分子（ｏｌｉｇｏ （ｐａｒａ−ｐｈｅｎｙｌｅｎｅｖｉｎｙｌｅｎｅ ｍｅｔｈｙｌ ｄｉｔｈｉｏｌ）を架橋させた素子を作り、直接電気伝導測定に成功した。その結果を図３に示す。電子ビーム露光を用いずに作製した固定化平面ナノギャップ電極で、合成した単分子の直接電気伝導測定を実現している例はこれまでなかったが、本発明によりその実現が可能となった。 According to the present invention, it is possible to provide a nanostructured element (device) using the nanogap electrode produced as described above. As a specific example, using the produced nanogap electrode of 5 nm or less (minimum electrode width 2 nm), a device in which a synthetic molecule (oligo (para-phenylene vinyl dithiol)) having a chain length of 2.4 nm is crosslinked between the electrodes, The results of the direct electrical conductivity measurement are shown in Fig. 3. An example of realizing the direct electrical conductivity measurement of a synthesized single molecule with an immobilized planar nanogap electrode fabricated without using electron beam exposure is shown in this figure. However, the present invention has made it possible.
次に、本発明の実施例を述べるが、本発明はこれに限定されるものではない。以下、本発明を実施例によりさらに詳細に説明する。
厚さ４００ｎｍの酸化シリコン層で被覆されたシリコン基板上に、通常の光露光手法で第１レジストパターンを作製した。第１レジストパターンの高さ（垂直方向の厚み）は
１μｍ、水平方向の幅は２μｍとした。次に、θ １ ´＝７５°の斜め蒸着によりＣｒ／Ａｕ（Ｃｒ膜は接着層で２ｎｍ厚）膜を高さＨ＝２５ｎｍに製膜し、電極エッジ角度θ １ がほぼ７５°の第１電極層とした。ギャップ幅はアッシングしなければ７ｎｍ程度となるものであった。
次に、パターンのリフトオフ処理を行った後、電極面にオゾンプラズマアッシャー処理を施した。オゾンプラズマアッシャーの条件は、ＲＦ ｐｏｗｅｒ ３００Ｗ、酸素流量 １００ｍｌ／ｍｉｎ、アッシング時間を６０秒に設定して行った。また、アッシング後金表面の酸化層を取り除くためエタノールで処理した。
次に、通常の光露光手法でスリット幅２μｍの第２レジストパターンを形成した後、蒸着角度θ ２ ＝６０°の斜め蒸着によりＣｒ（２ｎｍ）＋Ａｕ膜を２０ｎｍ厚に形成し、第２電極層とした。この条件で作製した電極は短絡しており、１００Ω以下の抵抗を示した。
リフトオフ処理後、電界破断処理を行った。その条件は、電極間に１Ｖの電位差を印加し、抵抗Ｒｃ＝１００Ω、可変抵抗Ｒｔを１００ｋΩから０Ωまでゆっくりと下げて電流量を徐々に増加させた。その結果、約４ｍＡ程度の電流が流れ出した時に短絡した電極が破断された。以上のようにしてナノギャップ電極を作製した。
Next, examples of the present invention will be described, but the present invention is not limited thereto. Hereinafter, the present invention will be described in more detail with reference to examples.
A first resist pattern was formed on a silicon substrate covered with a 400 nm thick silicon oxide layer by a normal light exposure technique. The height (vertical thickness) of the first resist pattern was 1 μm, and the horizontal width was 2 μm. Next, a Cr / Au (Cr film is an adhesive layer with a thickness of 2 nm) film is formed to a height H = 25 nm by oblique vapor deposition with θ 1 ′ = 75 °, and the first electrode edge angle θ 1 is approximately 75 ° . An electrode layer was obtained. The gap width was about 7 nm without ashing.
Next, after performing a pattern lift-off process, the electrode surface was subjected to an ozone plasma ashing process. The conditions for the ozone plasma asher were RF power 300 W, oxygen flow rate 100 ml / min, and ashing time 60 seconds. Further, after ashing, it was treated with ethanol to remove the oxide layer on the gold surface.
Next, after forming a second resist pattern having a slit width of 2 μm by a normal light exposure method, a Cr (2 nm) + Au film is formed to a thickness of 20 nm by oblique vapor deposition with a vapor deposition angle θ 2 = 60 °, and the second electrode layer It was. The electrode produced under these conditions was short-circuited and exhibited a resistance of 100Ω or less.
After the lift-off process, an electric field breaking process was performed. The condition was that a potential difference of 1 V was applied between the electrodes, the resistance Rc = 100Ω, and the variable resistance Rt was slowly lowered from 100 kΩ to 0Ω to gradually increase the amount of current. As a result, the shorted electrode was broken when a current of about 4 mA started to flow. A nanogap electrode was produced as described above.
図４にこの条件で作製したナノギャップ電極の電子顕微鏡像を示す。（ａ）と（ｃ）はそれぞれほぼ同じ条件でプラズマアッシャーの工程を含むもの（ａ）、含まないもの（ｃ）を示している。また（ｂ）は（ａ）の四角い枠部分を拡大したものを示している。（ｃ）は均一な５〜７ｎｍ程度の間隙幅を持っているのに対し、（ａ）、（ｂ）は不均一な間隙幅を示す。その間隙幅は２〜１０ｎｍと部分的に５ｎｍ以下の間隙を実現している。これらの電極の抵抗値は１０ＴΩ以上の抵抗値を示しリークが殆どない。またこの手法による５ｎｍ以下のナノギャップ電極の再現性は８０％を超え、非常に再現性の高い手法と言える。 FIG. 4 shows an electron microscope image of the nanogap electrode produced under these conditions. (A) and (c) respectively show (a) that does not include the plasma asher process under substantially the same conditions, and (c) that does not. (B) shows an enlarged view of the rectangular frame part of (a). (C) has a uniform gap width of about 5 to 7 nm, while (a) and (b) show non-uniform gap widths. The gap width is 2 to 10 nm, and a gap of 5 nm or less is partially realized. The resistance values of these electrodes are 10 TΩ or more and there is almost no leakage. The reproducibility of nanogap electrodes of 5 nm or less by this method exceeds 80%, which can be said to be a very reproducible method.
本発明の方法は、既存プロセス技術で唯一実現可能な１０ｎｍ以下のサイズの固定平面型ナノギャップ電極作製手法である。このサイズのナノ構造の物性を引き出す素子が完成することにより、その量産化に対して非常に有望な基盤技術になる可能性がある。 The method of the present invention is a method for producing a fixed planar nanogap electrode having a size of 10 nm or less that can be realized only by existing process technology. Completion of a device that draws out the physical properties of this size of nanostructure may become a very promising fundamental technology for mass production.
Ｈ：１回目蒸着金属電極の膜厚
Ｇ：ナノギャップのサイズ
θ１：１回目蒸着金属電極の電極エッジ角度（オゾンプラズマアッシャー無処理時はほぼ１回目の斜め蒸着の角度θ １ ´に相当）
θ２：２回目斜め蒸着時の蒸着角度
Ｖ：電極間印加電圧
Ｉ：電流計
Ｒｔ：可変抵抗の抵抗値
Ｒｃ：通常抵抗の抵抗値
H: Film thickness of the first vapor-deposited metal electrode G: Nanogap size θ 1 : Electrode edge angle of the first vapor-deposited metal electrode (equivalent to the angle θ 1 ′ of the first oblique vapor deposition when no ozone plasma asher is treated)
θ 2 : Deposition angle during the second oblique deposition V: Applied voltage between electrodes I: Ammeter Rt: Resistance value of variable resistance Rc: Resistance value of normal resistance
Claims (2)
基板面に対して導電性材料を斜め蒸着し、電極エッジ角度θ １ （０°＜θ １ ＜９０°）を有する第１番目の電極層を設ける第１の蒸着工程と、
第１のリフトオフ処理工程と、
電極表面をエッチングして電極エッジを不均一化させる不均一化工程と、
再度光露光によりスリットを持つレジストパターンを、前記ギャップをまたいで両側に形成する第２のレジストパターン形成工程と、
前記蒸着方向とは反対の方向から基板面に対して蒸着角度θ ２ （０°＜θ ２ ＜θ １ ＜９０°）で導電性材料を斜め蒸着し、１０ｎｍ以下の幅のギャップが形成されるように第２番目の電極層を設ける第２の蒸着工程と、
第２のリフトオフ処理工程と、
電極間に電流を流し、電極間の短絡部分を電界破断させる電界破断工程と
からなることを特徴とするナノギャップ電極の製造方法。 A first resist pattern forming step of forming a resist pattern having a predetermined horizontal width by light exposure on a substrate;
The conductive material is obliquely deposited to the substrate surface, a first deposition step of providing the first-th electrode layer having the electrode edge angle theta 1 a (0 ° <θ 1 <90 °),
A first lift-off process step;
A non-uniformization step of etching the electrode surface to make the electrode edge non-uniform,
A second resist pattern forming step of forming on both sides a resist pattern having a slit by a light exposure again, across said gap,
The conductive material is obliquely deposited at a deposition angle θ 2 (0 ° <θ 2 <θ 1 <90 ° ) with respect to the substrate surface from a direction opposite to the vapor deposition direction to form a gap having a width of 10 nm or less. A second vapor deposition step of providing a second electrode layer as follows:
A second lift-off process step;
A method for producing a nanogap electrode, comprising: an electric field breaking step in which an electric current is passed between electrodes, and a short-circuit portion between the electrodes is broken in an electric field.
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| KR100849384B1 (en) * | 2005-10-21 | 2008-07-31 | 한국생명공학연구원 | A method for fabricating nanogap and nanogap sensor |
| KR100762258B1 (en) * | 2006-05-02 | 2007-10-01 | 한국표준과학연구원 | Process for preparing nanogap electrode and nanogap device using the same |
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