JP3798568B2 - Semiconductor element - Google Patents

Semiconductor element Download PDF

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Publication number
JP3798568B2
JP3798568B2 JP04039999A JP4039999A JP3798568B2 JP 3798568 B2 JP3798568 B2 JP 3798568B2 JP 04039999 A JP04039999 A JP 04039999A JP 4039999 A JP4039999 A JP 4039999A JP 3798568 B2 JP3798568 B2 JP 3798568B2
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Prior art keywords
bump
bumps
semiconductor element
internal wiring
wiring
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JP04039999A
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JP2000243771A (en
Inventor
信久 熊本
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP04039999A priority Critical patent/JP3798568B2/en
Priority to US09/504,874 priority patent/US6707159B1/en
Publication of JP2000243771A publication Critical patent/JP2000243771A/en
Priority to US10/767,439 priority patent/US7329562B2/en
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Publication of JP3798568B2 publication Critical patent/JP3798568B2/en
Priority to US12/068,596 priority patent/US20080138976A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子に関し、特に半導体素子表面の配線に関するものである。
【０００２】
【従来の技術】
半導体素子の素子形成面に電極を設けて、キャリヤテープなどの配線基板の電極との間で直接接続し、この配線基板の電極を、プリント基板やセラミック基板に接続するワイヤレスボンディング技術が通常行われている。
また、半導体素子の一層の集積化を図るため、複数の半導体素子を２層に重ね合わせる、チップオンチップ構造の半導体素子が注目されている。
【０００３】
前記いずれの技術の場合も、配線基板の電極、又は半導体素子の素子形成面の電極の上に、「バンプ」という突起電極を設ける必要がある。
【０００４】
【発明が解決しようとする課題】
一方、半導体素子の素子形成面には、素子の機能を実現するための多数の配線がなされており、素子設計をするときには、これらの配線が錯綜しないように設計をしなければならない。
しかし、限られた素子形成面に配線を縦横に巡らせるのには限度があり、このため素子の小型化、集積化に制約を受けるという不都合を来していた。
【０００５】
そこで、本発明者は、前記バンプを素子の配線に利用するという発想に至った。本発明は、素子上の配線の自由度を増し、小型化、集積化を可能にする半導体素子を実現することを目的とする。
【０００６】
【課題を解決するための手段及び発明の効果】
(1)本発明の半導体素子は、半導体素子形成領域に外部接続用バンプを配置しているとともに、素子内配線を行うために、外部接続用バンプの高さよりも低い高さの内部配線用バンプを配置し、当該内部配線用バンプを外部接続用バンプに接続しているものである（請求項１）。
【０００７】
この構成によれば、素子内配線の一部を、内部配線用バンプによる配線で行えるので、素子内配線が簡単になる。また、バンプの低抵抗、高熱伝導率という特性を利用すれば、比較的大きな電流が流せるので、内部配線用バンプを接地配線や電源配線に好適に利用することができる。
また、前記内部配線用バンプの高さは、外部接続用バンプの高さよりも低いので、２つの半導体素子を貼り合わせてチップオンチップ構造とするときなどに、内部配線用バンプ同士が接触することはない。
【０００８】
前記内部配線用バンプは、外部接続用バンプに接続されているので、外部接続用バンプ間の配線が行える。
(2)本発明の半導体素子は、半導体基板の半導体素子形成領域外に周囲バンプを配置しているとともに、素子内配線を行うために、周囲バンプの高さよりも低い高さの内部配線用バンプを配置し、前記内部配線用バンプを周囲バンプに接続しているものである（請求項２）。
【０００９】
この構成であれば、周囲バンプを、接地と同電位に接続すれば、内部配線用バンプを簡単に接地することができる。周囲バンプを、電源と同電位に接続すれば、内部配線用バンプに簡単に電源を供給することができる。
また、前記内部配線用バンプの高さは、周囲バンプの高さよりも低いので、２つの半導体素子を貼り合わせてチップオンチップ構造とするときなどに、内部配線用バンプ同士が接触することを避けることができる。
【００１０】
【発明の実施の形態】
以下、本発明の実施の形態を、添付図面を参照しながら詳細に説明する。本発明の実施の形態では、半導体の種類として、Ｓｉを使用することを前提として説明するが、他にＧａＡｓ、Ｇｅなどの半導体を使用してもよい。
本実施形態に係る半導体素子１１は、図１に示すように、半導体素子１１の上面に、外部接続用バンプ８，９が形成されているとともに、内部配線用バンプ６が形成されている。
【００１１】
この内部配線用バンプ６の高さは、外部接続用バンプ８，９の高さよりも低くなっている。このため、図２に示すように半導体素子１１を、他の半導体素子１２と、いわゆるフェイスツーフェイスの形で２層構造にする場合、又は半導体素子１１をＴＡＢ(Tape Automated Bonding)のフィルムキャリアのインナーリード側に接続する場合に、内部配線用バンプ６同士のくっつきをなくすための、一定のクリアランスＣを確保することができる。
【００１２】
図３は、半導体基板１にバンプ配線を形成する工程を説明するための断面図である。
図３(a)に示すように、半導体基板１上には、ＳｉＯ2膜２を介して所定の部位にＡｌ電極３ａ，３ｂ，３ｃ，３ｄが形成されている。ここでは、電極３ａ、電極３ｃは外部接続用バンプを形成する電極、電極３ｂと電極３ｃは内部配線用バンプにより接続される電極とする。電極３ｄはバンプと接続しない電極である。電極３ｃは内部配線用バンプによる接続と外部接続用バンプを形成する電極を兼ねる。電極３ａ，３ｂ，３ｃ以外の部分はＳｉＮ，ＳｉＯＮ，ＳｉＯ2，ＰＳＧ等のパッシベーション膜４に覆われている。
【００１３】
なお、バンプと接続しない電極３ｄの上は、パッシベーション膜４を除去する必要がないことはもちろんである。したがって、電極３ｄが半導体基板１上で内部配線用バンプとクロスしても、絶縁は確保される。
この上に、Ａｌ電極とバンプとの密着性をよくするためのＴｉＷ合金層、及び給電のためのＡｕ，Ｐｔなどの層を積層したシード層（図示せず）をスパッタなどの方法で蒸着する。
【００１４】
次に、フォトレジスト５を塗布し、内部配線用バンプのメッキのための孔あけを配線したい部位に行う（図３(b)）。
そして電解メッキ法にてバンプ用金属をメッキする（図３(c)）。このバンプ用金属として、Ａｕ，Ｐｄ，Ｐｔ，Ａｇ，Ｉｒ（イリジウム）等をあげることができる。形成された内部配線用バンプを番号６で示す。なお、電解メッキ法に代えて、化学反応による還元作用を利用した金属のメッキ成膜方法である無電解メッキ法を採用してもよい。この内部配線用バンプ６の高さは、例えば１μｍである。
【００１５】
次に、フォトレジスト５を除去し表面のシード層を除去して、フォトレジスト７を塗布し、外部接続用バンプのための孔あけを、電極３ａ、電極３ｃの部位に行う（図３(d)）。
そして、シード層（図示せず）を蒸着し、バンプ用金属をメッキし、フォトレジスト７を除去し表面のシード層を除去して、アニール処理を行うことにより、電極３ａ、電極３ｃに外部接続用バンプ８，９がそれぞれ形成された半導体素子を得る（図３(e)）。この外部接続用バンプ８，９の高さは、例えば２０μｍである。
【００１６】
図４は、本発明の他の実施形態を示す斜視図である。半導体素子１１の上面に、外部接続用バンプ８，９が形成されているとともに、半導体素子１１の周囲に接地用バンプ１０ａ又は電源用バンプ１０ｂ（総称するときは「周囲バンプ１０」という）が形成され、これらの間を結ぶ内部配線用バンプ６が形成されている。
【００１７】
この周囲バンプ１０は、半導体素子１１の、抵抗の低い接地線として利用することにより、他の外部接続用バンプを簡単に接地することができる。また、抵抗の低い電源線として利用することにより、他の外部接続用バンプを簡単に電源につなぐことができる。また、図４に示したように、周囲バンプ１０の途中に切れ目Ｄを作ることにより、一方の周囲バンプ１３ａを接地に、他方の周囲バンプ１３ｂを電源につなぐことができる。
【００１８】
図５は、周囲バンプ１０付きの半導体素子１１を、いわゆるチップオンチップの形で２層構造にする場合の断面図である。周囲バンプ１０が接合することにより、完全なシールド構造ができるので、静電誘導に強い半導体素子とすることができる。また、実装時もしくは実装後、半導体素子にかかる応力を、周囲バンプ１０が緩和する作用もある。
【００１９】
この図５の場合、内部配線用バンプ６の高さは、外部接続用バンプ９、周囲バンプ１０の高さよりも低くなっているので、半導体素子１１を、他の半導体素子１２と、いわゆるチップオンチップの形で２層構造にする場合などに、内部配線用バンプ６同士のくっつきをなくすための、一定のクリアランスＣを確保することができる。
【００２０】
図６は、バンプ配線を形成する工程を説明するための断面図である。この実施形態では、半導体基板１の素子形成領域Ａの中の外部接続用バンプと、素子形成領域の外（例えばスクライブ線の領域Ｂ）に設けた周囲バンプとの間を内部配線用バンプで接続することを想定している。
図６(a)に示すように、半導体基板１の素子形成領域Ａ上には、ＳｉＯ2膜２を介して所定の部位にＡｌ電極３が形成されている。Ａｌ電極３以外の部分はパッシベーション膜４に覆われている。また、スクライブ線領域Ｂは、オーミック接触又は絶縁を確保するため、所定極性の不純物１３を高濃度に注入しておく。不純物の極性は、オーミック接触させる場合は、基板と同極性、絶縁させる場合は基板と異極性とする。
【００２１】
この素子形成領域Ａ及びスクライブ線領域Ｂに、Ａｌ電極とバンプとの密着性をよくするためのＴｉＷ合金層、給電のためのＡｕ，Ｐｔなどの層を積層したシード層（図示せず）をスパッタなどの方法で蒸着しておく。
次に、フォトレジスト５を塗布し、内部配線用バンプのメッキのための孔あけを素子形成領域Ａ及びスクライブ線領域Ｂにまたがって行う（図６(b)）。
【００２２】
そして電解メッキ法又は無電解メッキ法にてバンプ用金属６を薄くメッキする（図６(c)）。このバンプ用金属として、Ａｕ，Ｐｄ，Ｐｔ，Ａｇ，Ｉｒ（イリジウム）等をあげることができる。
次に、フォトレジスト５を除去し表面のシード層も除去して、フォトレジスト７を塗布し、外部接続用バンプ９，１０のための孔あけを、電極３及びスクライブ線の部位に行う（図６(d)）。
【００２３】
そして、シード層（図示せず）を蒸着し、バンプ用金属を厚くメッキし、フォトレジスト７を除去し表面のシード層を除去して、アニール処理を行うことにより、電極３に外部接続用バンプ９が形成され、スクライブ線の領域に周囲バンプ１０が形成された半導体素子を得る（図６(e)）。最後に、スクライブ線領域Ｂの切削部をカッター１５で切り出す。
【図面の簡単な説明】
【図１】発明の実施の形態に係る半導体素子の要部斜視図である。
【図２】半導体素子１１を、他の半導体素子１２と、いわゆるチップオンチップの形で２層構造にした場合の断面図である。
【図３】半導体基板１にバンプ配線を形成する工程を説明するための断面図である。
【図４】発明の他の実施の形態に係る半導体素子の要部斜視図である。
【図５】半導体素子１１を、他の半導体素子１２と、いわゆるチップオンチップの形で２層構造にした場合の断面図である。
【図６】バンプ配線を形成する工程を説明するための断面図である。
【符号の説明】
１ 半導体基板
２ ＳｉＯ2膜
３ａ〜３ｄ Ａｌ電極
４ パッシベーション膜
５，７ フォトレジスト
６ 内部配線用バンプ
８，９ 外部接続用バンプ
１０ 周囲バンプ
１１，１２ 半導体素子
１３ 不純物層
１５ カッター
Ａ 素子形成領域
Ｂ スクライブ線領域
Ｃ クリアランス
Ｄ 周囲バンプ途中の切れ目[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element, and more particularly to wiring on the surface of a semiconductor element.
[0002]
[Prior art]
Generally, a wireless bonding technique is used in which an electrode is provided on the element formation surface of a semiconductor element and is directly connected to an electrode of a wiring board such as a carrier tape, and the electrode of the wiring board is connected to a printed board or a ceramic board. ing.
Further, in order to further integrate semiconductor elements, a semiconductor element having a chip-on-chip structure in which a plurality of semiconductor elements are stacked in two layers has been attracting attention.
[0003]
In any of the above techniques, it is necessary to provide a bump electrode called “bump” on the electrode of the wiring board or the electrode on the element formation surface of the semiconductor element.
[0004]
[Problems to be solved by the invention]
On the other hand, a large number of wirings for realizing the function of the element are formed on the element forming surface of the semiconductor element, and when designing the element, the wiring must be designed so as not to be complicated.
However, there is a limit in routing the wiring vertically and horizontally on a limited element formation surface, which causes the inconvenience of being restricted by downsizing and integration of elements.
[0005]
Therefore, the present inventor has come up with the idea of using the bumps for element wiring. An object of the present invention is to realize a semiconductor element that increases the degree of freedom of wiring on the element and enables miniaturization and integration.
[0006]
[Means for Solving the Problems and Effects of the Invention]
(1) In the semiconductor element of the present invention, external connection bumps are disposed in the semiconductor element formation region, and internal wiring bumps having a height lower than the height of the external connection bumps are used for wiring in the element. And the internal wiring bumps are connected to the external connection bumps (Claim 1).
[0007]
According to this configuration, part of the intra-element wiring can be performed by wiring using the internal wiring bumps, so that the intra-element wiring is simplified. Moreover, if the characteristics of the bumps such as low resistance and high thermal conductivity are used, a relatively large current can be flowed, so that the internal wiring bumps can be suitably used for ground wiring and power supply wiring.
Also, since the height of the internal wiring bump is lower than the height of the external connection bump, when the two semiconductor elements are bonded to form a chip-on-chip structure, the internal wiring bumps are in contact with each other. There is no.
[0008]
Since the internal wiring bumps are connected to the external connection bumps, wiring between the external connection bumps can be performed.
(2) In the semiconductor element of the present invention, the peripheral bump is disposed outside the semiconductor element formation region of the semiconductor substrate, and the internal wiring bump having a height lower than the height of the peripheral bump is used for wiring in the element. And the internal wiring bumps are connected to the surrounding bumps (claim 2).
[0009]
With this configuration, the internal wiring bump can be easily grounded by connecting the peripheral bump to the same potential as the ground. If the peripheral bumps are connected to the same potential as the power supply, the power can be easily supplied to the internal wiring bumps.
In addition, since the height of the internal wiring bump is lower than the height of the surrounding bump, when the two semiconductor elements are bonded to form a chip-on-chip structure, the internal wiring bumps are prevented from contacting each other. be able to.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiment of the present invention will be described on the assumption that Si is used as the type of semiconductor, but other semiconductors such as GaAs and Ge may be used.
As shown in FIG. 1, the semiconductor element 11 according to this embodiment has external connection bumps 8 and 9 formed on the upper surface of the semiconductor element 11, and internal wiring bumps 6.
[0011]
The height of the internal wiring bump 6 is lower than the height of the external connection bumps 8 and 9. For this reason, as shown in FIG. 2, when the semiconductor element 11 has a two-layer structure in the form of a so-called face-to-face with another semiconductor element 12, or the semiconductor element 11 is a TAB (Tape Automated Bonding) film carrier. When connecting to the inner lead side, it is possible to secure a certain clearance C for eliminating the sticking between the internal wiring bumps 6.
[0012]
FIG. 3 is a cross-sectional view for explaining a process of forming bump wiring on the semiconductor substrate 1.
As shown in FIG. 3 (a), Al electrodes 3a, 3b, 3c and 3d are formed on the semiconductor substrate 1 at predetermined sites with the SiO 2 film 2 interposed therebetween. Here, the electrodes 3a and 3c are electrodes that form external connection bumps, and the electrodes 3b and 3c are electrodes that are connected by internal wiring bumps. The electrode 3d is an electrode that is not connected to the bump. The electrode 3c also serves as an electrode for forming a connection by an internal wiring bump and an external connection bump. Portions other than the electrodes 3a, 3b and 3c are covered with a passivation film 4 such as SiN, SiON, SiO 2 or PSG.
[0013]
Of course, it is not necessary to remove the passivation film 4 on the electrode 3d not connected to the bump. Therefore, even if the electrode 3d crosses the internal wiring bump on the semiconductor substrate 1, insulation is ensured.
On top of this, a TiW alloy layer for improving the adhesion between the Al electrode and the bump, and a seed layer (not shown) in which a layer of Au, Pt or the like for power feeding is laminated is deposited by a method such as sputtering. .
[0014]
Next, a photoresist 5 is applied, and a hole for plating of the internal wiring bump is formed in a portion to be wired (FIG. 3B).
Then, bump metal is plated by electrolytic plating (FIG. 3C). Examples of the bump metal include Au, Pd, Pt, Ag, Ir (iridium), and the like. The formed internal wiring bump is denoted by reference numeral 6. Instead of the electrolytic plating method, an electroless plating method that is a metal plating film formation method using a reducing action by a chemical reaction may be employed. The height of the internal wiring bump 6 is, for example, 1 μm.
[0015]
Next, the photoresist 5 is removed, the seed layer on the surface is removed, the photoresist 7 is applied, and holes for the external connection bumps are made in the portions of the electrodes 3a and 3c (FIG. 3 (d)). )).
Then, a seed layer (not shown) is deposited, a bump metal is plated, the photoresist 7 is removed, the seed layer on the surface is removed, and an annealing process is performed, so that the electrodes 3a and 3c are externally connected. A semiconductor element on which the bumps 8 and 9 are formed is obtained (FIG. 3 (e)). The height of the external connection bumps 8 and 9 is, for example, 20 μm.
[0016]
FIG. 4 is a perspective view showing another embodiment of the present invention. External connection bumps 8 and 9 are formed on the upper surface of the semiconductor element 11, and a grounding bump 10 a or a power supply bump 10 b (generally called “surrounding bump 10”) is formed around the semiconductor element 11. Then, an internal wiring bump 6 is formed to connect them.
[0017]
By using the peripheral bump 10 as a ground line having a low resistance of the semiconductor element 11, other bumps for external connection can be easily grounded. Further, by using it as a power supply line having a low resistance, other external connection bumps can be easily connected to the power supply. Also, as shown in FIG. 4, by making a cut D in the middle of the peripheral bump 10, it is possible to connect one peripheral bump 13a to the ground and the other peripheral bump 13b to the power source.
[0018]
FIG. 5 is a cross-sectional view in the case where the semiconductor element 11 with the peripheral bumps 10 has a two-layer structure in the form of a so-called chip-on-chip. By joining the peripheral bumps 10, a complete shield structure can be formed, so that a semiconductor element resistant to electrostatic induction can be obtained. Further, the peripheral bump 10 has an action of relaxing the stress applied to the semiconductor element during or after mounting.
[0019]
In the case of FIG. 5, the height of the internal wiring bump 6 is lower than the height of the external connection bump 9 and the peripheral bump 10, so that the semiconductor element 11 and other semiconductor elements 12 are so-called chip-on. In the case of a two-layer structure in the form of a chip or the like, a certain clearance C can be secured to eliminate the sticking between the internal wiring bumps 6.
[0020]
FIG. 6 is a cross-sectional view for explaining a process of forming bump wiring. In this embodiment, an internal wiring bump is connected between an external connection bump in the element formation area A of the semiconductor substrate 1 and a peripheral bump provided outside the element formation area (for example, the scribe line area B). Assumes that
As shown in FIG. 6A, an Al electrode 3 is formed at a predetermined site on the element formation region A of the semiconductor substrate 1 via the SiO 2 film 2. Portions other than the Al electrode 3 are covered with a passivation film 4. In the scribe line region B, an impurity 13 having a predetermined polarity is implanted at a high concentration in order to ensure ohmic contact or insulation. The polarity of the impurity is the same polarity as that of the substrate in the case of ohmic contact, and different from that of the substrate in the case of insulation.
[0021]
In the element formation region A and the scribe line region B, a seed layer (not shown) in which a TiW alloy layer for improving the adhesion between the Al electrode and the bump and a layer of Au, Pt or the like for feeding is laminated. Evaporation is performed by a method such as sputtering.
Next, a photoresist 5 is applied, and a hole for plating the internal wiring bump is formed across the element formation region A and the scribe line region B (FIG. 6B).
[0022]
Then, the bump metal 6 is thinly plated by an electrolytic plating method or an electroless plating method (FIG. 6C). Examples of the bump metal include Au, Pd, Pt, Ag, Ir (iridium), and the like.
Next, the photoresist 5 is removed, the seed layer on the surface is also removed, the photoresist 7 is applied, and the holes for the external connection bumps 9 and 10 are formed in the portions of the electrode 3 and the scribe line (see FIG. 6 (d)).
[0023]
Then, a seed layer (not shown) is vapor-deposited, the bump metal is thickly plated, the photoresist 7 is removed, the surface seed layer is removed, and an annealing process is performed, whereby an external connection bump is formed on the electrode 3. 9 is formed, and a semiconductor element having a peripheral bump 10 formed in the region of the scribe line is obtained (FIG. 6E). Finally, the cutting portion of the scribe line region B is cut out by the cutter 15.
[Brief description of the drawings]
FIG. 1 is a perspective view of a main part of a semiconductor device according to an embodiment of the invention.
FIG. 2 is a cross-sectional view in the case where a semiconductor element 11 has a two-layer structure in the form of a so-called chip-on-chip with another semiconductor element 12;
FIG. 3 is a cross-sectional view for explaining a step of forming a bump wiring on the semiconductor substrate 1;
FIG. 4 is a perspective view of a main part of a semiconductor device according to another embodiment of the invention.
FIG. 5 is a cross-sectional view of a semiconductor element 11 having a two-layer structure in the form of a so-called chip-on-chip with another semiconductor element 12;
FIG. 6 is a cross-sectional view for explaining a step of forming a bump wiring.
[Explanation of symbols]
1 semiconductor substrate 2 SiO 2 film 3 a to 3 d Al electrode 4 passivation film 5 and 7 the photoresist 6 internal wiring bump 8,9 external connection bumps 10 around the bumps 11, 12 semiconductor device 13 impurity layer 15 Cutter A device forming region B Scribe line area C clearance D

Claims (2)

半導体素子形成領域に外部接続用バンプを配置しているとともに、素子内配線を行うために、外部接続用バンプの高さよりも低い高さの内部配線用バンプを配置し、当該内部配線用バンプを外部接続用バンプに接続していることを特徴とする半導体素子。In addition to arranging external connection bumps in the semiconductor element formation region, in order to perform internal wiring, an internal wiring bump having a height lower than the height of the external connection bump is arranged, and the internal wiring bumps are arranged. A semiconductor element connected to an external connection bump. 半導体基板の半導体素子形成領域外に周囲バンプを配置しているとともに、素子内配線を行うために、周囲バンプの高さよりも低い高さの内部配線用バンプを配置し、前記内部配線用バンプを周囲バンプに接続していることを特徴とする半導体素子。Surrounding bumps are disposed outside the semiconductor element formation region of the semiconductor substrate, and in order to perform internal wiring, internal wiring bumps having a height lower than the height of the surrounding bumps are disposed, and the internal wiring bumps are arranged. A semiconductor element connected to a peripheral bump.
JP04039999A 1999-02-18 1999-02-18 Semiconductor element Expired - Lifetime JP3798568B2 (en)

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JP04039999A JP3798568B2 (en) 1999-02-18 1999-02-18 Semiconductor element
US09/504,874 US6707159B1 (en) 1999-02-18 2000-02-16 Semiconductor chip and production process therefor
US10/767,439 US7329562B2 (en) 1999-02-18 2004-01-30 Process of producing semiconductor chip with surface interconnection at bump
US12/068,596 US20080138976A1 (en) 1999-02-18 2008-02-08 Semiconductor chip and production process therefor

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JP4904619B2 (en) * 2000-11-29 2012-03-28 富士通セミコンダクター株式会社 Semiconductor device
US6727533B2 (en) 2000-11-29 2004-04-27 Fujitsu Limited Semiconductor apparatus having a large-size bus connection
US6646347B2 (en) * 2001-11-30 2003-11-11 Motorola, Inc. Semiconductor power device and method of formation
KR20110124993A (en) 2010-05-12 2011-11-18 삼성전자주식회사 Semiconductor chip and semiconductor package including the same and method of manufacturing the same

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