JP3716327B2 - Method for processing printed circuit boards - Google Patents

Method for processing printed circuit boards Download PDF

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JP3716327B2
JP3716327B2 JP23129696A JP23129696A JP3716327B2 JP 3716327 B2 JP3716327 B2 JP 3716327B2 JP 23129696 A JP23129696 A JP 23129696A JP 23129696 A JP23129696 A JP 23129696A JP 3716327 B2 JP3716327 B2 JP 3716327B2
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printed circuit
circuit board
inner layer
resin layer
photosensitive resin
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JPH1065051A (en
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利久 上原
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株式会社アイレックス
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、多層プリント基板上にＩＣベアチップ即ちＬＳＩチップを表面実装するためのプリント基板の加工方法に関する。
【０００２】
【従来の技術】
従来、電子機器に用いられる基板において、電子機器の小型化や薄型化等の要求に応えるため、様々な形状並びに構造のＬＳＩパッケージ並びにプリント基板が案出されている。
例えば、ＬＳＩパッケージについては、ピン数の多いＬＳＩパッケージの主流としてはプラスチックＱＦＰ（quad flat package ）が用いられているが、ピン数を増加させることに限界があった。
そこで、上記プラスチックＱＦＰに代えて、裏面に多数のピンをアレイ状に配置した表面実装型のＬＳＩパッケージが用いられるようになってきた。
表面実装型のＬＳＩパッケージとして一例を挙げると、多層プリント基板（以下、単にプリント基板という）の裏面に球状のハンダをアレイ状に配置して入出力端子を形成し、ＩＣベアチップ（ＬＳＩチップ）をプリント基板の表面上に載置して樹脂で封止して成るＢＧＡ（ball grid array ）が用いられている。
【０００３】
ＢＧＡは、一例として図８に示すように、プリント基板ａの裏面に球状のハンダをアレイ状に配置して成る入出力端子ｂを設け、プリント基板ａの表面にＩＣベアチップ（ＬＳＩチップ）ｃを載置し、入出力端子ｂに接続された導体（リード）ｄと、ＩＣベアチップｃとをボンディング・ワイヤｅで接続し、外周の導体ｄをソルダ・レジストｆで覆い、全体を樹脂から成る封止剤ｇで封止している。以上、ＬＳＩパッケージについてのみ述べてきたが、ＩＣベアチップを実装する通常のプリント基板においても、同様の構成を備えている。
【０００４】
プリント基板のＩＣベアチップを実装する部位を削り出す手段として、一般に機械加工が用いられているが、絶縁性樹脂の厚さが一定ではないために、樹脂表面から内層回路までの深さが変化することになり、削り過ぎ、或いは削り残しを生じるという問題があった。
この問題を解決するための手段が提案されており、例えば、主軸支持機構に支持された座ぐり用回転切削刀（ドリルビット）と、主軸支持機構の主軸の送り方向に向けて移動可能のプローブとを備え、このプローブに高周波電流を印加してプリント基板の内層ボンディング端子回路（内層回路）に渦電流を発生させ、発生した渦電流による高周波磁界を検出し、検出された高周波磁界の強さに基づき前記ドリルビットと前記被切削部との距離を算出し、この算出値に基づいて前記主軸の送り量を制御するものが知られている。
【０００５】
【発明が解決しようとする課題】
しかしながら、上記従来のプリント基板の加工方法においては、切削機械装置が高価になるとともに、プリント基板の内層ボンディング端子回路の形状によって発生する渦電流に強弱が生じて渦電流による高周波磁界が変化し、検出された高周波磁界の強さに変動が生じて、算出するドリルビットと被切削部との距離が正確に測定できない恐れがあるという問題があった。
また、プリント基板の表面側にも銅箔等で外層ボンディング端子回路が形成されているために、外層ボンディング端子回路にも渦電流が発生して高周波磁界が発生する恐れがあり、内層ボンディング端子回路で発生する高周波磁界に干渉することになって、ドリルビットと被切削部との距離が正確に測定できない恐れがあるという問題があった。
【０００６】
本発明の目的は、絶縁性樹脂の厚さの変動による影響を受けずに、簡単な構成で、高精度の切削加工を行うことを可能とするプリント基板の加工方法を提供することである。
【０００７】
【課題を解決するための手段】
上記目的を達成するために本発明のプリント基板の加工方法は、ＩＣベアチップを実装するプリント基板の加工方法であって、感光性樹脂層をプリント基板の表面に設け、少なくともプリント基板のＩＣベアチップの実装位置の略中心部を除いて感光させ、未感光部分を除去して未感光部分の底部に基準面を形成し、該基準面から内層回路の上面高さを測定し、測定した内層回路の上面高さ位置の樹脂層を削ることによって内層回路を露出させるものである。
この構成により、絶縁性樹脂層の厚さのバラツキの影響を受けること無く、削りだす部分の中央位置で内層回路の下面高さを測定測定できるから、露出させる回路位置に近い場所で測定でき、精度を高くすることができる。
また、削りだし加工機に特別な構成を必要とせず、絶縁性樹脂層を設けるに当たって特別な加工精度を必要としないものである。
【０００８】
【発明の実施の形態】
本発明の実施例を図面を参照して説明する。
図７において、本発明の加工方法を適用して製作したプリント基板について説明する。
プリント基板１の一側面に内層回路２を予め形成し、その上に絶縁層となる感光性樹脂層３を適宜位置に設けて、内層回路２の導体部分であるパッド20を露出させ、他の部分を感光性樹脂層３で被覆する。
なお、感光性樹脂層３は、紫外線等の光を当てると硬化する光硬化性を備えた樹脂である。
【０００９】
ＩＣベアチップ４を、本実施例では対向して配設されている内層回路２のパッド20の間に載置し、ボンディングワイヤ５を用いてＩＣベアチップ４とパッド20とをボンディング接続する。
なお、内層回路２のパッド20は、ＩＣベアチップを挟んで両側に対向して設けられたものに限定されるわけではなく、ＩＣベアチップの全周或いは三方を囲むように、或いは一方に設けても良いことは当然である。
【００１０】
ＩＣベアチップ４の周囲に感光性樹脂層３の厚さによる段差が形成されて流れ防止ダムとなり、ＩＣベアチップ４を載置した部分を覆って樹脂等の封止剤６が流し込まれる際に、不要な部分にまで封止剤６が流出することを防止する。
ＩＣベアチップ４を載置した部分を覆う封止剤６が流し込まれ、ＩＣベアチップ４とボンディングワイヤ５及びパッド20を封止剤６で被覆して保護している。
感光性樹脂層３の外側面と内層回路２とを接続するために、感光性樹脂層３の所定位置にバイアホール７を感光性樹脂層３を貫通して穿設し、内層回路２をバイアホール７内において露出させた後、メッキ70によってバイアホール７内の内層回路２と感光性樹脂層３の外側面とを電気的に接続し、感光性樹脂層３の外側面でメッキ70に接続された外側回路71が設けられている。
【００１１】
外側回路71は、感光性樹脂層３の外側面において、電子部品等に接続する外部パッド72を備えており、外部パッド72と、別に感光性樹脂層３の外側面に設けられた電子部品実装用パッド73とに電子部品８の脚をハンダ付けする。
なお、本実施例においては、プリント基板の一側面にのみＩＣベアチップを設けたものについて述べてきたが、プリント基板の両側面に、それぞれ内層回路を設け、上記実施例と同様にしてＩＣベアチップを設けることができることは勿論である。
また、上記電子部品８に代えて、ＩＣベアチップを接続することもできる。
【００１２】
図を参照して本発明の加工方法の一例について説明する。
図２において、プリント基板の基板１の表面に、部品実装に合わせた導体回路である内層回路２をエッチング加工等によって形成した（図２イ参照）後、その上から絶縁層となる感光性樹脂を塗布し、プリント基板１の全面に紫外線等の光を当てると硬化する光硬化性の感光性樹脂層３を形成して（図２ロ参照）乾燥させる。
紫外線等の光を当てずに硬化させない部分、即ち光を照射しないで感光性樹脂を除去する部分として、ＩＣベアチップ４を載置する矩形部分111 の略中央に、樹脂層３の底部に達する略円筒形部分110 と、露出させたい内層回路２の部分（内層回路２のバイアホール７等）を定める。
上記円筒形部分110 の上面に対応する形状（本実施例では円形）の部分11と、露出させたい内層回路２の部分（バイアホール７等）12，13を黒くする、即ち光不透過性とし、他の部分を光透過性としたマスクフィルム10を、感光性樹脂層３の上面に位置合わせして載置し（図２ハ参照）、紫外線などの光を当てて感光性樹脂層３を光硬化させる。
【００１３】
感光性樹脂層３を光硬化させた後、アルカリ性溶液等で感光性樹脂層３を現像し（図２ニ参照）、マスクフィルム10の黒い部分に対応した光の当たっていない未硬化の部分の感光性樹脂を、水、アルカリ性溶液、有機溶剤等の溶液を用いて洗い流して除去し、円筒形部分110 と内層回路２の所定部分（バイアホール７）とを露出させる（図２ホ参照）。
未硬化の感光性樹脂を除去した後、図３及び図４に示すように、バイアホール７内に内層回路２と感光性樹脂層３の外側面とを電気的に接続するメッキ70を施すとともに、エッチング加工により感光性樹脂層３上に回路形成を行って外側回路71、外部パッド72、電子部品実装用パッド73等を形成する。
【００１４】
次に、図５に示すように、測定プローブ14を円筒形部分110 内に挿入し、円筒形部分110 内底部に露出された基板１の上面１Ａ即ち内層回路２の下面の高さ位置を確認して、内層回路２の下面（即ち、基板１の上面１Ａ）を基準面として定める。
該基準面（内層回路２の下面、即ち基板１の上面１Ａ）から、内部パッド20の厚さ（即ち、内部パッド20を形成する銅箔の厚さであり、既知の値である）だけ上昇させた位置を加工設定位置Ａとして算出する。
図１に示すように、ドリルピット15により、該加工設定位置Ａを研削して内部パッド20の上面を露出させ、ＩＣベアチップ４を載置する矩形部分111 を形成する（図６参照）。
【００１５】
この構成により、必要部分に紫外線等の光を当てて感光性樹脂を硬化させ、未硬化の部分を、水、アルカリ性溶液、有機溶剤等の溶液を用いて除去することにより、容易に且つ高い精度をもって必要な範囲の感光性樹脂を除去し、プリント基板の基板１の上面１Ａを確実に露出させることができるから、機械加工を行う際の基準面として内層回路２の下面（即ち、基板１の上面１Ａ）を採用することができ、内層回路２の下面（基板１の上面１Ａ）の高さ位置を測定確認し、内部パッド20を形成する銅箔の厚さであり、既知の値である内部パッド20の厚さだけ上昇させた位置を加工設定位置Ａとして算出することによって、絶縁性樹脂層の厚さの影響を受けること無く、削り代を正確に定めることができる。
【００１６】
したがって、絶縁性樹脂層の厚さのバラツキの影響を受けること無く、削りだす部分の中央位置で内層回路の下面高さを測定できるから、露出させる回路位置に近い場所で測定でき、精度を高くすることができる。
また、削りだし加工機に特別な構成を必要とせず、絶縁性樹脂層を設けるに当たって特別な加工精度を必要としないものである。
【００１７】
【発明の効果】
本発明は上述のとおり構成されているから、以下に述べるとおりの効果を奏する。
感光性樹脂層をプリント基板の表面に設け、少なくともプリント基板のＩＣベアチップの実装位置の略中心部を除いて感光させ、未感光部分を除去して未感光部分の底部である基板の上面即ち内部回路の下面を基準面とし、該基準面から内層回路の上面高さ位置の樹脂層を削って内層回路を露出させることにより、絶縁性樹脂層の厚さのバラツキの影響を受けること無く、削りだす部分の中央位置で内層回路の下面高さを測定できるから、露出させる回路位置に近い場所で測定でき、精度を高くすることができる。
また、削りだし加工機に特別な構成を必要とせず、絶縁性樹脂層を設けるに当たって特別な加工精度を必要としないものである。
【図面の簡単な説明】
【図１】 本発明のプリント基板の機械加工の説明図である。
【図２】 本発明のプリント基板の光硬化加工方法の説明図である。
【図３】 本発明のプリント基板の光硬化加工終了時の断面図である。
【図４】 本発明のプリント基板の光硬化加工終了時の平面図である。
【図５】 本発明のプリント基板の機械加工方法の説明図である。
【図６】 同じく本発明のプリント基板の機械加工方法の説明図である。
【図７】 本発明を適用した表面実装型ＬＳＩパッケージの一例を示す断面図である。
【図８】 従来の表面実装型ＬＳＩパッケージの一例を示す断面図である。
【符号の説明】
１ 基板、２ 内層回路、３ 感光性樹脂、４ ＩＣベアチップ
５ ボンディングワイヤ、６ 封止剤、７ バイアホール、20 パッド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board processing method for surface mounting an IC bare chip, that is, an LSI chip, on a multilayer printed circuit board.
[0002]
[Prior art]
Conventionally, LSI packages and printed circuit boards having various shapes and structures have been devised in order to meet demands for downsizing and thinning electronic devices in substrates used in electronic devices.
For example, for LSI packages, plastic QFP (quad flat package) is used as the mainstream of LSI packages with many pins, but there is a limit to increasing the number of pins.
Therefore, instead of the plastic QFP, a surface mount type LSI package in which a large number of pins are arranged in an array on the back surface has been used.
As an example of a surface-mount LSI package, spherical solder is arranged in an array on the back surface of a multilayer printed circuit board (hereinafter simply referred to as a printed circuit board) to form input / output terminals, and an IC bare chip (LSI chip) is formed. A BGA (ball grid array) is used that is placed on the surface of a printed circuit board and sealed with resin.
[0003]
For example, as shown in FIG. 8, the BGA is provided with input / output terminals b formed by arranging spherical solder in an array on the back surface of the printed circuit board a, and an IC bare chip (LSI chip) c is provided on the surface of the printed circuit board a. The conductor (lead) d placed and connected to the input / output terminal b and the IC bare chip c are connected by the bonding wire e, the outer peripheral conductor d is covered with the solder resist f, and the whole is sealed with resin. Sealed with a stopper g. Although only the LSI package has been described above, a normal printed circuit board on which an IC bare chip is mounted has a similar configuration.
[0004]
Machining is generally used as a means for scraping a portion of a printed circuit board on which an IC bare chip is mounted. However, since the thickness of the insulating resin is not constant, the depth from the resin surface to the inner layer circuit changes. As a result, there was a problem that overcutting or uncutting occurred.
Means for solving this problem have been proposed. For example, a counterbore rotary cutting blade (drill bit) supported by the spindle support mechanism and a probe movable in the feed direction of the spindle of the spindle support mechanism The eddy current is generated in the inner layer bonding terminal circuit (inner layer circuit) of the printed circuit board by applying a high frequency current to the probe, the high frequency magnetic field due to the generated eddy current is detected, and the strength of the detected high frequency magnetic field The distance between the drill bit and the part to be cut is calculated based on the above, and the feed amount of the spindle is controlled based on the calculated value.
[0005]
[Problems to be solved by the invention]
However, in the above-described conventional method for processing a printed circuit board, the cutting machine device is expensive and the strength of the eddy current generated by the shape of the inner layer bonding terminal circuit of the printed circuit board is changed to change the high-frequency magnetic field due to the eddy current, There is a problem in that the detected strength of the high-frequency magnetic field varies, and the distance between the calculated drill bit and the part to be cut cannot be measured accurately.
In addition, since the outer layer bonding terminal circuit is formed of copper foil or the like on the surface side of the printed circuit board, an eddy current may be generated in the outer layer bonding terminal circuit, and a high frequency magnetic field may be generated. There is a problem that the distance between the drill bit and the part to be cut may not be measured accurately because it interferes with the high-frequency magnetic field generated in the above.
[0006]
An object of the present invention is to provide a method for processing a printed circuit board that enables high-precision cutting with a simple configuration without being affected by variation in the thickness of an insulating resin.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a printed circuit board processing method of the present invention is a printed circuit board processing method for mounting an IC bare chip, wherein a photosensitive resin layer is provided on the surface of the printed circuit board, and at least the IC bare chip of the printed circuit board is mounted. Except for the substantially central portion of the mounting position, it is exposed, the unexposed portion is removed, a reference surface is formed at the bottom of the unexposed portion, the upper surface height of the inner layer circuit is measured from the reference surface, and the measured inner layer circuit The inner layer circuit is exposed by scraping the resin layer at the upper surface height position.
With this configuration, the lower surface height of the inner layer circuit can be measured and measured at the center position of the part to be cut out without being affected by variations in the thickness of the insulating resin layer, so that it can be measured at a location close to the exposed circuit position, The accuracy can be increased.
Further, a special configuration is not required for the shaving machine, and no special processing accuracy is required for providing the insulating resin layer.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
In FIG. 7, a printed circuit board manufactured by applying the processing method of the present invention will be described.
An inner layer circuit 2 is formed in advance on one side of the printed circuit board 1 and a photosensitive resin layer 3 serving as an insulating layer is provided on the inner surface of the printed circuit board 1 at an appropriate position to expose the pad 20 which is a conductor portion of the inner layer circuit 2. The portion is covered with the photosensitive resin layer 3.
The photosensitive resin layer 3 is a resin having photocurability that cures when exposed to light such as ultraviolet rays.
[0009]
The IC bare chip 4 is placed between the pads 20 of the inner layer circuit 2 disposed opposite to each other in this embodiment, and the IC bare chip 4 and the pads 20 are bonded to each other using the bonding wires 5.
The pads 20 of the inner layer circuit 2 are not limited to those provided opposite to both sides of the IC bare chip, and may be provided so as to surround the entire circumference or three sides of the IC bare chip or on one side. It is natural to be good.
[0010]
A step due to the thickness of the photosensitive resin layer 3 is formed around the IC bare chip 4 to form a flow prevention dam, which is unnecessary when a sealing agent 6 such as a resin is poured over the portion where the IC bare chip 4 is placed. The sealant 6 is prevented from flowing out to such a part.
A sealing agent 6 covering the portion on which the IC bare chip 4 is placed is poured, and the IC bare chip 4, the bonding wire 5 and the pad 20 are covered with the sealing agent 6 to protect them.
In order to connect the outer surface of the photosensitive resin layer 3 and the inner layer circuit 2, a via hole 7 is drilled through the photosensitive resin layer 3 at a predetermined position of the photosensitive resin layer 3 to connect the inner layer circuit 2 to the via. After being exposed in the hole 7, the inner circuit 2 in the via hole 7 and the outer surface of the photosensitive resin layer 3 are electrically connected by the plating 70, and the outer surface of the photosensitive resin layer 3 is connected to the plating 70. An outer circuit 71 is provided.
[0011]
The outer circuit 71 includes an external pad 72 connected to an electronic component or the like on the outer surface of the photosensitive resin layer 3, and an electronic component mounting provided on the outer surface of the photosensitive resin layer 3 separately from the external pad 72. The leg of the electronic component 8 is soldered to the pad 73 for use.
In this embodiment, the case where the IC bare chip is provided only on one side surface of the printed board has been described. However, the inner layer circuit is provided on each side surface of the printed board, and the IC bare chip is formed in the same manner as in the above embodiment. Of course, it can be provided.
Further, instead of the electronic component 8, an IC bare chip can be connected.
[0012]
An example of the processing method of the present invention will be described with reference to the drawings.
In FIG. 2, an inner layer circuit 2 which is a conductor circuit suitable for component mounting is formed on the surface of the substrate 1 of a printed circuit board by etching or the like (see FIG. 2A), and then a photosensitive resin that becomes an insulating layer from above Is applied, and a photocurable photosensitive resin layer 3 that is cured when light such as ultraviolet rays is applied to the entire surface of the printed circuit board 1 is formed (see FIG. 2B) and dried.
As a part that is not cured without being irradiated with light such as ultraviolet rays, that is, a part that removes the photosensitive resin without irradiating light, it is approximately at the center of the rectangular part 111 on which the IC bare chip 4 is placed and reaches the bottom of the resin layer 3. The cylindrical portion 110 and the portion of the inner layer circuit 2 to be exposed (such as the via hole 7 of the inner layer circuit 2) are defined.
The portion 11 having a shape (circular in this embodiment) corresponding to the upper surface of the cylindrical portion 110 and the portions (via holes 7 etc.) 12 and 13 of the inner layer circuit 2 to be exposed are blackened, that is, made light-impermeable. Then, the mask film 10 having the other part light-transmitting is placed in alignment with the upper surface of the photosensitive resin layer 3 (see FIG. 2C), and the photosensitive resin layer 3 is applied by applying light such as ultraviolet rays. Light cure.
[0013]
After photo-curing the photosensitive resin layer 3, the photosensitive resin layer 3 is developed with an alkaline solution or the like (see FIG. 2D), and the uncured portion of the mask film 10 corresponding to the black portion that is not exposed to light. The photosensitive resin is washed away using a solution such as water, an alkaline solution, or an organic solvent to expose the cylindrical portion 110 and a predetermined portion (via hole 7) of the inner layer circuit 2 (see FIG. 2E).
After removing the uncured photosensitive resin, as shown in FIGS. 3 and 4, plating 70 is applied in the via hole 7 to electrically connect the inner layer circuit 2 and the outer surface of the photosensitive resin layer 3. Then, a circuit is formed on the photosensitive resin layer 3 by etching to form an outer circuit 71, an external pad 72, an electronic component mounting pad 73, and the like.
[0014]
Next, as shown in FIG. 5, the measuring probe 14 is inserted into the cylindrical portion 110, and the height position of the upper surface 1A of the substrate 1 exposed at the inner bottom of the cylindrical portion 110, that is, the lower surface of the inner layer circuit 2 is confirmed. Then, the lower surface of the inner layer circuit 2 (that is, the upper surface 1A of the substrate 1) is defined as the reference surface.
Increased from the reference plane (the lower surface of the inner layer circuit 2, that is, the upper surface 1A of the substrate 1) by the thickness of the inner pad 20 (that is, the thickness of the copper foil forming the inner pad 20, which is a known value). The processed position is calculated as the machining setting position A.
As shown in FIG. 1, the machining setting position A is ground by a drill pit 15 to expose the upper surface of the internal pad 20, and a rectangular portion 111 on which the IC bare chip 4 is placed is formed (see FIG. 6).
[0015]
With this configuration, the photosensitive resin is cured by applying light such as ultraviolet rays to the necessary part, and the uncured part is removed using a solution such as water, an alkaline solution, an organic solvent, etc., easily and with high accuracy. Therefore, the photosensitive resin in a necessary range can be removed and the upper surface 1A of the substrate 1 of the printed circuit board can be reliably exposed, so that the lower surface of the inner layer circuit 2 (that is, the substrate 1) can be used as a reference surface for machining. The upper surface 1A) can be adopted, and the height position of the lower surface of the inner layer circuit 2 (the upper surface 1A of the substrate 1) is measured and confirmed, and the thickness of the copper foil forming the internal pad 20 is a known value. By calculating the position increased by the thickness of the internal pad 20 as the processing setting position A, the cutting allowance can be accurately determined without being affected by the thickness of the insulating resin layer.
[0016]
Therefore, the height of the lower surface of the inner circuit can be measured at the center position of the part to be cut out without being affected by the thickness variation of the insulating resin layer. can do.
Further, a special configuration is not required for the shaving machine, and no special processing accuracy is required for providing the insulating resin layer.
[0017]
【The invention's effect】
Since this invention is comprised as mentioned above, there exists an effect as described below.
A photosensitive resin layer is provided on the surface of the printed circuit board, exposed at least at substantially the center of the mounting position of the IC bare chip on the printed circuit board, and the unexposed area is removed to remove the unexposed area. By using the lower surface of the circuit as a reference surface and removing the resin layer at the height of the upper surface of the inner layer circuit from the reference surface to expose the inner layer circuit, cutting without being affected by the variation in the thickness of the insulating resin layer Since the lower surface height of the inner layer circuit can be measured at the center position of the soaking portion, it can be measured at a location close to the circuit position to be exposed, and the accuracy can be increased.
Further, a special configuration is not required for the shaving machine, and no special processing accuracy is required for providing the insulating resin layer.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of machining of a printed board according to the present invention.
FIG. 2 is an explanatory diagram of a method of photocuring a printed circuit board according to the present invention.
FIG. 3 is a cross-sectional view of the printed circuit board according to the present invention at the end of photocuring processing.
FIG. 4 is a plan view at the end of photocuring processing of the printed circuit board of the present invention.
FIG. 5 is an explanatory diagram of a printed board machining method according to the present invention.
FIG. 6 is also an explanatory diagram of a printed board machining method according to the present invention.
FIG. 7 is a cross-sectional view showing an example of a surface mount LSI package to which the present invention is applied.
FIG. 8 is a cross-sectional view showing an example of a conventional surface mount LSI package.
[Explanation of symbols]
1 substrate, 2 inner layer circuit, 3 photosensitive resin, 4 IC bare chip, 5 bonding wire, 6 sealant, 7 via hole, 20 pads

Claims (1)

ＩＣベアチップを実装するプリント基板の加工方法であって、感光性樹脂層をプリント基板の表面に設け、少なくともプリント基板のＩＣベアチップの実装位置の略中心部を除いて感光させ、未感光部分を除去して未感光部分の底部に基準面を形成し、該基準面から内層回路の上面高さを測定し、測定した内層回路の上面高さ位置の樹脂層を削ることによって内層回路を露出させることを特徴とするプリント基板の加工方法。A method of processing a printed circuit board for mounting an IC bare chip, in which a photosensitive resin layer is provided on the surface of the printed circuit board, and at least the central portion of the mounting position of the IC bare chip on the printed circuit board is exposed, and unexposed parts are removed. Forming a reference surface at the bottom of the unexposed portion, measuring the upper surface height of the inner layer circuit from the reference surface, and exposing the inner layer circuit by scraping the resin layer at the upper surface height position of the measured inner layer circuit. A printed circuit board processing method characterized by the above.
JP23129696A 1996-08-14 1996-08-14 Method for processing printed circuit boards Expired - Fee Related JP3716327B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23129696A JP3716327B2 (en) 1996-08-14 1996-08-14 Method for processing printed circuit boards

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23129696A JP3716327B2 (en) 1996-08-14 1996-08-14 Method for processing printed circuit boards

Publications (2)

Publication Number Publication Date
JPH1065051A JPH1065051A (en) 1998-03-06
JP3716327B2 true JP3716327B2 (en) 2005-11-16

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CN104135815B (en) * 2013-05-03 2018-01-02 讯芯电子科技（中山）有限公司 A kind of board structure of circuit for preventing metal pad to be scraped off and manufacture method

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