JP3569642B2 - Semiconductor device carrier substrate, method of manufacturing the same, and method of manufacturing a semiconductor device - Google Patents

Semiconductor device carrier substrate, method of manufacturing the same, and method of manufacturing a semiconductor device Download PDF

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JP3569642B2
JP3569642B2 JP6379099A JP6379099A JP3569642B2 JP 3569642 B2 JP3569642 B2 JP 3569642B2 JP 6379099 A JP6379099 A JP 6379099A JP 6379099 A JP6379099 A JP 6379099A JP 3569642 B2 JP3569642 B2 JP 3569642B2
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semiconductor device
plating film
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manufacturing
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JP2000260897A (en
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和人 米持
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置用キャリア基板及びその製造方法及び半導体装置の製造方法に関し、さらに詳細には、樹脂封止型であると共にリードレス表面実装型の半導体装置を好適に製造するために用いる半導体装置用キャリア基板及びその製造方法及び半導体装置の製造方法に関する。
【０００２】
【従来の技術】
半導体装置の技術分野では、電子機器の小型化及び高集積化に伴い、半導体チップ自体の微細化と共に、パッケージの外部接続端子のピッチを小さくすることで、半導体装置を小型化及び高集積化する要請がある。
樹脂封止型の半導体装置の小型化を実現する構造として、特開平９−１６２３４８号には、リードレス表面実装型のパッケージ構造が提案されている。
すなわち、そのパッケージ構造が利用された半導体装置は、図６（ｄ）に示すように、半導体チップ２０と、半導体チップ２０を封止する樹脂パッケージ２２と、樹脂パッケージ２２の実装基板へ接続される側の面に突起して設けられた樹脂突起２４と、樹脂突起２４の外面に設けられためっき被膜１４と、半導体チップ２０の電極２８とめっき被膜１４とを電気的に接続するワイヤ３０とを具備する。
この半導体装置は、図５（ｄ）に示すようなめっき被膜１４を担持すると共に前記半導体チップ２０が搭載される板状の金属基材１２を備える半導体装置用キャリア基板５０が用いられて製造される。
【０００３】
先ず、キャリア基板５０の製造方法について、図５に基づいて説明する。
最初に、金属基材１２の両面にレジスト３９を塗布し、その金属基材１２の片面１２ａの前記樹脂突起２４に対応する部位のレジスト３９を除去してレジストパターンを形成する（図５（ａ））。
次に、上記のようにレジストパターンを形成した金属基材１２をエッチング液に浸漬してエッチング加工を行い、樹脂突起２４に対応するレジスト３９が除去された部位をハーフエッチングして凹部１６を形成する（図５（ｂ））。
次に、レジストパターンをそのままにして、めっき加工を施し、凹部１６内にめっき被膜１４を形成する（図５（ｃ））。
そして、レジストを剥離することで、キャリア基板５０が形成される（図５（ｄ））。
【０００４】
次に、以上のように形成されたキャリア基板５０を利用して、半導体装置を製造する製造方法について、図６に基づいて説明する。
先ず、キャリア基板５０の前記片面１２ａ上に接着等によって、半導体チップ２０を搭載する（図６（ａ））。
次に、半導体チップ２０に設けられた電極２８と、キャリア基板５０の金属基材１２上に形成されためっき被膜１４とを、ワイヤーボンディングによってワイヤ３０で電気的に接続する（図６（ｂ））。
次に、キャリア基板５０上に、半導体チップ２０及びワイヤ３０による接続部を樹脂で封止すべく、樹脂モールド成形によって樹脂パッケージ２２を形成する（図６（ｃ））。
そして、キャリア基板５０のめっき被膜１４を残して金属基材１２をエッチングで除去する（図６（ｄ））。これにより、めっき被膜１４がパッケージの外部に露出して外部接続端子の接続面となり、実装基板との接続が可能な構造の半導体装置が完成する。なお、金属基材１２の材質としては、エッチングが好適になされるよう、例えば、銅（Ｃｕ）が用いられている。
【０００５】
【発明が解決しようとする課題】
しかしながら、上記従来のキャリア基板５０にあっては、ハーフエッチングによって形成された凹部１６のみについてめっきを施されることになるが、めっきの特性上、凹部１６の面積を一定以上小さくすることができない。これは、凹部１６が微細に形成された場合、めっき液がその凹部１６内へ適切に回り込みことは難しく、所定のめっき層を形成することが困難であることによる。
従って、半導体装置の実装基板と接続する外部接続端子のピッチを小さくして半導体装置を小型化することができないという課題があった。
【０００６】
そこで、本発明は上記課題を解決すべくなされたものであり、その目的とするところは、樹脂封止型であると共にリードレス表面実装型の半導体装置における外部接続端子のピッチを小さく形成することができる半導体装置用キャリア基板及びその製造方法及び半導体装置の製造方法を提供することにある。
【０００７】
【課題を解決するための手段】
本発明は上記目的を達成するため次の構成を備える。
【０００８】
すなわち、本発明の半導体装置用キャリア基板の製造方法は、半導体チップと、該半導体チップを封止する樹脂パッケージと、該樹脂パッケージの実装基板へ接続される側の面に設けられた樹脂突起と、該樹脂突起の外面に設けられためっき被膜と、前記半導体チップの電極と前記めっき被膜とを電気的に接続するワイヤとを具備する半導体装置を製造する際に用いられる半導体装置用キャリア基板であって、前記半導体装置の製造工程で、前記半導体チップが搭載される板状の金属基材と、前記金属基材に予めめっき被膜が形成された後、該金属基材の前記樹脂突起に対応する位置に、プレス加工によって形成された凹部と、前記凹部の内面に形成された前記めっき被膜とを具備する半導体装置用キャリア基板の製造方法において、前記金属基材の片面にめっき被膜を形成するめっき工程と、前記金属基材のめっき被膜が形成された面の前記樹脂突起に対応する位置に、内面に前記めっき被膜が形成された前記凹部をプレス加工によって形成する凹部形成工程と、前記凹部の内面以外のめっき被膜を除去する不要めっき部の除去工程とを有し、前記不要めっき部の除去工程は、前記金属基材をめっきの剥離液に浸けて、前記凹部内の前記めっき被膜の剥離が遅いことを利用して、凹部の内面以外のめっき被膜を除去することを特徴とする。
【０００９】
これにより、容易に好適な半導体装置用キャリア基板を製造できる。
【００１０】
また、前記不要めっき部の除去工程は、前記凹部の内面以外のめっき被膜を研削等によって機械的に除去することでも、好適な半導体装置用キャリア基板を製造できる。
【００１１】
また、前記プレス加工は、潰し加工、絞り加工、或いは半抜き加工のうちのいずれか一つであることで、既存の技術を用いて、容易且つ確実に前記凹部を好適に形成できる。
【００１２】
また、本発明は、前記半導体装置用キャリア基板の製造方法によって製造される半導体装置用キャリア基板にもある。
【００１３】
また、本発明は、前記半導体装置用キャリア基板を用いて半導体装置を製造する際に、前記キャリア基板上に半導体チップを搭載する半導体チップ搭載工程と、前記半導体チップに設けられた電極と前記金属基材の凹部の内面に形成された前記めっき被膜とをワイヤで電気的に接続するワイヤーボンディング工程と、前記キャリア基板上に搭載された半導体チップとワイヤを樹脂で封止して樹脂パッケージを形成するモールド成形工程と、前記めっき被膜を残して前記金属基材を除去する金属基材の除去工程とを有することを特徴とする半導体装置の製造方法にもある。
【００１４】
【発明の実施の形態】
以下、本発明の好適な実施の形態を添付図面に基づいて詳細に説明する。
図１は本発明にかかる半導体装置用キャリア基板（以下、「キャリア基板」という）の製造方法の一実施例を説明する工程図（断面図）である。また、図２及び図３はプレス加工の他の実施例を説明する工程図（断面図）である。また、図４は本発明にかかるキャリア基板の製造方法の他の実施例を説明する工程図（断面図）である。
【００１５】
（第１実施例）
本実施例によって製造されるキャリア基板１０は、図１（ｃ）に示すように、前記半導体装置の製造工程で、半導体チップが搭載されると共に最終的には除去される板状の金属基材１２と、その金属基材１２に予めめっき被膜が形成された後、金属基材１２の前述した樹脂突起２４（図６（ｄ）参照）に対応する位置に、プレス加工によって形成された凹部１６と、前記プレス加工によって押し下げられることによって凹部１６の内面に形成されためっき被膜１４とを具備する。
このキャリア基板１０を用いることで、半導体チップ２０と、半導体チップ２０を封止する樹脂パッケージ２２と、樹脂パッケージ２２の実装基板へ接続される側の面に突起して設けられた樹脂突起２４と、樹脂突起２４の外面に設けられためっき被膜１４と、半導体チップの電極２８とめっき被膜１４とを電気的に接続するワイヤ３０とを具備する半導体装置（図６（ｄ）参照）を、好適に製造することができる。
【００１６】
次に、図１に基づいて、本発明にかかるキャリア基板の製造方法の第１実施例について工程順に説明する。
先ず、図１（ａ）はめっき工程を示しており、この工程では、金属基材１２の片面１２ａに電解めっきを施して複数の凹部１６形成領域にわたってめっき層１３を形成する。
このめっき層１３の構成としては、金（Ａｕ）、パラジウム（Ｐｄ）、ニッケル（Ｎｉ）、パラジウム（Ｐｄ）の順にめっきを施し、４層のめっき層を形成したものが好適である。この４層のめっき層１３から成るめっき被膜１４が、半導体装置の樹脂突起２４に転写された状態となった際、凹部１６の最下層の金めっき層が表面に露出して外部接続端子の接続面になる。この最下層の金めっき層は、はんだと好適に結合できるため、回路基板への表面実装を好適に行うことができる。また、凹部１６の最表層のパラジウムめっき層はワイヤボンディングによる金ワイヤと好適に結合できるため、電気的に確実に接続できる。
なお、金属基材１２の裏面１２ｂや、めっきの不要な部分には、レジストを塗布して、めっきを施さないようにすればよい。
【００１７】
次に、図１（ｂ）は凹部１６を形成する凹部形成工程を示しており、この工程では、金属基材１２のめっきが施された面（片面１２ａ）の前記樹脂突起２４に対応する位置にプレス加工によって凹部１６を形成する。第１実施例では、プレス加工の一態様である潰し加工によって、凹部１６を形成している。
この凹部１６は、半導体装置を基板に好適に実装するため、所定以上の深さが必要となる。例えば、０．１ｍｍ程度の深さに形成される。プレス加工によれば、精度よく形成することができる。
なお、３２は潰し加工金型のポンチである。
【００１８】
そして、図１（ｃ）は不要めっき部の除去工程を示しており、この工程では、凹部１６の内面のめっき被膜１４以外のめっき被膜１５を除去する。
この不要めっき部の除去工程としては、例えば、キャリア基板１０全体をめっきの剥離液に浸けて、凹部１６内のめっき被膜１４にかかる剥離（溶解）が遅いことを利用して、凹部１６の内面以外のめっき被膜１５を溶解させて除去すればよい。
凹部１６内のめっき被膜１４にかかる剥離速度（溶解速度）が遅いのは、凹部１６が微小に形成されるため、その他の領域と比べ、めっきの剥離液の回り込む速度が遅いためである。
【００１９】
また、予め施すめっきの厚さをコントロールすることで、外部接続端子となる凹部１６内のめっき（めっき被膜１４）のみを好適な厚さに残して、他の不要部分のめっき（他のめっき被膜１５）を好適に除去することが可能である。
この方法によれば、キャリア基板１０全体をめっきの剥離液に浸けて、その浸漬時間をコントロールするだけで、容易にキャリア基板１０を製造できる。
【００２０】
また、不要めっき部の除去工程は、上記の方法に限らず、不要めっき部を機械的に除去する機械的除去方法を用いたものであってもよい。すなわち、凹部１６の内面以外のめっき被膜１５を研削等によって除去すればよい。機械的除去方法としては、前記の研削と定義されるもの範疇の他に、切削、又は研磨と定義される加工手段のいずれを利用してもよいのは勿論である。
この機械的除去工程によっても、表層を平面的に均一に除去すれば、一段下がって設けられた凹部１６内のめっき被膜１４は自動的に残るため、容易にキャリア基板１０を製造できる。
【００２１】
次に、前記プレス加工の他の態様について説明する。
図２は、プレス加工の一態様である絞り加工によって、凹部１６を形成する工程を示す断面図である。３３はポンチであり、３４はダイである。
絞り加工によっても、予めめっきが施された金属基材１２で、めっき被膜１４が設けられた凹部１６を好適に形成できる。また、前後の工程を、図１で示した工程と同様に行うことで、好適にキャリア基板を形成できる。
図３は、プレス加工の一態様である半抜き加工によって、凹部１６を形成する工程を示す断面図である。３５はポンチであり、３６はダイである。
半抜き加工によっても、予めめっきが施された金属基材１２で、めっき被膜１４が設けられた凹部１６を好適に形成できる。また、前後の工程を、図１で示した工程と同様に行うことで、好適にキャリア基板を形成できる。
【００２２】
このように、前記プレス加工は、潰し加工、絞り加工、或いは半抜き加工のうちのいずれか一つであることで、既存の技術を用いて、容易且つ確実に凹部１６を好適に形成できる。
プレス加工によれば、微細加工を好適に行うことができ、凹部１６を小さく形成することができ、そのピッチを小さくできる。従って、半導体装置の樹脂突起２４に設けられるめっき被膜１４のピッチを小さくすることが可能である。これにより、最終的に、半導体装置を、小型化、或いは外部接続端子を増やして高集積化できる。
【００２３】
（第２実施例）
次に、図４に基づいて、本発明にかかるキャリア基板の製造方法の第２実施例について工程順に説明する。
先ず、図示しないが、金属基材１２の両面にめっきレジスト３８を塗布するレジスト塗布工程がある。
そして、図４（ａ）はレジストパターン形成工程を示しており、この工程では、金属基材１２の片面１２ａの樹脂突起２４に対応する部位のめっきレジスト３８を除去してレジストパターン４０を形成する。
【００２４】
図４（ｂ）はめっき被膜１４を形成すべく金属基材１２の片面１２ａにめっき部１４ａを設ける工程を示している。このめっき部１４ａは、めっき工程及びレジストの剥離工程を経て形成される。すなわち、金属基材１２のめっきレジスト３８が除去された部位にめっきを施した後、レジストが剥離される。めっき部１４ａは、広範囲に形成されるのではなく、前記樹脂突起２４に対応して形成されるめっき被膜１４のサイズに形成される。
【００２５】
図４（ｃ）はプレス加工の工程を示しており、この工程では、金属基材１２のめっき部１４ａが形成された面（片面１２ａ）の前記樹脂突起２４に対応する位置に、内面にめっき被膜１４が設けられた凹部１６を、プレス加工によって形成する。本実施例では、絞り加工によって凹部１６が形成されている。
このようにキャリア基板を形成すれば、凹部１６の形成部分のみにめっきを施せばよいので、剥離されて無駄になるめっきが少なく、効率よく製造できる。
なお、プレス加工には、前述したように、絞り加工の他に、潰し加工、又は半抜き加工があり、いずれか一つの加工方法を選択的に用いればよい。
【００２６】
以上の実施例によれば、予め、金属基材１２にめっきを施した後、プレス加工によって凹部１６を形成する。このため、前述した従来のハーフエッチングによって形成された凹部にめっきを施す場合に比較して、小さなめっき被膜１４でも好適に形成できる。
従って、めっき被膜１４が半導体装置の樹脂突起２４に転写された状態で表面に露出して外部接続端子となる際、その外部接続端子を小さくすることができる。これにより、多数の外部接続端子が並設される場合、その外部接続端子間のピッチを小さくすることができ、ひいては、半導体装置を小型化できる。
また、プレス加工による簡単な工程で効率的にキャリア基板１０を形成できるため、コストを低減できる。
【００２７】
以上に説明したキャリア基板１０の製造に続いて、図６に示した工程と同様に、キャリア基板１０上に半導体チップ２０を付けるチップ付け（半導体チップ搭載）、ワイヤーボンディング、モールディング（樹脂モールド成形）、エッチングによる金属基材１２の除去という工程を行うことで、半導体装置を製造することができる。
以上本発明につき好適な実施例を挙げて種々説明したが、本発明はこの実施例に限定されるものではなく、発明の精神を逸脱しない範囲内で多くの改変を施し得るのはもちろんである。
【００２８】
【発明の効果】
以上のように、本発明にかかるキャリア基板よれば、金属基材に予めめっき被膜が形成された後、その金属基材の半導体装置の樹脂突起に対応する位置に、プレス加工によって形成された凹部と、その凹部の内面に形成された前記めっき被膜とを具備する。
このように凹部がプレス加工によって形成されたキャリア基板によれば、従来のような凹部を形成した後のめっき工程を行わないため、めっき被膜が設けられた凹部のピッチを好適に小さくすることができる。
従って、このキャリヤ基板を用いて形成される半導体装置における外部接続端子のピッチを小さく形成することができ、半導体装置を小形化できるという著効を奏する。
【図面の簡単な説明】
【図１】本発明にかかる半導体装置用キャリア基板の製造方法の一実施例を説明する断面工程図である。
【図２】プレス加工として絞り加工を用いた実施例を説明する断面図である。
【図３】プレス加工として半抜き加工を用いた実施例を説明する断面図である。
【図４】本発明にかかる半導体装置用キャリア基板の製造方法の他の実施例を説明する断面工程図である。
【図５】従来のキャリア基板の製造方法を説明する示す断面工程図である。
【図６】従来のキャリア基板を用いた半導体装置の製造方法を説明する断面工程図である。
【符号の説明】
１０ キャリア基板
１２ 金属基材
１４ めっき被膜
１６ 凹部
２０ 半導体チップ
２２ 樹脂パッケージ
２４ 樹脂突起
２８ 電極
３０ ワイヤ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a carrier substrate for a semiconductor device, a method for manufacturing the same, and a method for manufacturing a semiconductor device. More specifically, a semiconductor device used for suitably manufacturing a resin-sealed and leadless surface-mounted semiconductor device. The present invention relates to a carrier substrate for use, a method for manufacturing the same, and a method for manufacturing a semiconductor device.
[0002]
[Prior art]
In the technical field of semiconductor devices, miniaturization and high integration of electronic devices are accompanied by miniaturization of semiconductor chips themselves and miniaturization of pitches of external connection terminals of a package with miniaturization and high integration of electronic devices. There is a request.
As a structure for realizing miniaturization of a resin-encapsulated semiconductor device, Japanese Patent Application Laid-Open No. 9-162348 proposes a leadless surface mount type package structure.
That is, the semiconductor device using the package structure is connected to the semiconductor chip 20, the resin package 22 for sealing the semiconductor chip 20, and the mounting substrate of the resin package 22, as shown in FIG. A resin projection 24 provided on the side of the resin projection 24, a plating film 14 provided on the outer surface of the resin projection 24, and a wire 30 for electrically connecting the electrode 28 of the semiconductor chip 20 to the plating film 14. Have.
This semiconductor device is manufactured using a carrier substrate 50 for a semiconductor device, which carries a plating film 14 as shown in FIG. 5D and has a plate-shaped metal substrate 12 on which the semiconductor chip 20 is mounted. You.
[0003]
First, a method for manufacturing the carrier substrate 50 will be described with reference to FIG.
First, a resist 39 is applied to both surfaces of the metal base 12, and the resist 39 at a portion corresponding to the resin protrusion 24 on one surface 12a of the metal base 12 is removed to form a resist pattern (FIG. 5A )).
Next, the metal base material 12 on which the resist pattern has been formed as described above is immersed in an etching solution to perform an etching process, and a portion where the resist 39 corresponding to the resin protrusion 24 has been removed is half-etched to form the concave portion 16. (FIG. 5B).
Next, plating processing is performed while the resist pattern is left as it is, to form a plating film 14 in the recess 16 (FIG. 5C).
Then, the carrier substrate 50 is formed by removing the resist (FIG. 5D).
[0004]
Next, a method of manufacturing a semiconductor device using the carrier substrate 50 formed as described above will be described with reference to FIG.
First, the semiconductor chip 20 is mounted on the one surface 12a of the carrier substrate 50 by bonding or the like (FIG. 6A).
Next, the electrode 28 provided on the semiconductor chip 20 and the plating film 14 formed on the metal base 12 of the carrier substrate 50 are electrically connected by wires 30 by wire bonding (FIG. 6B). ).
Next, a resin package 22 is formed on the carrier substrate 50 by resin molding in order to seal a connection portion of the semiconductor chip 20 and the wire 30 with a resin (FIG. 6C).
Then, the metal substrate 12 is removed by etching while leaving the plating film 14 of the carrier substrate 50 (FIG. 6D). As a result, the plating film 14 is exposed to the outside of the package and serves as a connection surface for an external connection terminal, thereby completing a semiconductor device having a structure that can be connected to a mounting board. In addition, as a material of the metal base material 12, for example, copper (Cu) is used so that etching is suitably performed.
[0005]
[Problems to be solved by the invention]
However, in the above-described conventional carrier substrate 50, plating is performed only on the concave portion 16 formed by half-etching. However, due to plating characteristics, the area of the concave portion 16 cannot be reduced by a certain amount or more. . This is because, when the recess 16 is finely formed, it is difficult for the plating solution to appropriately flow into the recess 16, and it is difficult to form a predetermined plating layer.
Therefore, there has been a problem that the pitch of the external connection terminals connected to the mounting board of the semiconductor device cannot be reduced to make the semiconductor device smaller.
[0006]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the pitch of external connection terminals in a resin-sealed type leadless surface mount type semiconductor device. It is an object of the present invention to provide a semiconductor device carrier substrate, a method of manufacturing the same, and a method of manufacturing a semiconductor device.
[0007]
[Means for Solving the Problems]
The present invention is Ru with the following configuration to achieve the above object.
[0008]
That is, the method for manufacturing a carrier substrate for a semiconductor device of the present invention comprises a semiconductor chip, a resin package for sealing the semiconductor chip, and a resin protrusion provided on a surface of the resin package connected to the mounting substrate. A semiconductor device carrier substrate used when manufacturing a semiconductor device comprising: a plating film provided on an outer surface of the resin protrusion; and a wire for electrically connecting the electrode of the semiconductor chip and the plating film. In the manufacturing process of the semiconductor device, a plate-shaped metal base on which the semiconductor chip is mounted, and a plating film is formed on the metal base in advance, and then corresponds to the resin protrusion of the metal base. a position, a recess formed by press working, in the method for producing a carrier substrate for a semiconductor device including a said plated film formed on the inner surface of the recess, the gold A plating step of forming a plating film on one surface of the substrate, and pressing the concave portion having the plating film on the inner surface at a position corresponding to the resin protrusion on the surface of the metal substrate on which the plating film is formed. possess a recess forming step of forming, a step of removing the unnecessary plated portions of removing the plating film other than the inner surface of the recess by step removal of the unnecessary plating unit, immerse the metal substrate in a stripping solution of plated Then, the plating film other than the inner surface of the concave portion is removed by utilizing the fact that the plating film in the concave portion is slowly peeled off.
[0009]
Thereby, a suitable carrier substrate for a semiconductor device can be easily manufactured.
[0010]
Also, in the step of removing the unnecessary plating portion, a suitable semiconductor device carrier substrate can be manufactured by mechanically removing a plating film other than the inner surface of the concave portion by grinding or the like.
[0011]
Further, the press working is any one of crushing, drawing, and half-blanking, so that the recess can be suitably formed easily and reliably using existing technology.
[0012]
The present invention also resides in a semiconductor device carrier substrate manufactured by the method for manufacturing a semiconductor device carrier substrate.
[0013]
Further, the present invention, the in manufacturing a semiconductor device by using the carrier substrate for a semiconductor device, wherein a semiconductor chip mounting step of mounting a semiconductor chip on the carrier substrate, an electrode provided on the semiconductor chip metal A wire bonding step of electrically connecting the plating film formed on the inner surface of the concave portion of the base material with a wire, and forming a resin package by sealing the semiconductor chip and the wire mounted on the carrier substrate with a resin; And a metal substrate removing step of removing the metal substrate while leaving the plating film.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a process diagram (cross-sectional view) illustrating an embodiment of a method for manufacturing a carrier substrate for a semiconductor device (hereinafter, referred to as a “carrier substrate”) according to the present invention. 2 and 3 are process diagrams (cross-sectional views) for explaining another embodiment of the press working. FIG. 4 is a process drawing (cross-sectional view) for explaining another embodiment of the method of manufacturing a carrier substrate according to the present invention.
[0015]
(First embodiment)
As shown in FIG. 1C, the carrier substrate 10 manufactured according to the present embodiment is a plate-shaped metal base on which a semiconductor chip is mounted and finally removed in the semiconductor device manufacturing process. After a plating film is formed on the metal substrate 12 in advance, the recesses 16 formed by pressing are formed at positions corresponding to the resin protrusions 24 (see FIG. 6D) of the metal substrate 12. And a plating film 14 formed on the inner surface of the concave portion 16 by being pressed down by the press working.
By using the carrier substrate 10, a semiconductor chip 20, a resin package 22 for sealing the semiconductor chip 20, and a resin protrusion 24 protrudingly provided on the surface of the resin package 22 on the side connected to the mounting substrate A semiconductor device (see FIG. 6D) including a plating film 14 provided on the outer surface of the resin protrusion 24 and wires 30 for electrically connecting the electrode 28 of the semiconductor chip and the plating film 14 is preferable. Can be manufactured.
[0016]
Next, a first embodiment of a method of manufacturing a carrier substrate according to the present invention will be described in order of steps with reference to FIG.
First, FIG. 1A shows a plating step. In this step, one surface 12 a of the metal base 12 is subjected to electrolytic plating to form a plating layer 13 over a plurality of recess 16 forming regions.
It is preferable that the plating layer 13 be formed by plating four layers of gold (Au), palladium (Pd), nickel (Ni), and palladium (Pd) in this order. When the plating film 14 composed of the four plating layers 13 is transferred to the resin protrusion 24 of the semiconductor device, the lowermost gold plating layer of the concave portion 16 is exposed on the surface, and the connection of the external connection terminal is performed. Face. Since this lowermost gold plating layer can be suitably bonded to solder, surface mounting on a circuit board can be suitably performed. Further, since the outermost palladium plating layer of the concave portion 16 can be suitably connected to the gold wire by wire bonding, it can be reliably connected electrically.
Note that a resist may be applied to the back surface 12b of the metal base material 12 and portions that do not require plating so that plating is not performed.
[0017]
Next, FIG. 1B shows a concave portion forming step of forming the concave portion 16, and in this step, the position corresponding to the resin protrusion 24 on the plated surface (one surface 12 a) of the metal base 12. The recess 16 is formed by pressing. In the first embodiment, the recess 16 is formed by crushing, which is one mode of press working.
The recess 16 needs to have a predetermined depth or more in order to properly mount the semiconductor device on the substrate. For example, it is formed to a depth of about 0.1 mm. According to the press working, it can be formed with high accuracy.
Reference numeral 32 denotes a punch of a crushing die.
[0018]
FIG. 1C shows a step of removing the unnecessary plating portion. In this step, the plating film 15 other than the plating film 14 on the inner surface of the concave portion 16 is removed.
In the step of removing the unnecessary plating portion, for example, the entire surface of the concave portion 16 is immersed in a plating stripping solution, and the slow release (dissolution) of the plating film 14 in the concave portion 16 is used. The other plating films 15 may be dissolved and removed.
The reason why the peeling rate (dissolution rate) applied to the plating film 14 in the concave portion 16 is low is that since the concave portion 16 is minutely formed, the speed at which the plating stripping solution flows around is lower than in other regions.
[0019]
Further, by controlling the thickness of the plating to be applied in advance, only the plating (plating film 14) in the concave portion 16 serving as an external connection terminal is left at a suitable thickness, and plating of other unnecessary portions (other plating film) is performed. 15) can be suitably removed.
According to this method, the carrier substrate 10 can be easily manufactured only by immersing the entire carrier substrate 10 in the plating stripping solution and controlling the immersion time.
[0020]
Further, the step of removing the unnecessary plating portion is not limited to the above-described method, and may be a method using a mechanical removal method of mechanically removing the unnecessary plating portion. That is, the plating film 15 other than the inner surface of the concave portion 16 may be removed by grinding or the like. As a mechanical removal method, in addition to the category defined as the above-described grinding, any of processing means defined as cutting or polishing may be used.
Also by this mechanical removal step, if the surface layer is uniformly removed in a planar manner, the plating film 14 in the recess 16 provided one step down remains automatically, so that the carrier substrate 10 can be easily manufactured.
[0021]
Next, another embodiment of the press working will be described.
FIG. 2 is a cross-sectional view showing a step of forming the recess 16 by drawing, which is one mode of press working. 33 is a punch and 34 is a die.
Also by the drawing process, the concave portion 16 provided with the plating film 14 can be suitably formed on the metal base material 12 which has been plated in advance. In addition, by performing the preceding and following steps in the same manner as the step shown in FIG. 1, a carrier substrate can be suitably formed.
FIG. 3 is a cross-sectional view showing a step of forming the recess 16 by half blanking, which is one mode of press working. 35 is a punch and 36 is a die.
The recess 16 provided with the plating film 14 can be suitably formed of the metal base material 12 which has been plated in advance by the half blanking process. In addition, by performing the preceding and following steps in the same manner as the step shown in FIG. 1, a carrier substrate can be suitably formed.
[0022]
As described above, since the press working is any one of crushing, drawing, and half-blanking, the concave portion 16 can be appropriately formed easily and reliably using the existing technology.
According to the press working, fine working can be suitably performed, the recess 16 can be formed small, and the pitch thereof can be reduced. Therefore, the pitch of the plating film 14 provided on the resin protrusion 24 of the semiconductor device can be reduced. Thereby, finally, the semiconductor device can be miniaturized or highly integrated by increasing the number of external connection terminals.
[0023]
(Second embodiment)
Next, a second embodiment of the method of manufacturing a carrier substrate according to the present invention will be described in order of steps with reference to FIG.
First, although not shown, there is a resist coating step of coating the plating resist 38 on both surfaces of the metal base 12.
FIG. 4A shows a resist pattern forming step. In this step, the plating resist 38 at a portion corresponding to the resin protrusion 24 on one surface 12 a of the metal base 12 is removed to form a resist pattern 40. .
[0024]
FIG. 4B shows a step of providing a plating portion 14 a on one surface 12 a of the metal base 12 to form the plating film 14. The plated portion 14a is formed through a plating step and a resist stripping step. That is, after plating is performed on a portion of the metal base 12 from which the plating resist 38 has been removed, the resist is peeled off. The plating portion 14a is not formed in a wide area, but is formed in the size of the plating film 14 formed corresponding to the resin protrusion 24.
[0025]
FIG. 4C shows a step of press working. In this step, the inner surface is plated at a position corresponding to the resin protrusion 24 on the surface (one surface 12 a) of the metal base 12 on which the plated portion 14 a is formed. The recess 16 provided with the coating 14 is formed by press working. In this embodiment, the recess 16 is formed by drawing.
If the carrier substrate is formed in this manner, only the portion where the concave portion 16 is to be formed needs to be plated, so that there is less plating that is peeled off and wasted, and it is possible to manufacture efficiently.
In addition, as described above, in addition to the drawing process, the pressing process includes a crushing process or a half blanking process, and any one of the working methods may be selectively used.
[0026]
According to the above embodiment, after the metal base 12 is plated in advance, the recess 16 is formed by press working. For this reason, compared with the case where plating is performed on the concave portion formed by the conventional half etching described above, even a small plating film 14 can be suitably formed.
Therefore, when the plating film 14 is exposed on the surface in a state transferred to the resin protrusion 24 of the semiconductor device to become an external connection terminal, the external connection terminal can be reduced in size. Thus, when a large number of external connection terminals are arranged in parallel, the pitch between the external connection terminals can be reduced, and the semiconductor device can be downsized.
Further, since the carrier substrate 10 can be efficiently formed by a simple process by press working, the cost can be reduced.
[0027]
Subsequent to the manufacture of the carrier substrate 10 described above, chip attachment (semiconductor chip mounting) for attaching the semiconductor chip 20 on the carrier substrate 10, wire bonding, molding (resin molding) in the same manner as the process shown in FIG. By performing the step of removing the metal base 12 by etching, a semiconductor device can be manufactured.
Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the embodiments, and it is needless to say that many modifications can be made without departing from the spirit of the invention. .
[0028]
【The invention's effect】
As described above, according to the carrier substrate of the present invention, after the plating film is formed on the metal substrate in advance, the concave portion formed by pressing is formed at the position corresponding to the resin protrusion of the semiconductor device on the metal substrate. And the plating film formed on the inner surface of the concave portion.
According to the carrier substrate in which the recesses are formed by the press working as described above, since the plating process after forming the recesses as in the related art is not performed, it is possible to preferably reduce the pitch of the recesses provided with the plating film. it can.
Therefore, the pitch of the external connection terminals in the semiconductor device formed using the carrier substrate can be reduced, and the semiconductor device can be downsized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional process diagram illustrating one embodiment of a method for manufacturing a carrier substrate for a semiconductor device according to the present invention.
FIG. 2 is a cross-sectional view illustrating an embodiment using drawing as press working.
FIG. 3 is a cross-sectional view illustrating an embodiment using half blanking as press working.
FIG. 4 is a cross-sectional process diagram illustrating another embodiment of the method for manufacturing a carrier substrate for a semiconductor device according to the present invention.
FIG. 5 is a sectional process view illustrating a method for manufacturing a conventional carrier substrate.
FIG. 6 is a sectional process view illustrating a method for manufacturing a semiconductor device using a conventional carrier substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Carrier board 12 Metal substrate 14 Plating film 16 Depression 20 Semiconductor chip 22 Resin package 24 Resin protrusion 28 Electrode 30 Wire

Claims (5)

半導体チップと、該半導体チップを封止する樹脂パッケージと、該樹脂パッケージの実装基板へ接続される側の面に設けられた樹脂突起と、該樹脂突起の外面に設けられためっき被膜と、前記半導体チップの電極と前記めっき被膜とを電気的に接続するワイヤとを具備する半導体装置を製造する際に用いられる半導体装置用キャリア基板であって、前記半導体装置の製造工程で、前記半導体チップが搭載される板状の金属基材と、前記金属基材に予めめっき被膜が形成された後、該金属基材の前記樹脂突起に対応する位置に、プレス加工によって形成された凹部と、前記凹部の内面に形成された前記めっき被膜とを具備する半導体装置用キャリア基板の製造方法において、
前記金属基材の片面にめっき被膜を形成するめっき工程と、
前記金属基材のめっき被膜が形成された面の前記樹脂突起に対応する位置に、内面に前記めっき被膜が形成された前記凹部をプレス加工によって形成する凹部形成工程と、
前記凹部の内面以外のめっき被膜を除去する不要めっき部の除去工程とを有し、前記不要めっき部の除去工程は、前記金属基材をめっきの剥離液に浸けて、前記凹部内の前記めっき被膜の剥離が遅いことを利用して、凹部の内面以外のめっき被膜を除去することを特徴とする半導体装置用キャリア基板の製造方法。 A semiconductor chip, a resin package for encapsulating the semiconductor chip, a resin protrusion provided on a surface of the resin package connected to a mounting substrate, a plating film provided on an outer surface of the resin protrusion, A semiconductor device carrier substrate used when manufacturing a semiconductor device including a wire for electrically connecting an electrode of the semiconductor chip and the plating film , wherein in the semiconductor device manufacturing process, the semiconductor chip is A plate-shaped metal substrate to be mounted, a concave portion formed by press working at a position corresponding to the resin protrusion on the metal substrate after a plating film is previously formed on the metal substrate, and the concave portion A method for manufacturing a carrier substrate for a semiconductor device , comprising: a plating film formed on an inner surface of a semiconductor device.
A plating step of forming a plating film on one side of the metal substrate,
A concave portion forming step of forming the concave portion having the plated film formed on the inner surface thereof by press working at a position corresponding to the resin protrusion on the surface of the metal substrate on which the plated film is formed;
Removing an unnecessary plating portion for removing a plating film other than the inner surface of the concave portion. The removing step of the unnecessary plating portion is performed by immersing the metal base material in a stripping solution for plating to remove the plating in the concave portion. A method of manufacturing a carrier substrate for a semiconductor device, wherein a plating film other than the inner surface of a concave portion is removed by utilizing the slow peeling of the film. 半導体チップと、該半導体チップを封止する樹脂パッケージと、該樹脂パッケージの実装基板へ接続される側の面に設けられた樹脂突起と、該樹脂突起の外面に設けられためっき被膜と、前記半導体チップの電極と前記めっき被膜とを電気的に接続するワイヤとを具備する半導体装置を製造する際に用いられる半導体装置用キャリア基板であって、前記半導体装置の製造工程で、前記半導体チップが搭載される板状の金属基材と、前記金属基材に予めめっき被膜が形成された後、該金属基材の前記樹脂突起に対応する位置に、プレス加工によって形成された凹部と、前記凹部の内面に形成された前記めっき被膜とを具備する半導体装置用キャリア基板の製造方法において、A semiconductor chip, a resin package for encapsulating the semiconductor chip, a resin protrusion provided on a surface of the resin package connected to a mounting substrate, and a plating film provided on an outer surface of the resin protrusion; A semiconductor device carrier substrate used when manufacturing a semiconductor device including a wire for electrically connecting an electrode of the semiconductor chip and the plating film, wherein the semiconductor chip is manufactured in a process of manufacturing the semiconductor device. A plate-shaped metal substrate to be mounted, a concave portion formed by press working at a position corresponding to the resin protrusion on the metal substrate after a plating film is formed on the metal substrate in advance, and the concave portion A method for manufacturing a carrier substrate for a semiconductor device, comprising: a plating film formed on an inner surface of a semiconductor device.
前記金属基材の片面にめっき被膜を形成するめっき工程と、  A plating step of forming a plating film on one side of the metal substrate,
前記金属基材のめっき被膜が形成された面の前記樹脂突起に対応する位置に、内面に前記めっき被膜が形成された前記凹部をプレス加工によって形成する凹部形成工程と、  A concave portion forming step of forming the concave portion in which the plating film is formed on the inner surface by press working, at a position corresponding to the resin protrusion on the surface of the metal substrate on which the plating film is formed,
前記凹部の内面以外のめっき被膜を除去する不要めっき部の除去工程とを有し、前記不要めっき部の除去工程は、前記凹部の内面以外のめっき被膜を研削等によって機械的に除去することを特徴とする半導体装置用キャリア基板の製造方法。  A step of removing an unnecessary plating portion for removing a plating film other than the inner surface of the concave portion. A method for manufacturing a carrier substrate for a semiconductor device. 前記プレス加工は、潰し加工、絞り加工、或いは半抜き加工のうちのいずれか一つであることを特徴とする請求項１又は２記載の半導体装置用キャリア基板の製造方法。3. The method according to claim 1 , wherein the pressing is any one of crushing, drawing, and half-blanking. 4. 請求項１〜３のうちのいずれか一項記載の半導体装置用キャリア基板の製造方法によって製造される半導体装置用キャリア基板。A carrier substrate for a semiconductor device manufactured by the method for manufacturing a carrier substrate for a semiconductor device according to claim 1. 請求項４記載の半導体装置用キャリア基板を用いて半導体装置を製造する際に、
前記キャリア基板上に半導体チップを搭載する半導体チップ搭載工程と、
前記半導体チップに設けられた電極と前記金属基材の凹部の内面に形成された前記めっき被膜とをワイヤで電気的に接続するワイヤーボンディング工程と、
前記キャリア基板上に搭載された半導体チップとワイヤを樹脂で封止して樹脂パッケージを形成するモールド成形工程と、
前記めっき被膜を残して前記金属基材を除去する金属基材の除去工程とを有することを特徴とする半導体装置の製造方法。When manufacturing a semiconductor device using the semiconductor device carrier substrate according to claim 4 ,
A semiconductor chip mounting step of mounting a semiconductor chip on the carrier substrate,
A wire bonding step of electrically connecting an electrode provided on the semiconductor chip and the plating film formed on the inner surface of the concave portion of the metal base with a wire,
A molding step of forming a resin package by sealing the semiconductor chip and wires mounted on the carrier substrate with a resin,
Removing the metal substrate while leaving the plating film. A method for manufacturing a semiconductor device, comprising:
JP6379099A 1999-03-10 1999-03-10 Semiconductor device carrier substrate, method of manufacturing the same, and method of manufacturing a semiconductor device Expired - Fee Related JP3569642B2 (en)

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