JP3476224B2 - Method for manufacturing plasma display panel - Google Patents
Method for manufacturing plasma display panelInfo
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- JP3476224B2 JP3476224B2 JP25034593A JP25034593A JP3476224B2 JP 3476224 B2 JP3476224 B2 JP 3476224B2 JP 25034593 A JP25034593 A JP 25034593A JP 25034593 A JP25034593 A JP 25034593A JP 3476224 B2 JP3476224 B2 JP 3476224B2
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- glass
- layer
- glass material
- manufacturing
- plasma display
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Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＡＣ型のプラズマ
ディスプレイパネル（ＰＤＰ）の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an AC type plasma display panel (PDP ) .
【０００２】ＰＤＰは、表示輝度の上で有利な自己発光
型の表示デバイスであり、画面の大型化及び高速表示が
可能であることから、ＣＲＴに代わる表示デバイスとし
て注目されている。特に蛍光体によるカラー表示に適し
た面放電型ＰＤＰは、ハイビジョンを含むテレビジョン
映像の分野にその用途が拡大されつつある。[0002] PDPs are self-luminous display devices that are advantageous in terms of display brightness, and because they are capable of large screens and high-speed display, they have attracted attention as display devices that replace CRTs. In particular, the surface discharge PDP suitable for color display using a phosphor is expanding its application in the field of television images including high definition.
【０００３】[0003]
【従来の技術】図３は一般的な面放電型ＰＤＰの分解斜
視図であり、１つの画素ＥＧに対応する部分の基本的な
構造を示している。2. Description of the Related Art FIG. 3 is an exploded perspective view of a general surface discharge PDP and shows a basic structure of a portion corresponding to one pixel EG.
【０００４】図３に例示したＰＤＰ１０は、蛍光体の配
置形態による分類の上で反射型と呼称される３電極構造
のＰＤＰであり、一対のガラス基板１１，２１、横方向
に互いに平行に隣接して延びた一対の表示電極Ｘ，Ｙ、
壁電荷によって放電を維持するＡＣ駆動のための誘電体
層１７、ＭｇＯからなる保護膜１８、表示電極Ｘ，Ｙと
直交するアドレス電極Ａ、アドレス電極Ａと平行なスト
ライプ状の隔壁２９、及びフルカラー表示のための蛍光
体層２８などから構成されている。The PDP 10 illustrated in FIG. 3 is a PDP having a three-electrode structure, which is called a reflection type in terms of classification according to the arrangement form of the phosphors. A pair of glass substrates 11 and 21 are adjacent to each other in parallel in the lateral direction. A pair of display electrodes X, Y,
A dielectric layer 17 for AC driving that maintains discharge by wall charges, a protective film 18 made of MgO, an address electrode A orthogonal to the display electrodes X and Y, a stripe-shaped partition wall 29 parallel to the address electrode A, and a full color. It is composed of a phosphor layer 28 for display.
【０００５】内部の放電空間３０は、隔壁２９によって
表示電極Ｘ，Ｙの延長方向に単位発光領域ＥＵ毎に区画
され、且つその間隙寸法が規定されている。また、この
放電空間３０には適当な放電ガスが封入されている。The internal discharge space 30 is divided by the barrier ribs 29 in the extending direction of the display electrodes X and Y for each unit light emitting region EU, and the gap dimension thereof is defined. Further, a suitable discharge gas is filled in the discharge space 30.
【０００６】ＰＤＰ１０では、図のように１つの画素
（ドット）ＥＧに対応づけられた３つの単位発光領域Ｅ
Ｕのそれぞれにおいて、一方の表示電極Ｙとアドレス電
極Ａとの交差部に表示又は非表示を選択するための選択
放電セルが画定され、選択放電セルの近傍における表示
電極Ｘ，Ｙの間に主放電セルが画定される。In the PDP 10, as shown in the figure, three unit light emitting areas E associated with one pixel (dot) EG.
In each of U, a selective discharge cell for selecting display or non-display is defined at the intersection of one display electrode Y and the address electrode A, and a main portion is provided between the display electrodes X and Y in the vicinity of the selective discharge cell. A discharge cell is defined.
【０００７】蛍光体層２８は、面放電によるイオン衝撃
を避けるために、表示電極Ｘ，Ｙと反対側のガラス基板
２１上の各隔壁２９の間に設けられ、主放電セルの面放
電で生じる紫外線によって励起されて発光する。蛍光体
層２８の表層面（放電空間と接する面）で発光した光
は、誘電体層１７及びガラス基板１１などを透過して外
部へ射出する。つまり、ＰＤＰ１０では、ガラス基板１
１の外面が表示面Ｈとなる。The phosphor layer 28 is provided between the barrier ribs 29 on the glass substrate 21 on the side opposite to the display electrodes X and Y in order to avoid ion bombardment due to surface discharge, and is generated by surface discharge of the main discharge cells. It emits light when excited by ultraviolet rays. Light emitted on the surface of the phosphor layer 28 (the surface in contact with the discharge space) passes through the dielectric layer 17 and the glass substrate 11 and is emitted to the outside. That is, in the PDP 10, the glass substrate 1
The outer surface of 1 is the display surface H.
【０００８】表示電極Ｘ，Ｙは、蛍光体層２８に対して
表示面Ｈ側に配置されることから、面放電を広範囲とし
且つ表示光の遮光を最小限とするため、幅の広い透明導
電膜４１とその導電性を補うための幅の狭い金属膜（バ
ス電極）４２とから構成されている。透明導電膜４１
は、ＩＴＯ（酸化インジウム）やネサ（酸化錫）などの
酸化金属からなる。また、金属膜４２は、クロム−銅−
クロムの三層構造の薄膜などからなる。Since the display electrodes X and Y are arranged on the display surface H side with respect to the phosphor layer 28, a wide transparent conductive layer is provided in order to widen the surface discharge and minimize the shielding of the display light. It is composed of a film 41 and a narrow metal film (bus electrode) 42 for compensating for its conductivity. Transparent conductive film 41
Is made of a metal oxide such as ITO (indium oxide) or Nesa (tin oxide). Further, the metal film 42 is made of chromium-copper-
It consists of a thin film of a three-layer structure of chromium.
【０００９】さて、誘電体層１７の表層面は、放電特性
の均一化の上で、より平滑であることが望ましい。ただ
し、実際には粗さが２μｍ程度以下であれば表示に支障
はない。Now, it is desirable that the surface of the dielectric layer 17 is smoother in order to make the discharge characteristics uniform. However, actually, if the roughness is about 2 μm or less, there is no problem in the display.
【００１０】従来において、誘電体層１７は、単層構造
のガラス層とされ、例えば軟化点が４７０℃程度の低融
点鉛ガラス（ＰｂＯの組成比が７５％程度）を、軟化点
より十分に高い６００℃程度の温度で焼成することによ
って形成されていた。Conventionally, the dielectric layer 17 is a glass layer having a single layer structure. For example, a low melting point lead glass (having a PbO composition ratio of about 75%) having a softening point of about 470 ° C. can be sufficiently used from the softening point. It was formed by firing at a high temperature of about 600 ° C.
【００１１】[0011]
【発明が解決しようとする課題】軟化点より十分に高い
温度で焼成すれば、焼成に際してガラス材料が流動する
ことから、表層面の平坦なガラス層を得ることができ
る。しかし、そのようなガラス層では、焼成中にガラス
材料が特に表示電極Ｘ，Ｙと活発に反応し、層内に比較
的に大きな気泡が生じ易いという問題があった。If the glass material is baked at a temperature sufficiently higher than the softening point, the glass material flows during the baking, so that a glass layer having a flat surface can be obtained. However, in such a glass layer, there is a problem that the glass material particularly actively reacts with the display electrodes X and Y during firing, and relatively large bubbles are easily generated in the layer.
【００１２】このような気泡が誘電体層１７内に生じる
と、特に面放電型ＰＤＰにおいて、面放電を担う表示電
極Ｘ，Ｙと選択放電のためのアドレス電極Ａとの間で、
耐圧の低下に起因する不要の放電が生じ、表示が乱れる
とともに、アドレス電極Ａや駆動回路が破損するおそれ
がある。つまり、気泡が絶縁破壊を誘発する層欠陥とな
る。When such bubbles are generated in the dielectric layer 17, especially in the surface discharge type PDP, between the display electrodes X and Y which are responsible for the surface discharge and the address electrode A for the selective discharge.
There is a risk that unnecessary discharge will occur due to the decrease in breakdown voltage, display will be disturbed, and the address electrodes A and the drive circuit will be damaged. That is, the bubbles become layer defects that induce dielectric breakdown.
【００１３】本発明は、上述の問題に鑑み、耐圧の低下
を招く気泡の発生を抑えて誘電体層の均質化を図り、表
示動作の信頼性を高めることを目的としている。In view of the above problems, it is an object of the present invention to suppress the generation of bubbles causing a decrease in breakdown voltage, to homogenize the dielectric layer, and to improve the reliability of the display operation.
【００１４】請求項１の発明に係るプラズマディスプレ
イパネルの製造方法は、図１に示すように、表示電極
Ｘ，Ｙを放電空間３０に対して被覆する誘電体層１７を
有したＡＣ型のプラズマディスプレイパネル１の製造に
おいて、前記誘電体層１７を、第１のガラス材料をその
軟化点Ｔ１１より低い温度Ｔ２１で焼成してガラス層を
形成し、当該ガラス層上に第２のガラス材料を塗布し、
当該第２のガラス材料をその軟化点Ｔ１２より高い温度
Ｔ２２で焼成することによって形成するものである。The plasma display according to the invention of claim 1
As shown in FIG. 1 , the panel manufacturing method is the same as the method for manufacturing the AC type plasma display panel 1 having a dielectric layer 17 covering the display electrodes X and Y with respect to the discharge space 30. a glass layer by firing the first glass material at a lower temperature T21 than its softening point T11
Forming, applying a second glass material on the glass layer,
The second glass material is heated to a temperature higher than its softening point T12.
It is formed by firing at T22 .
【００１５】請求項２の発明に係るプラズマディスプレ
イパネルの製造方法において、誘電体層１７によって被
覆される表示電極Ｘ，Ｙは、透光性を有した酸化金属膜
４１及びその導電性を補う金属膜４２からなる。請求項
３の発明に係る製造方法は、前記第２のガラス材料を、
前記第１のガラス材料の焼成温度Ｔ２１より低い温度Ｔ
２２で焼成するものである。The plasma display according to the invention of claim 2
In the manufacturing method of the panel, the dielectric layer 17 is used for covering.
The display electrodes X and Y to be covered are composed of a translucent metal oxide film 41 and a metal film 42 which complements the conductivity thereof. A manufacturing method according to the invention of claim 3 is characterized in that the second glass material is
The first baking temperature T21 good Ri low temperature of the glass material T
It is fired at 22 .
【００１６】請求項４の発明に係る製造方法において
は、前記第２のガラス材料の軟化点Ｔ１２が前記第１の
ガラス材料の軟化点Ｔ１１よりも低い。A manufacturing method according to the invention of claim 4At
IsPreviousRecordOf the second glass materialSoftening point T12 is aboveFirst
Glass materialSofteningPoint T11It is low.
【００１７】請求項５の発明に係る製造方法において
は、前記第２のガラス材料の軟化速度が前記第１のガラ
ス材料の軟化速度よりも大きい。A manufacturing method according to the invention of claim 5At
Is the aboveOf the second glass materialSoftening rate is aboveFirst Gala
MaterialIs greater than the softening rate of.
【００１８】[0018]
【作用】一様に塗布した粒界状のガラス材料を熱してガ
ラス層を形成する際に、最高温度である焼成温度を、粘
度が特定値（４．５×１０7 ポアズ）となる軟化点より
も低い温度とすると、焼成中におけるガラス材料の流動
が緩慢であることから、ガラス材料と他の部材（主とし
て表示電極Ｘ，Ｙ）との接触により起こる化学反応が持
続せず、反応による大きな気泡の発生を抑えることがで
きる。ただし、そのガラス層の表層面（上面）は、ガラ
ス粒界の大きさを反映した凹凸面になる。[Function] When the uniformly coated grain-boundary glass material is heated to form the glass layer, the maximum firing temperature is the softening point at which the viscosity reaches a specific value (4.5 × 10 7 poise). When the temperature is lower than the above temperature, the flow of the glass material during firing is slow, so that the chemical reaction caused by the contact between the glass material and other members (mainly the display electrodes X and Y) does not continue, and a large reaction occurs. Generation of bubbles can be suppressed. However, the surface layer surface (upper surface) of the glass layer becomes an uneven surface reflecting the size of the glass grain boundary.
【００１９】一方、軟化点よりも高い温度で焼成する
と、表層面の平坦なガラス層を得ることができる。誘電
体層１７は、このように互いに異なる焼成条件で形成さ
れた下側ガラス層１７Ａと上側ガラス層１７Ｂとからな
る２層構造を有しており、上面が平坦であり且つ全体と
してほぼ均質である。つまり、誘電体層１７において、
下側ガラス層１７Ａは、それ自体が気泡の発生を抑えた
均質な層として形成されるとともに、上面を平坦化する
ための上側ガラス層１７Ｂの形成に際して、ガラス材料
と表示電極Ｘ，Ｙとを隔てて上側ガラス層１７Ｂ内での
気泡の発生を抑える。On the other hand, if the glass is fired at a temperature higher than the softening point, a glass layer having a flat surface can be obtained. The dielectric layer 17 has a two-layer structure composed of the lower glass layer 17A and the upper glass layer 17B formed under different firing conditions as described above, and has a flat upper surface and is substantially homogeneous as a whole. is there. That is, in the dielectric layer 17,
The lower glass layer 17A itself is formed as a homogeneous layer in which generation of bubbles is suppressed, and at the time of forming the upper glass layer 17B for flattening the upper surface, the glass material and the display electrodes X and Y are combined. The separation suppresses the generation of bubbles in the upper glass layer 17B.
【００２０】[0020]
【実施例】図１は本発明に係るＰＤＰ１の要部の構成を
示す断面図である。ＰＤＰ１は、マトリクス表示の単位
発光領域に一対の表示電極Ｘ，Ｙとアドレス電極Ａとが
対応する３電極構造を有し、蛍光体の配置形態による分
類の上で反射型と呼称される面放電型ＰＤＰである。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing the structure of the main part of a PDP 1 according to the present invention. The PDP 1 has a three-electrode structure in which a pair of display electrodes X and Y and an address electrode A correspond to each other in a unit light emitting region of matrix display, and is a surface discharge called a reflection type in terms of classification according to the arrangement form of phosphors. Type PDP.
【００２１】面放電のための表示電極Ｘ，Ｙは、表示面
Ｈ側のガラス基板１１上に設けられ、ＡＣ駆動用の誘電
体層１７によって放電空間３０に対して被覆されてい
る。誘電体層１７の厚さは２０〜３０μｍ程度である。
誘電体層１７の表面には、保護膜として数千Å程度の厚
さのＭｇＯ膜１８が設けられている。The display electrodes X and Y for surface discharge are provided on the glass substrate 11 on the display surface H side, and are covered in the discharge space 30 by a dielectric layer 17 for AC driving. The thickness of the dielectric layer 17 is about 20 to 30 μm.
On the surface of the dielectric layer 17, a MgO film 18 having a thickness of about several thousand Å is provided as a protective film.
【００２２】表示電極Ｘ，Ｙは、放電空間３０に対して
表示面Ｈ側に配置されることから、面放電を広範囲とす
るための幅の広い帯状の透明導電膜４１と、その導電性
を補うために外端側に重ねられた幅の狭いバス金属膜４
２とから構成されている。透明導電膜４１は数千Å〜１
μｍ程度の厚さのＩＴＯ膜（酸化インジウム膜）又はネ
サ膜（酸化錫膜）からなり、バス金属膜４２は例えばク
ロム−銅−クロムの３層構造の薄膜からなる。Since the display electrodes X and Y are disposed on the display surface H side with respect to the discharge space 30, a wide band-shaped transparent conductive film 41 for widening the surface discharge and its conductivity are provided. Narrow-width bus metal film 4 stacked on the outer edge side to compensate
2 and. The transparent conductive film 41 is several thousand Å to 1
The ITO film (indium oxide film) or the NES film (tin oxide film) having a thickness of about μm is used, and the bus metal film 42 is formed of, for example, a thin film having a three-layer structure of chromium-copper-chrome.
【００２３】一方、単位発光領域を選択的に発光させる
ためのアドレス電極Ａは、背面側のガラス基板２１上
に、表示電極Ｘ，Ｙと直交するように配列されている。
なお、ガラス基板２１には、アドレス電極Ａの上面を含
めて背面側の内面を被覆するように、所定発光色の蛍光
体２８が設けられている。蛍光体２８は、面放電時に放
電空間３０内の放電ガスが放つ紫外線によって励起され
て発光する。On the other hand, the address electrode A for selectively emitting light in the unit light emitting region is arranged on the rear glass substrate 21 so as to be orthogonal to the display electrodes X and Y.
The glass substrate 21 is provided with a phosphor 28 of a predetermined emission color so as to cover the inner surface on the back side including the upper surface of the address electrode A. The phosphor 28 is excited by the ultraviolet rays emitted by the discharge gas in the discharge space 30 during surface discharge to emit light.
【００２４】ＰＤＰ１において、図３のＰＤＰ１０との
構造上の相違点は、誘電体層１７が２層構造を有してい
る点である。すなわち、誘電体層１７は、層の欠陥とな
る気泡の発生を抑えるための下側ガラス層１７Ａと、表
層面を平坦化するための上側ガラス層１７Ｂとから構成
されている。これにより、誘電体層１７が全体的に欠陥
のない均質な層となっており、表示電極Ｘ，Ｙとアドレ
ス電極Ａとの間で所定の耐圧が確保されている。なお、
各ガラス層１７Ａ，１７Ｂの厚さは同程度に選定されて
いる。The PDP 1 is structurally different from the PDP 10 of FIG. 3 in that the dielectric layer 17 has a two-layer structure. That is, the dielectric layer 17 is composed of a lower glass layer 17A for suppressing the generation of bubbles which are defects in the layer, and an upper glass layer 17B for flattening the surface layer surface. As a result, the dielectric layer 17 is a uniform layer having no defects as a whole, and a predetermined breakdown voltage is secured between the display electrodes X and Y and the address electrode A. In addition,
The thickness of each glass layer 17A, 17B is selected to be approximately the same.
【００２５】以下、誘電体層１７の形成工程を中心にＰ
ＤＰ１の製造方法について図２を参照して説明する。図
２は、下側及び上側のガラス層１７Ａ，Ｂの各材料に係
る焼成温度と表面粗さとの関係、及び下側ガラス層１７
Ａの材料に係る焼成温度と欠陥発生率との関係を示すグ
ラフである。Hereinafter, the process of forming the dielectric layer 17 will be mainly described.
A method of manufacturing DP1 will be described with reference to FIG. FIG. 2 shows the relationship between the firing temperature and the surface roughness of each material of the lower and upper glass layers 17A and 17B, and the lower glass layer 17
4 is a graph showing the relationship between the firing temperature and the defect occurrence rate for the material A.
【００２６】ＰＤＰ１は、各ガラス基板１１，２１につ
いて別個に所定の構成要素を設け、その後にガラス基板
１１，２１を重ね合わせて封止を行い、内部の排気及び
放電ガスの充填を行う一連の工程によって製造される。The PDP 1 is provided with a predetermined constituent element separately for each glass substrate 11 and 21, after which the glass substrates 11 and 21 are overlapped and sealed, and a series of exhaust and discharge gas filling is performed. Manufactured by the process.
【００２７】ガラス基板１１側の製造に際しては、ま
ず、蒸着やスパッタなどによる成膜、及びフォトリソグ
ラフィ法によるパターニングによって、ガラス基板１１
上に透明導電膜４１とバス金属膜４２とを順に形成して
表示電極Ｘ，Ｙを設ける。なお、ガラス基板１１は、表
面に二酸化珪素膜を設けた３ｍｍ程度の厚さのソーダ石
灰ガラス板からなる。In manufacturing the glass substrate 11 side, first, the glass substrate 11 is formed by film formation by vapor deposition or sputtering, and patterning by photolithography.
A transparent conductive film 41 and a bus metal film 42 are sequentially formed on the display electrodes X and Y. The glass substrate 11 is made of a soda-lime glass plate having a silicon dioxide film on the surface and having a thickness of about 3 mm.
【００２８】次に、表示電極Ｘ，Ｙを被覆するように、
ガラス基板１１の表面に一様に低融点ガラスペーストを
塗布する。このとき、軟化点Ｔ１１が例えば５８０℃程
度の低融点鉛ガラス（ＰｂＯの組成比が６０％程度）を
主成分のガラス材料として含むペーストを用いる。Next, so as to cover the display electrodes X and Y,
The low melting point glass paste is uniformly applied to the surface of the glass substrate 11. At this time, a paste containing a low melting point lead glass (PbO composition ratio of about 60%) having a softening point T11 of about 580 ° C. as a main component glass material is used.
【００２９】そして、乾燥させたペースト層を、軟化点
Ｔ１１より低くガラス材料が若干軟化する程度の温度Ｔ
２１（例えば５５０〜５６０℃）で焼成し、下側ガラス
層１７Ａを形成する。焼成温度Ｔ２１を軟化点Ｔ１１よ
り低く設定することにより、図２において白抜きの三角
で示すように、電極材料との反応による気泡などの欠陥
のない下側ガラス層１７Ａを得ることができる。ただ
し、下側ガラス層１７Ａの表層面は、図２において白丸
で示すように、表面粗さが５〜６μｍの粗い面、すなわ
ちガラス材料の粒界の大きさに依存した凹凸を有する面
となる。Then, the dried paste layer is heated to a temperature T lower than the softening point T11 to such an extent that the glass material is slightly softened.
It is baked at 21 (for example, 550 to 560 ° C.) to form the lower glass layer 17A. By setting the firing temperature T21 lower than the softening point T11, it is possible to obtain the lower glass layer 17A having no defects such as bubbles due to the reaction with the electrode material, as shown by the white triangles in FIG. However, the surface layer surface of the lower glass layer 17A is a rough surface having a surface roughness of 5 to 6 μm, that is, a surface having irregularities depending on the size of the grain boundary of the glass material, as indicated by white circles in FIG. .
【００３０】そこで、続いて下側ガラス層１７Ａの上
に、誘電体層１７を平坦化するための上側ガラス層１７
Ｂが形成される。上側ガラス層１７Ｂの形成に際して
は、軟化点Ｔ１２が例えば４７０℃程度の低融点鉛ガラ
スを主成分のガラス材料として含むペーストを用いる。
つまり、上側ガラス層１７Ｂに比べて軟化点の低い材料
を用いる。そして、そのようなガラスペーストを、軟化
点Ｔ１２より高く且つ下側ガラス層１７Ａの焼成温度Ｔ
２１より低い温度Ｔ２２（例えば５３０℃）で焼成す
る。Then, subsequently, on the lower glass layer 17A, the upper glass layer 17 for flattening the dielectric layer 17 is formed.
B is formed. When forming the upper glass layer 17B, a paste containing a low melting point lead glass having a softening point T12 of, for example, about 470 ° C. as a main component glass material is used.
That is, a material having a lower softening point than that of the upper glass layer 17B is used. Then, the glass paste having such a temperature is higher than the softening point T12 and the firing temperature T of the lower glass layer 17A.
Baking is performed at a temperature T22 (eg, 530 ° C.) lower than 21.
【００３１】焼成温度Ｔ２２を軟化点Ｔ１２より高く設
定することにより、焼成中にガラス材料が流動すること
から、図２において黒丸で示すように表面粗さが１〜２
μｍ程度の平坦な上側ガラス層１７Ｂ（すなわち誘電体
層１７）を得ることができる。また、焼成温度Ｔ２２を
下側ガラス層１７Ａの焼成温度Ｔ２１より低く設定する
ことにより、下側ガラス層１７Ａの変質を防ぐことがで
きる。By setting the firing temperature T22 higher than the softening point T12, the glass material flows during firing, so that the surface roughness is 1 to 2 as indicated by black circles in FIG.
It is possible to obtain a flat upper glass layer 17B having a thickness of about μm (that is, the dielectric layer 17). Further, by setting the firing temperature T22 lower than the firing temperature T21 of the lower glass layer 17A, it is possible to prevent alteration of the lower glass layer 17A.
【００３２】このようにして下側ガラス層１７Ａと上側
ガラス層１７Ｂとを順に形成して誘電体層１７を設けた
後、電子ビーム蒸着などによってＭｇＯ膜１８を設けて
ガラス基板１１側の製造を終える。In this way, the lower glass layer 17A and the upper glass layer 17B are sequentially formed to provide the dielectric layer 17, and then the MgO film 18 is provided by electron beam evaporation or the like to manufacture the glass substrate 11 side. Finish.
【００３３】上述の実施例によれば、上側ガラス層１７
Ｂの材料として、軟化点Ｔ１２が下側ガラス層１７Ａの
軟化点Ｔ１１よりも低いガラス材料を用いたので、上側
ガラス層１７Ｂの焼成時に下側ガラス層１７Ａ内でガス
が発生したとしても、そのガスが上側ガラス層１７Ｂを
通って外部へ発散し、上側ガラス層１７Ｂによるガスの
封じ込めが起こらない。According to the embodiment described above, the upper glass layer 17
Since a glass material having a softening point T12 lower than the softening point T11 of the lower glass layer 17A was used as the material of B, even if gas was generated in the lower glass layer 17A during firing of the upper glass layer 17B, The gas diffuses to the outside through the upper glass layer 17B, and the gas is not confined by the upper glass layer 17B.
【００３４】なお、上側ガラス層１７Ｂの材料として、
軟化速度が下側ガラス層１７Ａよりも大きいガラス材料
を用いた場合にも、上側ガラス層１７Ｂの焼成に際し
て、上側ガラス層１７Ｂを下側ガラス層１７Ａに比べて
柔らかい状態とすることができるので、同様に上側ガラ
ス層１７Ｂによるガスの封じ込めを防止できる。As a material for the upper glass layer 17B,
Even when a glass material having a softening rate larger than that of the lower glass layer 17A is used, the upper glass layer 17B can be softer than the lower glass layer 17A when firing the upper glass layer 17B. Similarly, the containment of gas by the upper glass layer 17B can be prevented.
【００３５】上述の実施例において、各ガラス層１７
Ａ，１７Ｂの材料、互いの厚さの比率、及び焼成条件
（温度プロファイル）などは、ガラス基板材料・基板表
面コート材料・透明導電膜４１の材料、・バス金属膜の
材料に応じて、均質且つ上面の平坦な誘電体層１７が得
られるように適宜変更することができる。In the above embodiment, each glass layer 17
The materials of A and 17B, the thickness ratio of each other, the firing conditions (temperature profile), etc. are uniform according to the glass substrate material, the substrate surface coating material, the transparent conductive film 41 material, and the bus metal film material. Moreover, it can be appropriately changed so as to obtain the dielectric layer 17 having a flat upper surface.
【００３６】[0036]
【発明の効果】本発明によれば、誘電体層の均質化を図
り、所定の耐圧を確保して表示動作の信頼性を高めるこ
とができる。According to the present invention, the dielectric layer can be homogenized, a predetermined breakdown voltage can be secured, and the reliability of the display operation can be improved.
【図１】本発明に係るＰＤＰの要部の構成を示す断面図
である。FIG. 1 is a sectional view showing a configuration of a main part of a PDP according to the present invention.
【図２】焼成温度と表面粗さとの関係、及び焼成温度と
欠陥発生率との関係を示すグラフである。FIG. 2 is a graph showing the relationship between the firing temperature and the surface roughness, and the relationship between the firing temperature and the defect occurrence rate.
【図３】一般的な面放電型ＰＤＰの分解斜視図である。FIG. 3 is an exploded perspective view of a general surface discharge PDP.
１ ＰＤＰ（プラズマディスプレイパネル） １７ 誘電体層 １７Ａ 下側ガラス層 １７Ｂ 上側ガラス層 ３０ 放電空間 ４１ 透明導電膜（酸化金属膜） ４２ バス金属膜（金属膜） Ｔ１１，Ｔ１２ 軟化点 Ｔ２１，Ｔ２２ 焼成温度 Ｘ，Ｙ 表示電極 1 PDP (plasma display panel) 17 Dielectric layer 17A lower glass layer 17B Upper glass layer 30 discharge space 41 Transparent conductive film (metal oxide film) 42 Bus metal film (metal film) T11, T12 Softening point T21, T22 firing temperature X, Y display electrode
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−123635（ＪＰ，Ａ) 特開 平５−41167（ＪＰ，Ａ) 特開 平５−151901（ＪＰ，Ａ) 特開 平７−176269（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01J 11/02 H01J 9/02 H01J 9/24 ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-2-123635 (JP, A) JP-A-5-41167 (JP, A) JP-A-5-151901 (JP, A) JP-A-7- 176269 (JP, A) (58) Fields surveyed (Int.Cl. 7 , DB name) H01J 11/02 H01J 9/02 H01J 9/24
Claims (5)
体層を有したＡＣ型のプラズマディスプレイパネルの製
造方法であって、 前記誘電体層を、第１のガラス材料をその軟化点Ｔ１１
より低い温度Ｔ２１で焼成してガラス層を形成し、当該
ガラス層上に第２のガラス材料を塗布し、当該第２のガ
ラス材料をその軟化点Ｔ１２より高い温度Ｔ２２で焼成
することによって形成することを特徴とするプラズマデ
ィスプレイパネルの製造方法。1. A manufacturing the plasma display panel of AC type having a dielectric layer covering against the display electrodes between discharge space
A manufacturing method , wherein the dielectric layer is made of a softening point T11 of the first glass material.
Firing at a lower temperature T21 to form a glass layer,
The second glass material is applied on the glass layer and the second glass material is applied.
Lath material is fired at a temperature T22 higher than its softening point T12
A method for manufacturing a plasma display panel , the method comprising:
を補う金属膜からなる表示電極を放電空間に対して被覆
する誘電体層を有したＡＣ型のプラズマディスプレイパ
ネルの製造方法であって、 前記誘電体層を、第１のガラス材料をその軟化点Ｔ１１
より低い温度Ｔ２１で焼成してガラス層を形成し、当該
ガラス層上に第２のガラス材料を塗布し、当該第２のガ
ラス材料をその軟化点Ｔ１２より高い温度Ｔ２２で焼成
することによって形成することを特徴とするプラズマデ
ィスプレイパネルの製造方法。2. A translucent cover light-a has been oxidized metal Maku及 beauty metal film or Ranaru display electrodes to compensate the conductivity with respect to the discharge space
AC type plasma display device having a dielectric layer
A method of manufacturing a flannel, wherein the dielectric layer is made of a first glass material having a softening point T11.
Firing at a lower temperature T21 to form a glass layer,
The second glass material is applied on the glass layer and the second glass material is applied.
Lath material is fired at a temperature T22 higher than its softening point T12
A method for manufacturing a plasma display panel , the method comprising:
ス材料の焼成温度Ｔ２１より低い温度Ｔ２２で焼成する
請求項１または請求項２記載のプラズマディスプレイパ
ネルの製造方法。3. A pre-Symbol second glass material, wherein the first Gala
Fired at a firing temperature T21 good Ri low temperature T22 of the scan material
The method for manufacturing a plasma display panel according to claim 1 or 2 .
記第１のガラス材料の軟化点Ｔ１１よりも低い請求項１
または請求項２記載のプラズマディスプレイパネルの製
造方法。4. Before SL softening point T11 by remote low claim 1 softening point T12 of the second glass material of the first glass material
Alternatively, the method of manufacturing the plasma display panel according to claim 2 .
１のガラス材料の軟化速度よりも大きい請求項１ないし
請求項３のいずれかに記載のプラズマディスプレイパネ
ルの製造方法。5. The softening rate of the second glass material is the first softening rate .
The softening rate of the glass material of No. 1 is higher than that of Claim 1.
The method for manufacturing a plasma display panel according to claim 3 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25034593A JP3476224B2 (en) | 1993-10-06 | 1993-10-06 | Method for manufacturing plasma display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25034593A JP3476224B2 (en) | 1993-10-06 | 1993-10-06 | Method for manufacturing plasma display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07105855A JPH07105855A (en) | 1995-04-21 |
| JP3476224B2 true JP3476224B2 (en) | 2003-12-10 |
Family
ID=17206538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25034593A Expired - Fee Related JP3476224B2 (en) | 1993-10-06 | 1993-10-06 | Method for manufacturing plasma display panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3476224B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3163563B2 (en) | 1995-08-25 | 2001-05-08 | 富士通株式会社 | Surface discharge type plasma display panel and manufacturing method thereof |
| KR19980065367A (en) | 1996-06-02 | 1998-10-15 | 오평희 | Backlight for LCD |
| KR100480752B1 (en) * | 1997-03-14 | 2005-07-07 | 오리온전기 주식회사 | Multi-electrode plasma display device |
| JPH11180726A (en) * | 1997-03-28 | 1999-07-06 | Asahi Glass Co Ltd | Substrate for plasma display panel and low melting point glass composition |
| JP3739163B2 (en) | 1997-03-31 | 2006-01-25 | 三菱電機株式会社 | Plasma display panel |
| KR100438915B1 (en) * | 2001-12-04 | 2004-07-03 | 엘지전자 주식회사 | Method of Fabricating Back Plate of Plasma Display Panel |
| CN1287407C (en) | 2002-03-06 | 2006-11-29 | 松下电器产业株式会社 | Plasma display |
| CN100524588C (en) | 2003-05-21 | 2009-08-05 | 松下电器产业株式会社 | Plasma display panel and manufacturing method thereof |
-
1993
- 1993-10-06 JP JP25034593A patent/JP3476224B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07105855A (en) | 1995-04-21 |
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