JP3471700B2 - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JP3471700B2 JP3471700B2 JP2000071467A JP2000071467A JP3471700B2 JP 3471700 B2 JP3471700 B2 JP 3471700B2 JP 2000071467 A JP2000071467 A JP 2000071467A JP 2000071467 A JP2000071467 A JP 2000071467A JP 3471700 B2 JP3471700 B2 JP 3471700B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- crystal
- convex portion
- growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Semiconductor Lasers (AREA)
- Led Devices (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Description
【０００１】[0001]
【発明が属する技術分野】本発明は、半導体基材及びそ
の作製方法に関し、特に転位欠陥が生じ易い半導体材料
を用いる場合に有用な構造及び方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method for manufacturing the same, and more particularly to a structure and method useful when a semiconductor material that is prone to dislocation defects is used.
【０００２】[0002]
【従来の技術】ＧａＮ系材料を結晶成長する場合、Ｇａ
Ｎ系材料は格子整合する基板がないためにサファイア、
ＳｉＣ、スピネル、最近ではＳｉなどの格子整合しない
基板を用いている。しかしながら、格子整合しないこと
に起因し作製したＧａＮの膜中には１０10個／ｃｍ2も
の転位が存在している。近年高輝度の発光ダイオード、
半導体レーザーなどが実現されているが、特性向上を図
るためには転位密度の低減が望まれている。2. Description of the Related Art Ga is used for crystal growth of GaN-based materials.
Sapphire, because N-based materials do not have a lattice-matched substrate,
Substrates that are not lattice-matched, such as SiC, spinel, and recently Si, are used. However, as many as 10 10 dislocations / cm 2 are present in the GaN film produced due to the lack of lattice matching. High brightness light emitting diode in recent years,
Although semiconductor lasers and the like have been realized, it is desired to reduce the dislocation density in order to improve the characteristics.
【０００３】[0003]
【発明が解決しようとする課題】この転位密度低減を図
る方法としては、例えばＧａＮ系半導体結晶等を、バッ
ファ層及びＧａＮ基板上に気相成長するにあたり、前記
基板上に部分的なマスクを設けて選択成長する事でラテ
ラル方向の結晶成長を行わせ、転位密度を低減した高品
質な結晶を得る方法が提案されている（例えば特開平１
０−３１２９７１号公報）。As a method for reducing the dislocation density, for example, when vapor-depositing a GaN-based semiconductor crystal on a buffer layer and a GaN substrate, a partial mask is provided on the substrate. A method has been proposed in which crystal growth in the lateral direction is performed by selective selective growth to obtain a high-quality crystal with a reduced dislocation density (see, for example, Japanese Patent Laid-Open No. Hei 1
0-312971).
【０００４】しかしながら上記の方法によれば、マスク
層上にラテラル方向成長された部分において、ラテラル
成長方向にc軸が微小量ながら傾斜するといった問題が
生じ、これにより結晶品質が低下するという新たな問題
が有ることが判明した（MRS1998 Fall 、Meeting 予稿
集G3・1）。これは、Ｘ線ロッキングカーブ測定（ＸＲ
Ｃ）の入射方位依存性を測定（¢スキャン）することで
も確認できる。即ち、ラテラル成長方向からの入射Ｘ線
によるＸ線ロッキングカーブの半値全幅（ＦＷＨＭ）
は、マスク層のストライプ方向からのＸ線によるＦＷＨ
Ｍ値より大きくなっており、C軸の微小傾斜（チルティ
ング）に方位依存性がある事を示している。この事は、
マスク上のラテラル成長の合体部分に新たな欠陥を多数
誘起する可能性を示唆している。However, according to the above method, there is a problem that the c-axis is tilted in the lateral growth direction with a small amount in the portion laterally grown on the mask layer, which causes deterioration of crystal quality. It turned out that there was a problem (MRS1998 Fall, Meeting Proceedings G3.1). This is an X-ray rocking curve measurement (XR
It can also be confirmed by measuring (¢ scan) the incident azimuth dependency of C). That is, the full width at half maximum (FWHM) of the X-ray rocking curve due to incident X-rays from the lateral growth direction
Is the FWH of X-rays from the stripe direction of the mask layer.
It is larger than the M value, indicating that the small tilt (tilting) of the C axis has azimuth dependency. This thing is
This suggests that many new defects may be induced in the merged portion of lateral growth on the mask.
【０００５】また、マスク層材料として汎用されている
ものはＳｉＯ2なのであるが、その上に結晶成長層が積
重されるとＳｉ成分がこの結晶成長層中に移行するとい
う、いわゆるオートドーピング汚染の問題があることも
判明した。さらに、Ａｌを含む半導体材料、例えばＡｌ
ＧａＮをＳｉＯ2マスク層付き基板上に成長させた場
合、マスク層上にも結晶成長し、選択成長自体が効果的
に行えないという問題もあった。Although SiO 2 is commonly used as a mask layer material, when a crystal growth layer is stacked on it, Si component migrates into this crystal growth layer, so-called auto-doping contamination. It turned out that there is a problem. Furthermore, a semiconductor material containing Al, for example, Al
When GaN is grown on the substrate with the SiO 2 mask layer, there is also a problem that the crystal growth also occurs on the mask layer and the selective growth itself cannot be effectively performed.
【０００６】このような問題を解消する試みとして、Ｓ
ｉＣのベース基板上にバッファ層及びＧａＮ層を設けた
基板に対して、ＳｉＣ層にまで至るストライプ溝加工を
施して凸部を形成し、この凸部の上方部に位置すること
になるＧａＮ層から結晶成長させる方法が提案されてい
る（MRS 1998 Fall Meeting予稿集G3．38）。この方
法によればＳｉＯ2マスク層無しで選択成長させる事も
出来、上述のＳｉＯ2マスクを用いることに起因する各
種の問題を解消することが可能となる。As an attempt to solve such a problem, S
A substrate in which a buffer layer and a GaN layer are provided on an iC base substrate is subjected to stripe groove processing up to the SiC layer to form a convex portion, and the GaN layer to be located above the convex portion. Has proposed a method for crystal growth (MRS 1998 Fall Meeting Proceedings G3.38). According to this method, selective growth can be performed without the SiO 2 mask layer, and various problems caused by using the above-mentioned SiO 2 mask can be solved.
【０００７】上記方法は、ベース基板としてサファイア
基板を使用する事ができその方法も開示されている（例
えば、特開平１１−１９１６５９号公報）。しかしなが
ら上記方法では、サファイアベース基板上にバッファ層
材料ならびにＧａＮ系材料を結晶成長させ、一旦成長炉
から取り出し溝加工を施し、その後再び結晶成長を行う
というステップが必要となることから、製造プロセスが
複雑化するという新たな不都合が発生し、作業工程が多
くなりコストがかかるなどの問題を有していた。In the above method, a sapphire substrate can be used as a base substrate, and a method therefor is also disclosed (for example, Japanese Patent Laid-Open No. 11-191659). However, the above method requires the steps of crystal growth of the buffer layer material and the GaN-based material on the sapphire base substrate, once taking out from the growth furnace, performing groove processing, and then performing crystal growth again. There is a problem that a new inconvenience occurs, the number of working steps increases, and the cost increases.
【０００８】またＳｉ基板上にＧａＮ系材料を結晶成長
する試みもなされているが、ＧａＮ系結晶を成長すると
熱膨張係数差に起因した反りやクラックが発生し良質の
結晶成長を行えない問題があった。Attempts have also been made to grow a GaN-based material on a Si substrate, but when a GaN-based crystal is grown, there arises a problem that warpage or cracks are generated due to a difference in thermal expansion coefficient, and good quality crystal growth cannot be performed. there were.
【０００９】さらに、上述したラテラル方向成長技術を
用いる場合、基板からの貫通転位を可及的に低減するに
は非マスク部を細く形成することが効果的なのである
が、前記の反りに起因してフォトリソグラフィが正確に
行えない問題があり細いパターンを基板全面に形成する
事が困難であった。Further, in the case of using the lateral growth technique described above, it is effective to form the non-mask portion in a thin shape in order to reduce threading dislocations from the substrate as much as possible. Therefore, it is difficult to form a thin pattern on the entire surface of the substrate because of the problem that photolithography cannot be performed accurately.
【００１０】従って本発明は上記問題に鑑み、マスク層
を用いる事に起因する種々の問題を回避し、かつ製造工
程の簡略化を図ることを目的としている。また従来困難
であったＡｌＧａＮの選択成長ができない問題を解決す
る事を目的としている。さらにＳｉ基板等を用いた場合
の反りやクラックの発生を押さえることを目的としてい
る。In view of the above problems, it is therefore an object of the present invention to avoid various problems caused by using a mask layer and to simplify the manufacturing process. Another object is to solve the problem that AlGaN cannot be selectively grown, which has been difficult in the past. Furthermore, it is intended to suppress the occurrence of warpage and cracks when using a Si substrate or the like.
【００１１】[0011]
【課題を解決するための手段】本発明の半導体基材は、
基板と、該基板上に気相成長された半導体結晶とからな
る半導体基材であって、半導体結晶は、Ａｌ x Ｇａ 1-x-y
Ｉｎ y Ｎ（０≦ｘ≦１、０≦ｙ≦１）によって決定され
る半導体からなる結晶であり、基板の結晶成長面にはス
トライプ型の凸部を有する凹凸が設けられ、前記結晶成
長面に対する凸部の占有する面積の割合は５０％以下と
され、且つ、該凸部の幅ａは０＜ａ＜１μｍの範囲とさ
れ、前記半導体結晶が、該凸部の上方部から専ら成長し
て凹凸面を覆っている、ことを特徴とするものである。The semiconductor substrate of the present invention comprises:
A semiconductor substrate comprising a substrate and a semiconductor crystal vapor-deposited on the substrate, wherein the semiconductor crystal is Al x Ga 1-xy.
Determined by In y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1)
It is a crystal made of a semiconductor, and the crystal growth surface of the substrate is
The unevenness having a tripe-shaped convex portion is provided, and
The ratio of the area occupied by the convex portion to the long surface is 50% or less
And the width a of the protrusion is in the range of 0 <a <1 μm, and the semiconductor crystal grows exclusively from above the protrusion.
It is characterized in that it covers the uneven surface .
【００１２】上記した如き半導体基材において、基板表
面に対して凸部の占有する面積の割合が、２〜３０％と
することは、転位欠陥を可及的に少なくする観点からは
好ましいものである。In the semiconductor substrate as described above, it is preferable that the ratio of the area occupied by the protrusions to the substrate surface is 2 to 30% from the viewpoint of minimizing dislocation defects. is there.
【００１３】本発明の他の半導体基材は、基板と、該基
板上に気相成長された半導体結晶とからなる半導体基材
であって、半導体結晶は、Ａｌ x Ｇａ 1-x-y Ｉｎ y Ｎ（０
≦ｘ≦１、０≦ｙ≦１）によって決定される半導体から
なる結晶であり、基板の結晶成長面にはストライプ型の
凸部を有する凹凸が設けられ、前記結晶成長面に対する
凸部の占有する面積の割合は５０〜７０％とされ、且
つ、該凸部の幅ａは０＜ａ＜１μｍの範囲とされ、前記
半導体結晶が、該凸部の上方部から専ら成長して凹凸面
を覆っている、ことを特徴とするものである。Another semiconductor substrate of the present invention is a semiconductor substrate comprising a substrate and a semiconductor crystal vapor-deposited on the substrate, wherein the semiconductor crystal is Al x Ga 1-xy In y N. (0
From the semiconductor determined by ≦ x ≦ 1, 0 ≦ y ≦ 1)
And a stripe type on the crystal growth surface of the substrate.
Concavities and convexities having convex portions are provided, with respect to the crystal growth surface.
The ratio of the area occupied by the convex portion is 50 to 70%, and
One, the width a of the convex portion is in the range of 0 <a <1 [mu] m, the
The semiconductor crystal grows exclusively from the upper part of the convex portion to form an uneven surface.
It is characterized by covering the .
【００１４】また本発明のさらに他の半導体基材は、基
板と、該基板上に気相成長された半導体結晶とからなる
半導体基材であって、半導体結晶は、Ａｌ x Ｇａ 1-x-y Ｉ
ｎ y Ｎ（０≦ｘ≦１、０≦ｙ≦１）によって決定される
半導体からなる結晶であり、基板の結晶成長面にはスト
ライプ型の凸部を有する凹凸が設けられ、 該凸部の幅ａ
は、０＜ａ＜１μｍの範囲とされ、且つ、該凸部の幅ａ
が、凹部の幅ｂ以下とされている部分を有することを特
徴とするものである。Still another semiconductor substrate of the present invention is a semiconductor substrate comprising a substrate and a semiconductor crystal vapor-deposited on the substrate, the semiconductor crystal being Al x Ga 1-xy I.
n y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1)
It is a crystal made of semiconductor, and strikes the crystal growth surface of the substrate.
Irregularities having a convex portion of the stripe-type is provided, the width a of the protrusion
Is in the range of 0 <a <1 μm, and the width a of the convex portion is
There are those characterized by having a moiety that is the width b hereinafter recess.
【００１５】[0015]
【作用】本発明は、バッファ層等すら形成していない状
態の基板に対して凹凸面を設けることで、結晶成長当初
から実質的に低転位領域を形成可能なラテラル成長を起
こす素地面を予め提供しておく点に特徴を有する。即
ち、気相成長させた場合、成長初期には基板表面全体で
結晶成長が起こり得るが、やがて凸部の上方部での成長
が優位となり、この結果凹部に原材料が拡散しにくくな
り、ひいては凸部の上方部から専ら成長された層にて上
記の凹凸面が覆われるというものである。この凸部の成
長ではＣ軸と垂直方向のいわゆるラテラル成長が起き、
実質的に低転位領域の形成がマスク層レス（従来のよう
にマスク層を用いることなしに）で達成されることにな
る。しかもこの成長は、基板直上に位置する層（例えば
バッファ層）の結晶成長から行い得るので、その後の成
長工程を連続して行うことができるというメリットがあ
る。According to the present invention, by providing an uneven surface on a substrate in which no buffer layer or the like has been formed, it is possible to preliminarily prepare a ground plane which causes lateral growth capable of forming a low dislocation region from the beginning of crystal growth. It is characterized in that it is provided. That is, in the case of vapor phase growth, crystal growth may occur on the entire surface of the substrate in the initial stage of growth, but eventually the growth above the convex portion becomes dominant, and as a result, the raw material is less likely to diffuse into the concave portion, and eventually the convex portion. The uneven surface is covered with a layer grown exclusively from the upper part of the part. In the growth of this convex portion, so-called lateral growth in the direction perpendicular to the C axis occurs,
The formation of the low dislocation regions is substantially achieved without a mask layer (without using a mask layer as in the conventional case). Moreover, since this growth can be performed from the crystal growth of the layer (for example, the buffer layer) located immediately above the substrate, there is an advantage that the subsequent growth steps can be continuously performed.
【００１６】加えて、請求項１記載の発明にあっては、
前記凸部の幅aを０＜a＜１μmというサブミクロンオー
ダーの範囲とし、且つ、上記基板表面に対して該凸部の
占有する面積を５０％以下としたので、凸部の上方部か
ら専ら成長された層にて上記の凹凸面が覆うまでに必要
とする結晶厚みが薄くて済むことになる。その結果、結
晶が保有する熱膨張応力が低減されて反りの発生を抑え
ることができる。In addition, in the invention according to claim 1,
Since the width a of the convex portion is in the submicron range of 0 <a <1 μm, and the area occupied by the convex portion with respect to the substrate surface is 50% or less, the area above the convex portion is exclusively used. The crystal thickness required to cover the uneven surface with the grown layer can be small. As a result, the thermal expansion stress possessed by the crystal is reduced, and the occurrence of warpage can be suppressed.
【００１７】また、請求項２記載の発明では、上記構成
において基板表面に対して凸部の占有する面積の割合
を、特に２〜３０％とすることで、上記作用に加えて転
位欠陥の承継も最小限に抑制することができる。つま
り、転位線が延伸する可能性のある凸部面積割合を、ラ
テラル成長が達成し得る必要最小限の程度としたので、
その上に成長される結晶に含まれてしまう転位欠陥を極
小値に近づけることができるのである。According to the second aspect of the present invention, in addition to the above-mentioned effects, the dislocation defects are inherited by setting the ratio of the area occupied by the convex portion to the substrate surface in the above structure to 2 to 30%. Can be suppressed to a minimum. In other words, the area ratio of the convex portion where the dislocation line may be stretched is set to the minimum necessary degree that the lateral growth can be achieved.
The dislocation defects contained in the crystal grown on it can be brought close to the minimum value.
【００１８】請求項３記載の発明は、発明の観点を変え
て、結晶厚みを極小にすることを専ら意図して、凸部の
幅aを０＜a＜１μmの範囲とし、且つ、上記基板表面に
対して該凸部の占有する面積割合を５０〜７０％とした
ものである。即ち、凸部の占有面積割合を大きくするこ
とは、凸部の密集度を増加させることに帰着し、そのよ
うな凸部が存在する基板に対して上記のラテラル成長を
生起せしめると、成長開始から短時間で凸部の上方部か
ら専ら成長された層にて凹凸面が覆われ、結果としてよ
り薄くて、而してより反り問題が改善された結晶層が得
られるのである。According to the third aspect of the present invention, the width a of the convex portion is set in the range of 0 <a <1 μm, and the substrate is set to have a width a in the range of 0 <a <1 μm in order to minimize the crystal thickness by changing the viewpoint of the invention. The area ratio occupied by the convex portions with respect to the surface is set to 50 to 70%. That is, increasing the occupied area ratio of the protrusions results in increasing the density of the protrusions, and when the above-mentioned lateral growth is caused on the substrate in which such protrusions exist, the growth starts. Thus, the uneven surface is covered with the layer grown exclusively from the upper part of the convex portion in a short time, and as a result, a crystal layer having a smaller thickness and thus an improved warpage problem can be obtained.
【００１９】請求項４に係る発明は、転位欠陥の極小化
を目指した具体的アプローチの発明であって、例えば凸
部を平行なストライプ状に設ける場合等において、凸部
の幅aが０＜a＜１μmの範囲とされ、且つ、該凸部の幅
ａが前記凹部の幅ｂと同等以下とされている部分を有す
るよう凸部を形成するので、転位線の遮断効のある凹部
が支配的なストライプ形状となり、転位欠陥の承継性が
低く抑ええられて結果的に転位欠陥が抑制されることに
なる。The invention according to claim 4 is an invention of a specific approach aiming at minimization of dislocation defects. For example, when the convex portions are provided in parallel stripes, the width a of the convex portions is 0 < Since the projections are formed so that a <1 μm, and the width a of the projections is equal to or smaller than the width b of the recesses, the recesses having the dislocation line blocking effect are dominant. The stripe shape becomes a typical stripe shape, and the discontinuity of dislocation defects is suppressed to a low level, resulting in the suppression of dislocation defects.
【００２０】[0020]
【発明の実施の態様】以下図面に基いて、本発明の実施
態様につき詳細に説明する。図１（ａ）乃至（ｃ）は本
発明に係る半導体基材の結晶成長状態を説明するための
断面図である。図において、１は基板であり、２は該基
板１上に気相成長された半導体結晶をそれぞれ示してい
る。基板１の結晶成長面には凸部１１及び凹部１２が形
成されており、前記凸部１１の上方部から専ら結晶成長
が行われるよう構成されている。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. 1A to 1C are cross-sectional views for explaining a crystal growth state of a semiconductor substrate according to the present invention. In the figure, 1 is a substrate, and 2 is a semiconductor crystal vapor-deposited on the substrate 1, respectively. A convex portion 11 and a concave portion 12 are formed on the crystal growth surface of the substrate 1, and the crystal growth is performed exclusively from above the convex portion 11.
【００２１】本発明でいう基板とは、各種の半導体結晶
層を成長させるためのベースとなる基板であって、格子
整合のためのバッファ層等も未だ形成されていない状態
のものを言う。このような基板としては、サファイア
（Ｃ面、Ａ面、Ｒ面）、ＳｉＣ（６Ｈ、４Ｈ、３Ｃ）、
ＧａＮ、Ｓｉ、スピネル、ＺｎＯ，ＧａＡｓ，ＮＧＯな
どを用いることができるが、発明の目的に対応するなら
ばこのほかの材料を用いてもよい。またこれら基板から
ｏｆｆしたものを用いてもよい。The substrate referred to in the present invention is a substrate that serves as a base for growing various semiconductor crystal layers, and is in a state where a buffer layer for lattice matching has not been formed yet. Examples of such a substrate include sapphire (C surface, A surface, R surface), SiC (6H, 4H, 3C),
GaN, Si, spinel, ZnO, GaAs, NGO, etc. can be used, but other materials may be used as long as they meet the purpose of the invention. Moreover, you may use what turned off from these substrates.
【００２２】基板1上に成長される半導体結晶としては
種々の半導体材料を用いることができ、Ａｌ x Ｇａ 1-x-y
Ｉｎ y Ｎ（０≦ｘ≦１，０≦ｙ≦１）ではｘ、ｙの組成
比を変化させたＧａＮ、ＡｌＧａＮ、ＩｎＧａＮなどが
例示できる。As the semiconductor crystal grown on the substrate 1, various semiconductor materials can be used. Al x Ga 1-xy
For In y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), GaN, AlGaN , InGaN, and the like having different composition ratios of x and y can be exemplified.
【００２３】中でも、ＡｌＧａＮ等のＡｌを含有する半
導体材料の場合、従来のマスク方式ではＳｉＯ2マスク
層上に成長するという問題があったが、本発明によると
マスクレス化によりかかる問題が解消されるため、従来
できなかったＡｌＧａＮのラテラル成長が可能となり低
転位で高品質な膜の成長が基板直上から可能となる。こ
のため紫外線発光素子等で問題となるＧａＮ層による光
吸収がなくなり応用上特に好適である。In particular, in the case of a semiconductor material containing Al such as AlGaN, the conventional mask method has a problem that it grows on the SiO 2 mask layer, but according to the present invention, such a problem is solved by the maskless method. Therefore, lateral growth of AlGaN, which was not possible conventionally, can be performed, and a high-quality film with low dislocations can be grown directly on the substrate. For this reason, light absorption by the GaN layer, which is a problem in the ultraviolet light emitting element, etc. is eliminated, and it is particularly suitable for application.
【００２４】基板1の結晶成長面に形成される凸部１１
は、その上方部から専ら結晶成長が行われるような形状
とすると有効である。「上方部から専ら結晶成長が行わ
れる」とは、凸部１１の頂点ないし頂面及びその近傍で
の結晶成長が優勢に行い得る状態をいい、成長初期には
凹部での成長が生じてもよいが最終的には凸部１１の結
晶成長が優勢となることを指す。つまり上方部を起点と
したラテラル成長により低転位領域が形成されれば、従
来のマスクを要するＥＬＯと同様の効果がある。これが
本発明ではマスクレスで成長可能である事が特徴であ
る。以下、この点についての説明を、図1に基づいて行
う。Protrusions 11 formed on the crystal growth surface of the substrate 1
Is effective when the crystal is grown exclusively from the upper part. "The crystal growth is performed exclusively from the upper part" means a state in which the crystal growth can be predominantly performed at the apex or the top surface of the convex portion 11 and in the vicinity thereof, even if the growth in the concave portion occurs at the initial stage of the growth. Good, but finally indicates that the crystal growth of the convex portion 11 becomes dominant. That is, if the low dislocation region is formed by the lateral growth starting from the upper part, the same effect as that of the conventional ELO requiring a mask can be obtained. This is a feature of the present invention that maskless growth is possible. Hereinafter, this point will be described with reference to FIG.
【００２５】図１は凸部１１をストライプ状に形成した
ものの横断面図である。本発明にあっては、この凸部１
１の幅ａが、０＜ａ＜１μｍとされる。このように、サ
ブミクロンオーダーに凸部１１の幅ａを抑制するのは、
前述の通り、基板の凹凸面を覆うに要する結晶の厚さを
薄肉化するため、並びに、凸部の基板表面に占める面積
割合と相俟って、転位欠陥を減少させることにある。こ
の観点より、凸部１１の幅ａを１μｍ以上とした場合
は、薄肉化の目的が十分達成できないことから好ましく
ない。従って、幅ａは可及的に細い方が望ましいが、凹
凸加工の作業性を考慮すると細すぎる幅は逆に好ましく
なく、０．１＜ａ＜０．７μｍ程度の範囲で選定するこ
とが望ましい。なお、本発明でいう「凸部の幅」とは一
般的には凸部頂面の幅を指すが、凸部の頂面幅と立ち上
がり基底部の幅が相違する場合等においては、基底部の
幅を指す場合も有る。また、溝深さ（凸部高さｈ）は本
発明の効果が出る範囲内で適宜選べば良い。FIG. 1 is a cross-sectional view of the projection 11 formed in a stripe shape. In the present invention, this convex portion 1
The width a of 1 is 0 <a <1 μm. In this way, suppressing the width a of the convex portion 11 to the submicron order is
As described above, the dislocation defects are reduced in order to reduce the thickness of the crystal required to cover the uneven surface of the substrate and in combination with the area ratio of the convex portion on the substrate surface. From this point of view, it is not preferable to set the width a of the convex portion 11 to 1 μm or more because the purpose of thinning cannot be sufficiently achieved. Therefore, it is desirable that the width a is as narrow as possible, but in consideration of workability of uneven processing, a width that is too thin is not preferable, and it is desirable to select in the range of 0.1 <a <0.7 μm. . The "width of the convex portion" in the present invention generally refers to the width of the convex top surface, but in the case where the width of the convex base portion and the rising base portion are different, Sometimes refers to the width of. Further, the groove depth (height h of the convex portion) may be appropriately selected within the range where the effect of the present invention can be obtained.
【００２６】凸部１１が基板表面に占める面積の割合
は、目的に応じて設定することができる。先ず、半導体
結晶２の厚さを薄くし、しかも低転位化を図るという本
発明の一般的観点からは、凸部が占める面積割合は５０
％以下とされる。サファイア基板からの転位がまっすぐ
伸びる成長モードの場合、凸部の占める面積割合が少な
いほど転位の承継数が減るからである。The ratio of the area occupied by the convex portion 11 on the substrate surface can be set according to the purpose. First, from the general viewpoint of the present invention that the thickness of the semiconductor crystal 2 is made thin and the dislocation is made low, the area ratio of the convex portions is 50.
% Or less. This is because, in the growth mode in which dislocations from the sapphire substrate extend straight, the number of dislocation successions decreases as the area ratio of the protrusions decreases.
【００２７】従って凸部が占める面積割合は少ない方が
好ましく、４０％以下、更には３０％以下とすることが
望ましい。特に３０％以下とした場合は、転位の承継を
極小化するという目的を達成し得る。但し、極端に凸部
が占める面積割合を少なくするとラテラル成長自体が発
生し難くなる、乃至は成長に相当の時間を要してしまう
ことから、２％以上は凸部面積を確保しておくことが望
ましい。ゆえに、転位の承継を極小化するという観点か
らは、凸部が占める面積割合は２〜３０％、望ましくは
４〜２０％とすることが好ましい。Therefore, it is preferable that the area ratio of the convex portions is small, preferably 40% or less, and more preferably 30% or less. Especially when it is 30% or less, the purpose of minimizing the succession of dislocations can be achieved. However, if the area ratio occupied by the convex portions is extremely reduced, it becomes difficult for the lateral growth itself to occur, or since it takes a considerable time for the growth, it is necessary to secure the convex portion area at 2% or more. Is desirable. Therefore, from the viewpoint of minimizing the inheritance of dislocations, the area ratio of the protrusions is preferably 2 to 30%, more preferably 4 to 20%.
【００２８】一方、半導体結晶２の厚さを極小化すると
いう観点からは、凸部が占める面積割合は５０〜７０％
の範囲で選択される。このように凸部の密集度を上げる
ことで、各凸部上方部から始まった結晶成長が互いに合
体する時間を早めることができ、結果として半導体結晶
２の厚さの極小化が目指せるからである。なお、面積割
合が７０％を超えるよう設定すると、転位の遮断効が大
きく減少するため望ましくない。On the other hand, from the viewpoint of minimizing the thickness of the semiconductor crystal 2, the area ratio of the convex portion is 50 to 70%.
The range is selected. By increasing the density of the convex portions in this way, the time for crystal growth starting from the upper portion of each convex portion to coalesce with each other can be shortened, and as a result, the thickness of the semiconductor crystal 2 can be minimized. is there. When the area ratio is set to exceed 70%, the dislocation blocking effect is greatly reduced, which is not desirable.
【００２９】後述するが、凸部１１の望ましい形態とし
て、ストライプ状の凸部がある。このような凸部の場合
は、凸部１１の幅ａと、凹部１２の幅ｂとの関係におい
て凸部の態様を定義できる。即ち、凸部１１の幅ａが、
０＜ａ＜１μｍであることを前提とした上で、該凸部の
幅ａを前記凹部の幅ｂと同等以下とすることによって
も、転位欠陥の極小化を目指すことができる。この場
合、幅ａと幅ｂとの関係は、基板表面全面において厳格
に満たされていることは必ずしも必要でなく、基板表面
の主要部分が少なくともそのように構成されていれば良
い。As will be described later, a desirable form of the protrusion 11 is a stripe-shaped protrusion. In the case of such a convex portion, the aspect of the convex portion can be defined by the relationship between the width a of the convex portion 11 and the width b of the concave portion 12. That is, the width a of the convex portion 11 is
It is also possible to minimize dislocation defects by setting the width a of the convex portion to be equal to or smaller than the width b of the concave portion on the assumption that 0 <a <1 μm. In this case, the relationship between the width a and the width b does not necessarily have to be strictly satisfied on the entire surface of the substrate, and it suffices that at least the main part of the surface of the substrate be configured in such a manner.
【００３０】以下、ストライプ状の凸部の場合につい
て、実施例を説明する。図１(ａ)に示したものは、凸部
の幅が０．５μm、基板表面に占める面積割合が５０％
程度で、凸部高さｈも同程度とした場合を表している。
この場合原料ガスは凹部１２及びその近傍にまで到達し
得るため凹部１２での成長も生じる。また、凸部１１の
上方部からも結晶成長が生じ、図１(ｂ)に示すように、
凸部１１の上方部と凹部１２表面に、それぞれ結晶単位
２０、２１が生成される状態となる。このような状況
下、結晶成長が続くと凸部１１の上方部を起点とし横方
向に成長した膜がつながって、やがて図１(ｃ)のように
基板１の凹凸面を覆うことになる。この場合、凹部１２
上部には低転位領域が形成され、作製した膜の高品質化
が図れている。なおこの時の凹部が覆われ平坦になるま
でに要する厚みは０．５μmであった。An example will be described below in the case of a stripe-shaped convex portion. As shown in FIG. 1A, the width of the convex portion is 0.5 μm and the area ratio on the substrate surface is 50%.
In this case, the height h of the convex portion is the same.
In this case, since the source gas can reach the recess 12 and its vicinity, growth in the recess 12 also occurs. Further, crystal growth also occurs from the upper part of the convex portion 11, and as shown in FIG.
The crystal units 20 and 21 are formed on the upper portion of the convex portion 11 and the surface of the concave portion 12, respectively. Under such a circumstance, if the crystal growth continues, the films grown in the lateral direction from the upper portion of the convex portion 11 as a starting point are connected, and eventually the uneven surface of the substrate 1 is covered as shown in FIG. 1C. In this case, the recess 12
A low-dislocation region is formed in the upper part, and the quality of the manufactured film is improved. The thickness required to cover and flatten the concave portion at this time was 0.5 μm.
【００３１】本発明にあっては、このような凸部１１で
あれば特に制限はなく各種の形状を採用することができ
る。具体的には、上述したような溝幅Ｂに対し溝深さ
（凸部高さ）ｈが深い場合、溝幅Ｂに対し溝深さ（凸部
高さ）ｈが浅い場合、さらに溝幅Ｂに対し溝深さ（凸部
高さ）ｈが非常に浅い場合、もしくは凸部１１の幅Ａに
対し溝幅Ｂが非常に広い場合など種々の組み合わせを行
う事ができる。特に溝幅Ｂに対し溝深さ（凸部高さ）ｈ
が深い場合、気相成長時に原料ガスが実質的に底部まで
拡散できないため原料が効率良く凸部１１上部の成長に
寄与する点で好ましい。また凸部１１の幅Ａに対し溝幅
Ｂが広い場合、横方向成長の領域が多くなり低転位領域
が広く形成される点で好ましい。In the present invention, there is no particular limitation as long as it is such a convex portion 11, and various shapes can be adopted. Specifically, when the groove depth (height of protrusion) h is deeper than the groove width B as described above, and when the groove depth (height of protrusion) h is shallower than the groove width B, the groove width is further increased. Various combinations can be performed, such as when the groove depth (height of the convex portion) h is extremely shallow with respect to B, or when the groove width B is very large relative to the width A of the convex portion 11. Especially for groove width B, groove depth (height of protrusion) h
Is deep, the raw material gas cannot substantially diffuse to the bottom during vapor phase growth, and the raw material contributes to the growth of the upper portion of the convex portion 11 efficiently, which is preferable. Further, it is preferable that the groove width B is wider than the width A of the convex portion 11 in that the region of lateral growth is increased and the low dislocation region is widened.
【００３２】このような凹凸面の形成の態様としては、
島状の点在型の凸部、ストライプ型の凸条からなる凸
部、格子状の凸部、これらを形成する線が曲線である凸
部などが例示できる。これら凸部の態様の中でも、スト
ライプ型の凸条を設ける態様のものは、その作製工程を
簡略化できると共に、規則的なパターンが作製容易であ
る点で好ましい。ストライプの長手方向は任意であって
よいが、基板上に成長させる材料をＧａＮとし、ＧａＮ
系材料の＜１−１００＞方向にした場合｛１−１０１｝
面などの斜めファセットが形成され難いため横方向成長
（ラテラル成長）が早くなる。この結果凹凸面を覆うの
が速くなる点で特に好ましい。As a mode of forming such an uneven surface,
Examples thereof include island-shaped scattered convex portions, convex portions formed of stripe-shaped convex stripes, lattice-shaped convex portions, and convex portions in which the lines forming these are curved lines. Among these aspects of the protrusions, the aspect in which the stripe-shaped protrusions are provided is preferable because the production process can be simplified and a regular pattern can be easily produced. The longitudinal direction of the stripe may be arbitrary, but the material to be grown on the substrate is GaN, and
In the case of the <1-100> direction of the system material {1-101}
Lateral growth is accelerated because it is difficult to form oblique facets such as planes. As a result, it is particularly preferable in that the uneven surface can be covered more quickly.
【００３３】図１に示す実施例のように、空洞部１３を
残したまま基板１の凹凸面を埋め込み、続いてその上に
発光部を成長して発光素子を作製した場合、空洞部と半
導体界面の屈折率差が大きく取れる。この結果発光部下
方に向かった光がこの界面で反射される割合が増える。
例えばＬＥＤを、サファイア基板面を下側にしてダイボ
ンドを行った場合は、上方に取り出せる光量が増えるた
め好ましい。As in the embodiment shown in FIG. 1, when the uneven surface of the substrate 1 is buried with the cavity 13 left, and then the light emitting portion is grown thereon to manufacture a light emitting element, the cavity and the semiconductor are formed. A large difference in refractive index at the interface can be obtained. As a result, the proportion of light traveling downward from the light emitting portion is reflected at this interface.
For example, when the LED is die-bonded with the sapphire substrate surface facing downward, it is preferable because the amount of light that can be extracted upward increases.
【００３４】また空洞部１３を残したまま埋め込む事
は、基板１とその上に成長する半導体層との接触面積を
小さくできるという事であるため、半導体中に格子定数
差や熱膨張係数差に起因する歪を低減できる面で好まし
い。この歪の低減は、サファイア上にＧａＮ系材料を厚
く成長した時に発生する反りを低減させる効果がある。
特に従来法ではＳｉ基板上にＧａＮ系材料を結晶成長す
る際に熱膨張係数差に起因した反りやクラックが発生し
良質の結晶成長を行えない問題があったが、本発明によ
る歪低減によりこの問題を解消できる。Further, since it is possible to reduce the contact area between the substrate 1 and the semiconductor layer grown on the substrate 1 by filling the cavity 13 with the cavity 13 left, it is possible to reduce the difference in lattice constant and difference in thermal expansion coefficient in the semiconductor. It is preferable in that the distortion caused can be reduced. This reduction in strain has the effect of reducing the warpage that occurs when a GaN-based material is grown thick on sapphire.
In particular, in the conventional method, there was a problem that warpage or cracks occurred due to the difference in thermal expansion coefficient during crystal growth of a GaN-based material on a Si substrate, and high quality crystal growth could not be performed. You can solve the problem.
【００３５】さらに基板１とその上に成長する半導体層
２との接触面積を小さくできる事を利用すると、半導体
層２を厚く成長していった場合、この小さい接触部に応
力が集中し、この部分から基板１と半導体層２の分離が
可能となる。これを応用する事でＧａＮなどの基板が作
製可能となる。Further, by utilizing the fact that the contact area between the substrate 1 and the semiconductor layer 2 grown thereon can be made small, when the semiconductor layer 2 is grown thick, stress concentrates on this small contact portion, The substrate 1 and the semiconductor layer 2 can be separated from the portion. By applying this, a substrate such as GaN can be manufactured.
【００３６】以上、基板１の上に半導体層２を一層だけ
成長する場合について説明したが、転位欠陥をより少な
くするために、同様な工程を２回繰り返すようにしても
よい。即ち図２に示すように、上記と同様な手法にて基
板１の凹凸面を覆うように第一の半導体層２ａの結晶成
長を行った後に、該第一の半導体層２ａの表面を凹凸面
とする加工を施し、その上に気相成長により第一半導体
層２ａの凸部の上方部から専ら結晶成長するようにして
第二の半導体結晶２ｂを形成することもできる。この場
合、特に基板１の凸部１１と上記第一の半導体層２ａに
形成する凸部１１ａの位置とを、垂直方向にずらす態様
にすれば、第二の半導体層２ｂには第一の半導体層２ａ
の凸部１１ａ上部にある多くの転位が伝播しないことに
なる。つまり、かかる構成とすれば、第二の半導体層２
ｂ全域を低転位領域とすることができ、より高品質の半
導体層が得られるものである。Although the case where only one semiconductor layer 2 is grown on the substrate 1 has been described above, the same steps may be repeated twice in order to reduce dislocation defects. That is, as shown in FIG. 2, after crystal growth of the first semiconductor layer 2a is performed so as to cover the uneven surface of the substrate 1 by the same method as described above, the surface of the first semiconductor layer 2a is roughened. It is also possible to form the second semiconductor crystal 2b on which the second semiconductor crystal 2b is exclusively grown by crystal growth from above the convex portion of the first semiconductor layer 2a by vapor phase growth. In this case, in particular, if the protrusion 11 of the substrate 1 and the position of the protrusion 11a formed on the first semiconductor layer 2a are vertically displaced, the second semiconductor layer 2b has the first semiconductor layer 2b. Layer 2a
Many dislocations on the upper part of the convex portion 11a do not propagate. That is, with such a configuration, the second semiconductor layer 2
The entire dislocation region b can be a low dislocation region, and a higher quality semiconductor layer can be obtained.
【００３７】また、第二の半導体結晶２ｂの表面をさら
に凹凸面とし、その上に同様に気相成長法により形成さ
れる第３の半導体層を形成するようにしても良い。或い
は、さらに同様の工程を繰り返して、複数の半導体層を
多重的に形成するようにしても良い。このような構成と
すれば、上述したような上下間の凸部の位置調整を意図
的に行わずとも、層を重ねる毎に伝播する転位を漸減さ
せることができる。Further, the surface of the second semiconductor crystal 2b may be made uneven, and a third semiconductor layer similarly formed by the vapor phase growth method may be formed thereon. Alternatively, the same steps may be repeated to form a plurality of semiconductor layers in multiple layers. With such a configuration, it is possible to gradually reduce the dislocation propagating each time the layers are stacked, without intentionally adjusting the positions of the upper and lower convex portions as described above.
【００３８】凸部の形成は、例えば通常のフォトリソグ
ラフイ技術を使って凸部形状に応じてパターン化し、Ｒ
ＩＥ技術等を使ってエッチング加工を行うことで作製で
きる。The protrusions are formed by patterning according to the shape of the protrusions using, for example, an ordinary photolithography technique, and then R
It can be manufactured by etching using IE technology or the like.
【００３９】基板上に半導体層の結晶成長を行う方法は
ＨＶＰＥ、ＭＯＣＶＤ、ＭＢＥ法などがよい。厚膜を作
製する場合はＨＶＰＥ法が好ましいが、薄膜を形成する
場合はＭＯＣＶＤ法が好ましい。As a method for growing a crystal of a semiconductor layer on a substrate, HVPE, MOCVD, MBE method or the like is preferable. The HVPE method is preferable when forming a thick film, but the MOCVD method is preferable when forming a thin film.
【００４０】基板上に半導体層の結晶成長を行う時の成
長条件（ガス種、成長圧力、成長温度、など）は、本発
明の効果が出る範囲内であれば、目的に応じ使い分けれ
ばよい。The growth conditions (gas species, growth pressure, growth temperature, etc.) for crystal growth of the semiconductor layer on the substrate may be properly selected according to the purpose as long as the effects of the present invention can be obtained. .
【００４１】[0041]
【実施例】［実施例1］ｃ面サファイア基板上にフォト
レジストのパターニング（幅：０．３μｍ、周期：４μ
ｍ、ストライプ方位：ストライプ延伸方向がサファイア
基板の＜１１−２０＞方向）を行い、ＲＩＥ（Reactive
Ion Etching）装置で３μｍの深さまで断面方形型にエ
ッチングした。フォトレジストを除去後、ＭＯＶＰＥ装
置に基板を装着した。その後、水素雰囲気下で１１００
℃まで昇温し、サーマルエッチングを行った。その後温
度を５００℃まで下げ、３族原料としてトリメチルガリ
ウム（以下ＴＭＧ）を、Ｎ原料としてアンモニアを流
し、ＧａＮ低温バッファー層を成長した。つづいて温度
を１０００℃に昇温し原料としてＴＭＧ・アンモニア
を、ドーパントとしてシランを流しｎ型ＧａＮ層を成長
した。その時の成長時間は、通常の凹凸の施していない
場合のＧａＮ成長における４μｍに相当する時間とし
た。[Example] [Example 1] Photoresist patterning on a c-plane sapphire substrate (width: 0.3 µm, period: 4 µm)
m, stripe azimuth: stripe stretching direction is <11-20> direction of sapphire substrate, and RIE (Reactive
Ion Etching) apparatus was used to etch a rectangular cross-section to a depth of 3 μm. After removing the photoresist, the substrate was mounted on the MOVPE device. After that, 1100 under hydrogen atmosphere
The temperature was raised to ° C and thermal etching was performed. After that, the temperature was lowered to 500 ° C., trimethylgallium (hereinafter referred to as TMG) as a Group 3 raw material and ammonia as a N raw material were caused to flow to grow a GaN low temperature buffer layer. Subsequently, the temperature was raised to 1000 ° C. and TMG / ammonia as a raw material and silane as a dopant were flown to grow an n-type GaN layer. The growth time at that time was set to a time corresponding to 4 μm in the GaN growth in the case where the usual unevenness is not applied.
【００４２】成長後の断面を観察すると基板凹部に成長
は生じているが、図１(ｃ)に示すように凹部に空洞部１
３を残したまま凹凸部を覆い、平坦になったＧａＮ膜が
得られた。この膜の上にＩｎＧａＮ（ＩｎＮ混晶比＝
０．２、１００ｎｍ厚）を続けて成長して現れるピット
（転位に対応している）をカウントして転位密度の評価
を行ったところ２×１０6cm-3と転位密度が通常報告例
に比べ低減していた。When the cross section after the growth is observed, the growth occurs in the concave portion of the substrate, but as shown in FIG. 1 (c), the hollow portion 1 is formed in the concave portion.
A flat GaN film was obtained by covering the concave and convex portion while leaving 3 remaining. InGaN (InN mixed crystal ratio =
When the pits (corresponding to dislocations) appearing after continuous growth of 0.2 and 100 nm thickness were counted and the dislocation density was evaluated, the dislocation density was 2 × 10 6 cm −3, which is a commonly reported example. It was reduced compared to.
【００４３】比較のために、通常のｃ面サファイア基板
上に同じ成長条件でＧａＮ層、更にＩｎＧａＮ層を成膜
し評価を行なった。結果は２×１０9cm-3と通常報告例
と同程度であり実施例−１に比べ非常に多い数であっ
た。For comparison, a GaN layer and an InGaN layer were formed on a normal c-plane sapphire substrate under the same growth conditions and evaluated. The result was 2 × 10 9 cm −3, which was almost the same as that of the normally reported example, which was a very large number compared with Example-1.
【００４４】通常のＥＬＯ法により実施例−１との比較
を行なう事を試みた。まずサファイア基板上にバッファ
ー層を介しＧａＮ層を１．５μm形成した。その後Ｓｉ
Ｏ2膜をリフトオフにより形成するためのレジストを塗
布し、露光を試みた。ところがウエハーの中心部は０．
５μmのストライプが形成されるものの、ウエハー周辺
部ではパターンが形成されなかった。これはウエハーの
反りに起因しマスクとウエハーの距離が面内で変動して
いるためであることがわかった。このため０．３μmの
パターン形成は断念した。An attempt was made to compare with Example-1 by the usual ELO method. First, a GaN layer having a thickness of 1.5 μm was formed on a sapphire substrate via a buffer layer. Then Si
A resist for forming an O 2 film by lift-off was applied and exposure was attempted. However, the central part of the wafer is 0.
Although a 5 μm stripe was formed, no pattern was formed in the peripheral portion of the wafer. It has been found that this is because the distance between the mask and the wafer fluctuates in the plane due to the warp of the wafer. Therefore, the pattern formation of 0.3 μm was abandoned.
【００４５】［実施例２］実施例１で得られた膜に連続
してｎ型ＡｌＧａＮクラッド層、ＩｎＧａＮ発光層、ｐ
型ＡｌＧａＮクラッド層、ｐ型ＧａＮコンタクト層を順
に形成し、発光波長３７０ｎｍの紫外ＬＥＤウエハーを
作製した。その後、電極形成、素子分離を行い、ＬＥＤ
素子とした。ウェハ全体で採取されたＬＥＤチップの出
力の平均値と逆電流特性を評価した。比較対象として
は、通常のサファイア基板を使って上記構造を作製した
紫外ＬＥＤチップである。これらの評価結果を表１に示
す。[Example 2] An n-type AlGaN clad layer, an InGaN light emitting layer, and a p layer were formed in succession to the film obtained in Example 1.
-Type AlGaN clad layer and p-type GaN contact layer were sequentially formed to produce an ultraviolet LED wafer having an emission wavelength of 370 nm. After that, electrodes are formed and elements are separated, and the LED
The element. The average value of the output of the LED chips collected on the entire wafer and the reverse current characteristic were evaluated. The comparison target is an ultraviolet LED chip in which the above structure is manufactured using a normal sapphire substrate. The results of these evaluations are shown in Table 1.
【００４６】[0046]
【表１】 [Table 1]
【００４７】表２に示すように本発明を用い作製したサ
ンプルでは従来例に比べ出力が高く、リーク電流の少な
い高品質のＬＥＤが作製できる事がわかった。As shown in Table 2, it was found that the sample manufactured by using the present invention can manufacture a high-quality LED with higher output and less leak current than the conventional example.
【００４８】［実施例３］実施例1で作製したＧａＮ結
晶を第一結晶とし、その上に第二結晶を成長させた。ま
ずＧａＮ第一結晶にフォトレジストのパターニング
（幅：２μｍ、周期：４μｍ、ストライプ方位：ＧａＮ
基板の＜１−１００＞）を行い、ＲＩＥ装置で２μｍの
深さまで断面方形型にエッチングした。この時のパター
ニングは基板凸部の上に第一結晶の凹部がくるような配
置とした。この時のアスペクト比は1であった。フォト
レジストを除去後、MOVPE装置に基板を装着した。その
後、窒素、水素、アンモニア混合雰囲気下で１０００℃
まで昇温した。その後、原料としてＴＭＧ・アンモニア
を、ドーパントとしてシランを流しｎ型ＧａＮ層を成長
した。その時の成長時間は、通常の凹凸の施していない
場合のＧａＮ成長における４μｍに相当する時間とし
た。[Example 3] The GaN crystal prepared in Example 1 was used as a first crystal, and a second crystal was grown thereon. First, patterning a photoresist on the GaN first crystal (width: 2 μm, period: 4 μm, stripe orientation: GaN
<1-100>) of the substrate was performed, and the substrate was etched in a rectangular cross-section to a depth of 2 μm with an RIE apparatus. The patterning at this time was arranged so that the concave portion of the first crystal was located on the convex portion of the substrate. The aspect ratio at this time was 1. After removing the photoresist, the substrate was mounted on a MOVPE device. After that, 1000 ° C in a mixed atmosphere of nitrogen, hydrogen and ammonia
The temperature was raised to. After that, TMG / ammonia as a raw material and silane as a dopant were flown to grow an n-type GaN layer. The growth time at that time was set to a time corresponding to 4 μm in the GaN growth in the case where the usual unevenness is not applied.
【００４９】成長後の断面を観察すると基板凹部への成
長、凸部側面への成長が見られるものの、図２に示すよ
うに空洞部を残したまま凹凸部を覆い、平坦になったＧ
ａＮ膜が得られた。続いて得られた膜のピットの評価を
行ったところ２×１０5cm-3にピットが減少している事
がわかった。このように本実施例を繰り返す事により更
なる転位密度低減効果があることが確認できた。When the cross section after the growth is observed, the growth on the concave portion of the substrate and the growth on the side surface of the convex portion are observed, but as shown in FIG.
An aN film was obtained. When the pits of the obtained film were evaluated subsequently, it was found that the pits were reduced to 2 × 10 5 cm -3 . Thus, it was confirmed that the effect of further reducing the dislocation density was obtained by repeating this example.
【００５０】[0050]
【発明の効果】以上説明した通りの本発明の半導体基材
及びその作製方法によれば、基板に対して凸部を設けて
おくことで、マスク層を使用することなく低転位領域を
形成可能なラテラル成長を行わせることができる。従っ
てマスク層を形成することに起因する問題点である軸の
微小チルティングによるラテラル成長部の合体部分の新
たな欠陥の発生の問題やオートドーピングの問題、Al含
有半導体材料が選択成長不可という問題を解消できる。
また、基板に凹凸面を設けた後に、一回の成長でバッ
ファ層成長から発光部等の半導体結晶層の成長を連続し
て行えるので、製造プロセスの簡略化が図れるという利
点がある。また貫通転位のもととなる凸部の幅、面積を
規定することで低転位密度領域を相対的に広くしたり、
凹凸を覆い平坦化するのに用する厚みを薄くできる利点
がある。さらに空洞部の利用による反射率向上や、残留
歪の現象などの効果もあり特性向上、低コスト化の面か
ら非常に価値のある発明である。As described above, according to the semiconductor substrate and the method of manufacturing the same of the present invention, the low dislocation region can be formed without using the mask layer by providing the convex portion on the substrate. Lateral growth can be performed. Therefore, the problem caused by the formation of the mask layer is the problem of the generation of new defects in the merged portion of the lateral growth portion due to the minute tilting of the axis, the problem of autodoping, and the problem that the Al-containing semiconductor material cannot be selectively grown. Can be resolved.
Further, after providing the uneven surface on the substrate, the growth of the buffer layer and the growth of the semiconductor crystal layer such as the light emitting portion can be continuously performed by one growth, which is advantageous in that the manufacturing process can be simplified. In addition, by defining the width and area of the convex portion that is the source of threading dislocations, the low dislocation density region can be made relatively wide,
There is an advantage that the thickness used for covering the unevenness and flattening can be reduced. Further, it is an extremely valuable invention from the viewpoints of improving the characteristics and reducing the cost due to the effect of improving the reflectance and the phenomenon of residual strain by utilizing the cavity.
【図１】本発明に係わる半導体基材の結晶成長状態を説
明するための断面図である。FIG. 1 is a cross-sectional view for explaining a crystal growth state of a semiconductor substrate according to the present invention.
【図２】本発明に係わる半導体基材の結晶成長状態を説
明するための断面図である。FIG. 2 is a cross-sectional view for explaining a crystal growth state of a semiconductor substrate according to the present invention.
１ 基板 １１ 凸部 １２ 凹部 １３ 空洞部 ２ 半導体層 1 substrate 11 convex 12 recess 13 Cavity 2 semiconductor layers
───────────────────────────────────────────────────── フロントページの続き (72)発明者 湖東 雅弘 兵庫県伊丹市池尻４丁目３番地 三菱電 線工業株式会社伊丹製作所内 (56)参考文献 特開2000−106455（ＪＰ，Ａ) 特開2000−156524（ＪＰ，Ａ) 特表2003−511871（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/205 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Masahiro Koto, 4-3 Ikejiri, Itami City, Itami City, Hyogo Prefecture (56) References JP-A 2000-106455 (JP, A) JP 2000 -156524 (JP, A) Special Table 2003-511871 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/205
Claims (4)
体結晶とからなる半導体基材であって、半導体結晶は、Ａｌ x Ｇａ 1-x-y Ｉｎ y Ｎ（０≦ｘ≦１、
０≦ｙ≦１）によって決定される半導体からなる結晶で
あり、 基板の結晶成長面にはストライプ型の凸部を有する凹凸
が設けられ、前記結晶成長面に対する凸部の占有する面
積の割合は５０％以下とされ、且つ、該凸部 の幅ａは０
＜ａ＜１μｍの範囲とされ、前記半導体結晶が、該凸部の上方部から専ら成長して凹
凸面を覆っている、 半導体基材。1. A semiconductor substrate comprising a substrate and a semiconductor crystal vapor-deposited on the substrate, wherein the semiconductor crystal is Al x Ga 1-xy In y N (0 ≦ x ≦ 1,
A crystal made of a semiconductor determined by 0 ≦ y ≦ 1)
Yes, the crystal growth surface of the substrate is uneven with stripe-shaped protrusions.
A surface occupied by the convex portion with respect to the crystal growth surface
The ratio of the product is 50% or less, and the width a of the convex portion is 0.
<A <1 μm, and the semiconductor crystal grows exclusively from the upper part of the convex part to form a concave part.
A semiconductor substrate that covers the convex surface .
面積の割合が、２〜３０％とされていることを特徴とす
る請求項１記載の半導体基材。2. The semiconductor substrate according to claim 1, wherein the ratio of the area occupied by the convex portion to the crystal growth surface is 2 to 30%.
体結晶とからなる半導体基材であって、半導体結晶は、Ａｌ x Ｇａ 1-x-y Ｉｎ y Ｎ（０≦ｘ≦１、
０≦ｙ≦１）によって決定される半導体からなる結晶で
あり、 基板の結晶成長面にはストライプ型の凸部を有する凹凸
が設けられ、前記結晶成長面に対する凸部の占有する面
積の割合は５０〜７０％とされ、且つ、該凸部 の幅ａは
０＜ａ＜１μｍの範囲とされ、前記半導体結晶が、該凸部の上方部から専ら成長して凹
凸面を覆っている、 半導体基材。3. A semiconductor substrate comprising a substrate and a semiconductor crystal vapor-deposited on the substrate, wherein the semiconductor crystal is Al x Ga 1-xy In y N (0 ≦ x ≦ 1,
A crystal made of a semiconductor determined by 0 ≦ y ≦ 1)
Yes, the crystal growth surface of the substrate is uneven with stripe-shaped protrusions.
A surface occupied by the convex portion with respect to the crystal growth surface
The product ratio is 50 to 70%, the width a of the convex portion is in the range of 0 <a <1 μm, and the semiconductor crystal grows from the upper portion of the convex portion to form a concave portion.
A semiconductor substrate that covers the convex surface .
体結晶とからなる半導体基材であって、半導体結晶は、Ａｌ x Ｇａ 1-x-y Ｉｎ y Ｎ（０≦ｘ≦１、
０≦ｙ≦１）によって決定される半導体からなる結晶で
あり、 基板の結晶成長面にはストライプ型の凸部を有する凹凸
が設けられ、 該 凸部の幅ａは、０＜ａ＜１μｍの範囲とされ、且つ、
該凸部の幅ａが、凹部の幅ｂ以下とされている部分を有
することを特徴とする半導体基材。4. A semiconductor substrate comprising a substrate and a semiconductor crystal vapor-deposited on the substrate, wherein the semiconductor crystal is Al x Ga 1-xy In y N (0 ≦ x ≦ 1,
A crystal made of a semiconductor determined by 0 ≦ y ≦ 1)
Yes, the crystal growth surface of the substrate is uneven with stripe-shaped protrusions.
Is provided, the width a of the convex portion is in the range of 0 <a <1 [mu] m, and,
Width a of the convex portion, the semiconductor substrate and having a portion that is the width b hereinafter recess.
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