JP3453663B2 - Surface mount type semiconductor device - Google Patents

Surface mount type semiconductor device

Info

Publication number
JP3453663B2
JP3453663B2 JP25730594A JP25730594A JP3453663B2 JP 3453663 B2 JP3453663 B2 JP 3453663B2 JP 25730594 A JP25730594 A JP 25730594A JP 25730594 A JP25730594 A JP 25730594A JP 3453663 B2 JP3453663 B2 JP 3453663B2
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring
electrode pad
metal plate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP25730594A
Other languages
Japanese (ja)
Other versions
JPH0897314A (en
Inventor
友紀 松浦
秀次 相楽
研二郎 川合
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP25730594A priority Critical patent/JP3453663B2/en
Publication of JPH0897314A publication Critical patent/JPH0897314A/en
Application granted granted Critical
Publication of JP3453663B2 publication Critical patent/JP3453663B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To make it possible to easily mount a multi-terminal semiconductor element having a high heat radiation and to easily lay and connect wires to the element by providing a semiconductor element, wiring patterns with the semiconductor element and electrode pads for external terminals having a relatively simple construction on one of the surfaces of a metal substrate. CONSTITUTION: A recessed portion 4 almost corresponding to the thickness of a semiconductor element for mounting a semiconductor element on a first surface side of a metal plate 2 is provided, and the semiconductor element is mounted on the recessed portion 4 in such a manner that an end portion of the semiconductor element faces the first surface side. On the first surface side of the metal plate 2, provided are an electrode pad 12 electrically connected to the semiconductor element and electrode pads 13 for external terminals. Also, respective electrode pads 12 and 13 and wires 14A to 14C are made by conductive thin films through insulation layers of the same shapes corresponding respectively to each portion of the surface of the metal plate. Also, wiring comprising conductive thin films through insulation layers is provided in a multi-layer state where at least part of wiring is mutually overlapped. By doing this, a multi-layer wiring comprising fine wires having high heat radiation and excellent electric characteristics can be made possible.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は，半導体素子を搭載する
樹脂封止型の表面実装型半導体装置（プラスチックパッ
ケージ）に関し、詳しくは、高集積化、高機能化に対応
できる表面実装型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed surface mount type semiconductor device (plastic package) on which a semiconductor element is mounted, and more specifically, a surface mount type semiconductor device capable of high integration and high functionality. Regarding

【０００２】[0002]

【従来の技術】従来より、樹脂封止型の半導体装置の組
立て部材として用いられているリードフレーム（単層リ
ードフレームと言う）は、一般に、図６に示すような形
状をしており、半導体素子を搭載するためのダイパッド
６０２とダイパッド６０２の周囲に設けられ、半導体素
子と結線を行うためのインナーリード６０３と、該イン
ナーリード６０３に連続し外部回路との結線を行うため
のアウターリード６０４等を備えていた。このような単
層リードフレーム６０１は、通常、コバール、４２合金
（４２％Ｎｉ−鉄）、銅系合金等の導電性に優れ、且つ
強度が大きい金属板をフオトリソグラフイー技術を用い
たエッチング加工方法やスタンピング法等により、図６
に示すような形状に加工して作製されていた。そしてこ
の単層リードフレーム６０１を用いた半導体装置は、図
７に示すように単層リードフレーム７０１のダイパッド
７０２に半導体素子７０５（以下単に素子とも言う）を
搭載するとともに、素子のボンデイングパッド（図示せ
ず）と、金や銀等の貴金属のメッキを施してあるインナ
ーリード７０３ａ、７０３ｂの先端部とを金等からなる
ワイヤ７０６により電気的に接続していた。2. Description of the Related Art Conventionally, a lead frame (referred to as a single layer lead frame) used as an assembly member of a resin-sealed semiconductor device generally has a shape as shown in FIG. A die pad 602 for mounting an element, an inner lead 603 provided around the die pad 602 for connecting to a semiconductor element, an outer lead 604 for connecting to an external circuit continuous to the inner lead 603, etc. Was equipped with. Such a single-layer lead frame 601 is usually formed by etching a metal plate such as Kovar, 42 alloy (42% Ni-iron), copper alloy, etc., which has excellent conductivity and high strength, using photolithography technology. Figure 6 by the method and stamping method
It was manufactured by processing into a shape as shown in. In a semiconductor device using this single-layer lead frame 601, a semiconductor element 705 (hereinafter also simply referred to as an element) is mounted on a die pad 702 of the single-layer lead frame 701 as shown in FIG. (Not shown) and the tips of the inner leads 703a and 703b plated with a noble metal such as gold or silver were electrically connected by a wire 706 made of gold or the like.

【０００３】しかしながら、近年、半導体装置は、電子
機器の高性能化と軽薄短小化の傾向（時流）からＬＳＩ
のＡＳＩＣに代表されるように、ますます高集積化、高
機能化になってきている。このようなＬＳＩの大規模集
積化（高集積化）はウエハープロセスでの微細加工技術
の進歩の上に成り立っており、より多くのゲートを１チ
ップに収容でき、さらにチップサイズを小さくすること
ができるようになってきている。そして、この半導体チ
ップの高集積化、高機能化は、半導体チップの動作スピ
ードの増加を招くこととなり、信号の高速処理のため、
半導体チップ内の信号遅れよりパッケージ配線での信号
の遅れの方が支配的になってきて、ノイズの問題も含め
て半導体パッケージ内の電気的特性を改善する必要に迫
られてきた。パッケージ内のインダクタンスが無視でき
ない状況になってきたのである。このようなパッケージ
内のインダクタンスを低減するために、電源、グランド
の端子数を多くし、実質的なインダクタンスを下げるよ
うにして、ノイズの低減等電気的特性の改善をしてき
た。However, in recent years, semiconductor devices have become LSIs due to the trend toward higher performance and lighter, thinner, shorter and smaller electronic devices (current trend).
As is represented by the ASIC, the higher integration and higher functionality have been achieved. Such large-scale integration (high integration) of the LSI is based on the progress of the fine processing technology in the wafer process, and it is possible to accommodate more gates in one chip and further reduce the chip size. It is becoming possible. The high integration and high functionality of this semiconductor chip leads to an increase in operation speed of the semiconductor chip.
The signal delay in the package wiring has become more dominant than the signal delay in the semiconductor chip, and it has become necessary to improve the electrical characteristics in the semiconductor package including the problem of noise. The situation is that the inductance in the package cannot be ignored. In order to reduce the inductance in such a package, the number of power supply and ground terminals is increased to substantially reduce the inductance to improve electrical characteristics such as noise reduction.

【０００４】しかしながら、電源、グランドの接続端子
数の増大は、半導体装置の総ピン数の増大にもなる。こ
の端子数の増大は、リードフレームの加工限界から、イ
ンナーリード幅、ピッチをそのままとした場合には、イ
ンナーリード部をチップから離す傾向となり、リードフ
レームのインナーリード部を含むサイズは大きくなって
しまい、半導体装置自体を逆に大きいものとしてしま
う。そこで、半導体装置サイズを変えずに入出力端子を
増やす方法としてリードフレームのアウターリードのピ
ッチを狭くする方法が採られてきた。このアウターリー
ドのピッチはこれまで１．０ｍｍから０．８ｍｍ、０．
５ｍｍと徐々に狭くなってきているが、０．４ｍｍ、
０．３ｍｍと更にピッチが狭くなるにつれ、これら狭ピ
ッチの実装工程が難しくなってきた。However, an increase in the number of power supply / ground connection terminals also increases the total number of pins in the semiconductor device. This increase in the number of terminals tends to separate the inner lead part from the chip when the inner lead width and pitch are left unchanged due to the processing limit of the lead frame, and the size of the lead frame including the inner lead part becomes large. Therefore, the size of the semiconductor device itself is increased. Therefore, as a method of increasing the number of input / output terminals without changing the semiconductor device size, a method of narrowing the outer lead pitch of the lead frame has been adopted. The pitch of the outer leads has been 1.0 mm to 0.8 mm, 0.
It is gradually narrowing to 5 mm, but 0.4 mm,
As the pitch was further narrowed to 0.3 mm, the mounting process for these narrow pitches became difficult.

【０００５】このような半導体装置の実装工程の難しさ
を回避する方法として、ＢＧＡ（ボール・グリッド・ア
レイ）と呼ばれる半導体装置が開発されている。このＢ
ＧＡは、入出力端子を増やすために、ＢＴレジン（ビス
マレイミド系樹脂）を代表とする耐熱性を有する樹脂板
を基材とする両面配線基板（プリント基板）の表面に半
導体素子を搭載し、裏面に球状の半田を取付けた外部端
子用電極を設け、スルー・ホールを通じて半導体素子と
外部端子用電極との表裏導通をとっていた。裏面の球状
の半田をアレイ状に並べることにより、端子ピッチの間
隔を従来のリードフレームを用いた半導体装置より広く
することができ、この結果、半導体装置の実装工程の難
しさの度合いを上げることなく入出力端子の増加に対応
できた。また、ＢＧＡでは電気特性の向上を図る場合
は、基板を多層構造の多層配線基板とし、両面配線基板
同様スルーホールを通じて半導体と外部端子用電極との
導通をとっていた。As a method of avoiding such difficulty of the semiconductor device mounting process, a semiconductor device called BGA (ball grid array) has been developed. This B
In order to increase the number of input / output terminals, GA mounts semiconductor elements on the surface of a double-sided wiring board (printed circuit board) whose base material is a resin plate having heat resistance typified by BT resin (bismaleimide resin). Electrodes for external terminals having spherical solder attached are provided on the back surface, and the semiconductor element and the electrodes for external terminals are electrically connected to each other through the through holes. By arranging the spherical solder on the back surface in an array, the terminal pitch can be made wider than that of the semiconductor device using the conventional lead frame, and as a result, the degree of difficulty of the mounting process of the semiconductor device can be increased. It was possible to cope with an increase in the number of input / output terminals. Further, in the BGA, in order to improve the electric characteristics, the substrate is a multilayer wiring substrate having a multilayer structure, and the semiconductor and the external terminal electrode are electrically connected through through holes as in the double-sided wiring substrate.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、従来の
ＢＧＡでは単層の両面配線基板を用いた場合も、多層配
線基板を用いた場合も同様にスルーホールを設け、この
スルーホールを通じて表裏の導通をとる必要がある。こ
のスルーホールは基板総厚が厚くなればなる程樹脂の熱
膨張の影響から断線をおこし、信頼性の低下につながっ
てしまうという問題があった。また、従来のＢＧＡは両
面配線基板にスルーホールを設け、このスルーホールを
通じて表裏の導通をとる必要があるため、半導体装置コ
ストは従来の金属板をフオトエッチング法やスタンピン
グ法等により製造されるリードフレームを用いたものよ
り生産コストが高くなってしまうという問題もあった。
そして、従来のＢＧＡは両面配線基板（プリント基板）
としてＢＴレジン（ビスマレイミド系樹脂）を代表とす
る耐熱性を有する樹脂板基材をコア材として用いている
ため熱抵抗が大きくなり、放熱性が悪くなってしまうと
いう問題もあった。さらに、プリント基板にフオトエッ
チング法により配線等を形成するため微細配線の形成が
難しく、配線の引回しに制約が生じるという問題もあっ
た。本発明は、これらの問題を解決しようとするもの
で、上記のような信頼性低下を招かず、低コストで高放
熱性で多端子半導体素子の実装が簡単に行え、さらに、
微細配線が可能で配線の引き回しが簡単な表面実装型半
導体装置を提供しようとするものである。特に、基板を
多数使用しなくても多層配線の形成が可能であり、且
つ、電気的特性に優れた表面実装型半導体装置を提供し
ようとするものである。However, in the conventional BGA, through holes are similarly provided in both cases of using a single-sided double-sided wiring board and a multi-layered wiring board. Need to take. There is a problem that as the total thickness of the through-hole becomes thicker, the through-hole is disconnected due to the influence of the thermal expansion of the resin, leading to a decrease in reliability. Also, in the conventional BGA, it is necessary to provide a through hole on the double-sided wiring board and to conduct the front and back through this through hole. Therefore, the semiconductor device cost is reduced by the lead manufactured by the conventional metal plate by the photo etching method or the stamping method. There was also a problem that the production cost would be higher than that using the frame.
The conventional BGA is a double-sided wiring board (printed board).
As a core material, a resin plate base material having heat resistance represented by BT resin (bismaleimide resin) is used as a core material, which causes a problem that heat resistance is increased and heat dissipation is deteriorated. Further, since the wirings and the like are formed on the printed circuit board by the photo etching method, it is difficult to form fine wirings, and there is a problem that wiring is restricted. The present invention is intended to solve these problems, without causing the above-mentioned reliability deterioration, it is possible to easily mount a multi-terminal semiconductor element with high heat dissipation at low cost, and further,
An object of the present invention is to provide a surface-mounting type semiconductor device capable of fine wiring and having a simple wiring arrangement. In particular, it is an object of the present invention to provide a surface mount type semiconductor device which is capable of forming multi-layer wiring without using a large number of substrates and has excellent electrical characteristics.

【０００７】[0007]

【課題を解決するための手段】本発明の表面実装型半導
体装置は、半導体素子を搭載する金属板をベースとする
配線基板を用いた樹脂封止型の表面実装型半導体装置で
あって、金属板の第一の面側に半導体素子を搭載するた
めの半導体素子の厚みに略相当する凹部を設けて、該凹
部には半導体素子の端子が第一の面側に向くように搭載
されており、該金属板の第一の面側には半導体素子と電
気的に結線された電極パッドと、外部端子用電極パッド
と、前記半導体素子と電気的に結線された電極パッドと
外部端子用電極パッドとを電気的結線した配線とを配
し、上記半導体素子と、半導体素子と電気的結線された
電極パッドと、外部端子電極パッドとの領域以外はソル
ダーレジスト等の絶縁物によってマスキングされ、金属
板の第一の面側の半導体素子全体と、半導体素子と電気
的結線された電極パッドと、該半導体素子と電気的結線
された電極パッドと半導体素子との結線部とは樹脂封止
され、金属板の第二面は樹脂封止されずに露出してお
り、上記マスキングされていない外部端子用電極パッド
から略球状に、樹脂部より外側に突出した半田部が設け
られており、前記半導体素子と電気的結線された電極パ
ッド、外部端子用電極パッド、配線は、金属板上にそれ
ぞれ対応する同形状の絶縁層を介した導電性薄膜により
設けられ、且つ、絶縁層を介した導電性薄膜からなる配
線が互いに少なくとも一部が重なる多層状態で設けられ
ていることを特徴とするものである。そして、上記の表
面実装型半導体装置において、電源配線、ＧＮＤ（グラ
ンド）配線、信号配線は、それぞれ各層に区分けされた
状態で配線されていることを特徴とするものであり、電
源配線、ＧＮＤ（グランド）配線は信号配線よりも広い
配線幅となっていることを特徴とするものである。ま
た、上記の表面実装型半導体装置において、導電性薄膜
からなる配線は、半導体素子と結線する電極パッドと外
部端子用電極パッド間の距離を略最短距離で結ぶように
配線されていることを特徴とするものである。そしてま
た、上記の表面実装型半導体装置において、導電性薄膜
および絶縁層が電着により形成されたものであることを
特徴とするものである。A surface mount semiconductor device of the present invention is a resin-sealed surface mount semiconductor device using a wiring board based on a metal plate on which a semiconductor element is mounted. The first surface side of the plate is provided with a recess substantially corresponding to the thickness of the semiconductor element for mounting the semiconductor element, and the terminals of the semiconductor element are mounted in the recess so that the terminals face the first surface side. An electrode pad electrically connected to the semiconductor element, an electrode pad for an external terminal, an electrode pad electrically connected to the semiconductor element, and an electrode pad for an external terminal on the first surface side of the metal plate And a wiring electrically connected to the semiconductor element, the electrode pad electrically connected to the semiconductor element, and the external terminal electrode pad except the area is masked by an insulator such as a solder resist, a metal plate Half of the first side of The whole body element, the electrode pad electrically connected to the semiconductor element, and the connection portion between the electrode pad electrically connected to the semiconductor element and the semiconductor element are resin-sealed, and the second surface of the metal plate is made of resin. An electrode that is exposed without being sealed and has a substantially spherical solder portion protruding from the resin portion to the outside from the unmasked external terminal electrode pad, and is electrically connected to the semiconductor element. The pad, the electrode pad for the external terminal, and the wiring are provided on the metal plate by a conductive thin film via a corresponding insulating layer having the same shape, and at least one wiring formed of the conductive thin film via the insulating layer is provided. It is characterized in that the parts are provided in a multi-layered state in which the parts overlap. And the table above
Oite the surface mount type semiconductor device, power wiring, GND (ground) wiring, signal wiring is characterized in that it is wired in a state of being respectively divided into layers, power wiring, GND (ground) The wiring has a wider wiring width than the signal wiring. Further, Oite surface mount type semiconductor device described above, the wiring made of the conductive thin film, that are wired so as to connect the distance between the electrode pad and the external terminal electrode pads of the semiconductor element and connected at substantially the shortest distance It is characterized by. And also, is characterized in that Oite surface mount type semiconductor device described above, the conductive thin film and the insulating layer is one formed by electrodeposition.

【０００８】本発明の表面実装型半導体装置は、上記の
ように、半導体装置の小型化、高集積化、高機能化に対
応するもので、その為に、放熱性（熱放散性）の良い金
属板をベースとした配線基板としており、微細加工性の
良い導電性薄膜からなる配線を用いるものであり、金属
板上に孤立した絶縁層を介して、該絶縁層と略同形状の
導電性薄膜からなる配線を形成したもので、金属板は、
半導体素子搭載側でない第二の面側は金属部が露出した
状態になっている。そして、図５に示すように、導電性
薄膜と絶縁層とを電着により形成したものを、金属板上
に転写した構成にすることにより、配線パターン部の微
細化加工を簡単なものとしている。又、本発明の表面実
装型半導体装置は、半導体素子、半導体素子と電気的結
線される電極パッド、外部端子用電極パッド、配線を全
て金属板の第一の面側に形成することにより、従来のＢ
ＧＡのように、スルホールを介して半導体素子と外部端
子を結線する必要がないものとしているが、このような
構造は、半導体素子との結線用電極パッド、外部端子用
電極パッド、配線を微細加工することにより、又、配線
を少なくとも一部が重なる多層状態に配線にすることに
より達成される。As described above, the surface mount semiconductor device of the present invention is compatible with miniaturization, high integration, and high functionality of the semiconductor device, and therefore has good heat dissipation (heat dissipation). A wiring board based on a metal plate, which uses wiring made of a conductive thin film with good microfabrication properties, and a conductive material having substantially the same shape as that of the insulation layer via an insulating layer isolated on the metal plate. Formed with thin film wiring, the metal plate is
The metal portion is exposed on the second surface side, which is not the semiconductor element mounting side. Then, as shown in FIG. 5, a conductive thin film and an insulating layer formed by electrodeposition are transferred onto a metal plate so that the wiring pattern portion can be easily miniaturized. . In addition, the surface mount semiconductor device of the present invention has a conventional structure in which the semiconductor element, the electrode pad electrically connected to the semiconductor element, the electrode pad for the external terminal, and the wiring are all formed on the first surface side of the metal plate. B
Unlike GA, it is not necessary to connect the semiconductor element and the external terminal through the through hole, but such a structure has a fine processing of the connection electrode pad for the semiconductor element, the external terminal electrode pad, and the wiring. This is also achieved by forming the wiring in a multilayer state in which at least a part of the wiring overlaps.

【０００９】[0009]

【作用】本発明の表面実装型半導体装置は、上記のよう
な構成にすることにより、多端子半導体素子の実装がで
き、且つ、高放熱性で、電気的特性に優れた微細配線か
らなる多層配線を可能としている。特に、基板を多数使
用しなくても微細配線からなる多層配線ができて配線の
引き回しを簡単なものとしている。詳しくは、金属板を
ベースとする配線基板を用いていることにより、放熱
（熱放散性）に優れたものとしており、外部端子電極及
び半田部を金属板面に配列するため、端子としては多端
子を可能としている。そして、半導体素子の端子、半導
体素子と電気的に結線した電極、外部端子用電極を全て
金属板の第一の面側に形成することにより、従来のＢＧ
Ａのように、スルホールを介して半導体素子と外部端子
を結線する必要がないものとしている。そしてまた、半
導体素子と電気的結線された電極パッド、外部端子用電
極パッド、配線が金属板上に、それぞれ、対応した形状
の絶縁層を介した、該絶縁層と同形状の導電性薄膜部か
らなっていることにより、基板を多数使用しなくても、
配線を少なくとも一部が重なる多層状態に形成できるも
のとしており、且つ、配線のインダクタンスを小さくす
ることができ電気的特性を優れたものとしている。ま
た、本発明の表面実装型半導体装置は、半導体素子と電
気的結線された電極パッド、外部端子用電極パッド、配
線が金属板上に、それぞれ、対応した形状の絶縁層を介
した、該絶縁層と同形状の導電性薄膜部からなっている
ことにより、微細配線をし易いものとしている。具体的
には、この導電性薄膜部と絶縁層とを電着で形成したも
のを使用することにより、金属板上に転写した場合に
は、微細配線を重ねあわせた状態で形成することがで
き、且つ、その作製を容易なものとしており、低コスト
の作製を可能としている。The surface-mounting type semiconductor device of the present invention has the above-mentioned structure to enable mounting of a multi-terminal semiconductor element, high heat dissipation, and a multi-layer structure including fine wiring excellent in electrical characteristics. Wiring is possible. In particular, multilayer wiring consisting of fine wiring can be formed without using a large number of substrates, and wiring can be easily routed. Specifically, by using a wiring board based on a metal plate, it has excellent heat dissipation (heat dissipation), and since the external terminal electrodes and the solder parts are arranged on the metal plate surface, they are often used as terminals. Enables terminals. Then, the terminals of the semiconductor element, the electrodes electrically connected to the semiconductor element, and the electrodes for external terminals are all formed on the first surface side of the metal plate, so that a conventional BG is formed.
Unlike the case A, it is not necessary to connect the semiconductor element to the external terminal through the through hole. Further, an electrode pad electrically connected to the semiconductor element, an electrode pad for an external terminal, and a wiring are formed on a metal plate through an insulating layer having a corresponding shape, and a conductive thin film portion having the same shape as the insulating layer is formed. Because it consists of, without using a large number of substrates,
The wiring can be formed in a multi-layered state in which at least a part of the wiring is overlapped, and the inductance of the wiring can be reduced, and the electrical characteristics are excellent. Further, the surface mount semiconductor device of the present invention is characterized in that an electrode pad electrically connected to a semiconductor element, an electrode pad for an external terminal, and a wiring are formed on a metal plate through an insulating layer having a corresponding shape. By forming the conductive thin film portion having the same shape as the layer, fine wiring can be easily performed. Specifically, by using the electroconductive thin film portion and the insulating layer formed by electrodeposition, when transferred onto a metal plate, fine wiring can be formed in a superposed state. Moreover, it is easy to manufacture, and it is possible to manufacture at low cost.

【００１０】[0010]

【実施例】本発明の表面実装半導体装置の実施例を以
下、図にそって説明する。図１は本発明の実施例表面実
装半導体装置の内部構造の要部を示す概略図であり、図
２（ａ）は本発明の実施例表面実装半導体装置の平面図
で、図２（ｂ）はその概略断面図である。図３は本実施
例表面実装半導体装置の内部構造を示した概略平面図で
あり、半導体素子、半導体素子と結線された電極パッ
ド、外部端子用電極パッド、ソルダーレジストにより覆
われている領域等を示す。図１〜図３中、１は表面実装
半導体装置、２は金属板、３は半導体素子、３Ａは半導
体素子端子、４は半導体素子搭載部、５はワイヤ、６は
樹脂、８は半田、９はソルダーレジスト、１２は半導体
素子との結線用電極パッド、１３は外部端子用電極パッ
ド、１４は配線部、１４Ａは信号配線、１４ＢはＧＮＤ
配線、１４Ｃは電源配線、１５は絶縁層である。本実施
例表面実装半導体装置は、図２（ｂ）に示すように半導
体素子３の厚みに略相当する凹形状の半導体素子搭載部
４をＣｕからなる金属板２の一方の面（第一面）に設け
たもので、図１に示すように、金属板２の一方の面（第
一面）側の凹形状の半導体素子搭載部４側を含まない領
域に半導体素子３との結線用電極パッド１２、外部端子
用電極パッド１３、配線部１４を配設しており、半導体
素子３の端子３Ａと半導体素子３との結線用電極パッド
１２はワイヤ５により結線され、半導体素子との結線用
電極パッド１２と外部端子用電極パッド１３とは配線部
１４により結線されている。上記、導体素子搭載部４は
Ｃｕ、Ａｌ等の熱伝導性に優れる金属板である。Embodiments of the surface mount semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view showing a main part of an internal structure of a surface mount semiconductor device according to an embodiment of the present invention, and FIG. 2A is a plan view of a surface mount semiconductor device according to an embodiment of the present invention, and FIG. Is a schematic sectional view thereof. FIG. 3 is a schematic plan view showing the internal structure of the surface mount semiconductor device of this embodiment, showing a semiconductor element, electrode pads connected to the semiconductor element, electrode pads for external terminals, regions covered with solder resist, and the like. Show. 1 to 3, 1 is a surface mount semiconductor device, 2 is a metal plate, 3 is a semiconductor element, 3A is a semiconductor element terminal, 4 is a semiconductor element mounting portion, 5 is a wire, 6 is resin, 8 is solder, 9 Is a solder resist, 12 is an electrode pad for connection with a semiconductor element, 13 is an electrode pad for external terminals, 14 is a wiring portion, 14A is a signal wiring, and 14B is GND.
Wiring, 14C is a power supply wiring, and 15 is an insulating layer. In the surface-mounted semiconductor device of this embodiment, as shown in FIG. 2B, the concave semiconductor element mounting portion 4 substantially corresponding to the thickness of the semiconductor element 3 is provided on one surface (first surface) of the metal plate 2 made of Cu. ), As shown in FIG. 1, an electrode for connecting to the semiconductor element 3 in a region not including the concave semiconductor element mounting portion 4 side on one surface (first surface) side of the metal plate 2. A pad 12, an external terminal electrode pad 13, and a wiring portion 14 are provided. The connection electrode pad 12 for connecting the terminal 3A of the semiconductor element 3 and the semiconductor element 3 is connected by a wire 5 for connection with a semiconductor element. The electrode pad 12 and the external terminal electrode pad 13 are connected by a wiring portion 14. The conductor element mounting portion 4 is a metal plate such as Cu or Al having excellent thermal conductivity.

【００１１】本実施例表面実装半導体装置においては、
図１に示すように、半導体素子３との結線用電極パッド
１２、外部端子用電極パッド１３、配線部１４は、それ
ぞれ、対応した形状の絶縁層１５を介して、該絶縁層１
５と同形状の導電性薄膜からなっており、絶縁層１５と
同形状の導電性薄膜とは一体となって、金属基板２上に
少なくとも一部が重なる多層状態で設けられているが、
電源配線１４Ｃ、ＧＮＤ（グランド）配線１４Ｂ、信号
配線１４Ａは、各層に区分けられクロスオーバーして配
線されている。本実施例では３層になっており、一番金
属基板２側に近い１層目の配線及び２層目の配線は３層
目（外部側）に比べ配線幅は広く形成しており、外部側
の３層目の配線部を信号配線１４Ａとしており、２層目
の配線をＧＮＤ（グランド）配線１４Ｂ、１層目の配線
を電源配線１４Ｃとしている。そして、導電性薄膜から
なる配線（１４Ａ、１４Ｂ、１４Ｃ）は、半導体素子３
との結線用電極パッド１２と外部端子用電極パッド１３
間の距離を略最短距離で結ぶように配線されている。導
電性薄膜と絶縁層１５は電着によって形成されたもの
で、導電性薄膜としてＣｕ単層、約５．０μｍ厚のもの
を、絶縁層は粘着性をもつポリアミック酸薄膜からなる
絶縁性の有機絶縁層を使用した。又、図３に示すよう
に、上記、外部端子用電極パッド１３と半導体素子３や
半導体素子との結線用電極パッド１２、ワイヤ５のある
領域を除きソルダーレジスト９で覆い、外部端子用電極
パッド１３部のみが露出するようにしてある。この露出
した外部端子用電極パッド１３部には球状の半田を付着
させ実装時の外部端子としている。球状の半田部は、図
２（ｂ）に示すように、樹脂部６よりも外側に大きく突
出している。尚、電源配線１４Ｃ、ＧＮＤ（グランド）
配線１４Ｂの配線幅を信号配線１４Ａの配線幅より広く
しているがこの理由は、高速素子を実装する場合には、
パッケージの伝送特性を向上させる必要があり、このた
めパッケージ自身の特性インピーダンス整合をとること
からマイクロストリップライン構造に極力近づける為で
ある。In the surface mount semiconductor device of this embodiment,
As shown in FIG. 1, the connection electrode pad 12 with the semiconductor element 3, the external terminal electrode pad 13, and the wiring portion 14 are formed through the insulating layer 15 having a corresponding shape.
5 is formed of a conductive thin film having the same shape as the insulating layer 15, and the conductive thin film having the same shape as the insulating layer 15 is integrally provided on the metal substrate 2 in a multi-layer state in which at least a part thereof overlaps.
The power supply wiring 14C, the GND (ground) wiring 14B, and the signal wiring 14A are divided into layers and crossed over. In the present embodiment, there are three layers, and the wiring of the first layer and the wiring of the second layer closest to the metal substrate 2 side are formed to have a wider wiring width than that of the third layer (outside). The wiring portion of the third layer on the side is the signal wiring 14A, the wiring of the second layer is the GND (ground) wiring 14B, and the wiring of the first layer is the power wiring 14C. The wirings (14A, 14B, 14C) made of the conductive thin film are used for the semiconductor element 3
Electrode pad 12 for connection with and electrode pad 13 for external terminal
It is wired so that the distance between them is connected at a substantially shortest distance. The conductive thin film and the insulating layer 15 are formed by electrodeposition, and the conductive thin film is a Cu single layer having a thickness of about 5.0 μm, and the insulating layer is an insulating organic film made of a polyamic acid thin film having an adhesive property. An insulating layer was used. Further, as shown in FIG. 3, the external terminal electrode pad 13 is covered with the solder resist 9 except for the area where the wire 5 and the semiconductor element 3 or the semiconductor element 3 and the wire 5 are connected. Only 13 parts are exposed. Spherical solder is attached to the exposed external terminal electrode pad 13 to form an external terminal for mounting. As shown in FIG. 2 (b), the spherical solder portion projects more outward than the resin portion 6. Power wiring 14C, GND (ground)
The wiring width of the wiring 14B is made wider than that of the signal wiring 14A. The reason for this is that when a high-speed element is mounted,
This is because it is necessary to improve the transmission characteristics of the package, and for this reason, the characteristic impedance matching of the package itself is taken, so that the microstrip line structure is made as close as possible.

【００１２】次いで、本発明の表面実装半導体装置の製
造方法を挙げ、図４に沿って説明する。図４は製造工程
を説明するため要部の概略図である。先ず、表面実装半
導体装置のベースとなる基材であるＣｕからなる金属板
４０１に半導体素子搭載用の凹部４０２を形成した。
（Ａ） 次いで、凹部を形成した側の金属板表面（凹部を除く）
に半導体素子との結線用の電極パッド４０３、外部端子
用の電極パッド４０４、配線４０５を絶縁層４１５を介
して後述する転写方法により形成した（Ｂ）。 電着により形成されたＣｕからなる導電性薄膜を転写に
より電極パッド４０３、４０４、配線４０５として形成
しているため、この部分の微細加工を可能としている。
次いで、半導体素子領域（凹部４０２）や半導体素子と
の結線用の電極パッド４０３領域、外部端子用の電極パ
ッド４０４のみを露出させた状態に、ソルダーレジスト
４０６で覆った。この後、ソルダーレジスト４０６から
露出した、外部端子用の電極パッド４０４の表面を電解
金メッキ４１０を施しておく。（Ｃ） 次いで、金属板４０１の凹部４０２に半導体素子４０７
を端子側が露出するようにして搭載した。（Ｄ） 半導体素子を凹部４０２に搭載した後、半導体素子４０
７の端子部と電極パッド４０３とを金線からなるワイヤ
４０８にてボンデイング結線した（Ｅ）。 ボンデイング結線後、半導体素子４０７、ワイヤ４０
８、半導体素子との結線用の電極パッド４０３とを含む
所定領域をイオン性不純物の含有量が少ないエポキシか
らなる樹脂４０９にて樹脂封止した。（Ｆ） 次いで、ソルダーレジスト４０６から露出した外部端子
用電極パッド４０４部上の金メッキ４１０部上に球状に
半田４１１を作製して（Ｇ）、表面実装半導体装置を得
た。この状態に相当するものが図２である。球状の半田
４１１の作製は、金メッキされている外部端子用電極パ
ッド４０４にフラックスを供給した後、０．８ｍｍφ程
度の半田ボールを搭載し、リフローすることにより行
う。Next, a method of manufacturing the surface mount semiconductor device of the present invention will be described with reference to FIG. FIG. 4 is a schematic view of a main part for explaining the manufacturing process. First, a recess 402 for mounting a semiconductor element was formed on a metal plate 401 made of Cu, which is a base material serving as a base of a surface mount semiconductor device.
(A) Next, the surface of the metal plate on the side where the recess is formed (excluding the recess)
Then, an electrode pad 403 for connection with a semiconductor element, an electrode pad 404 for an external terminal, and a wiring 405 were formed via an insulating layer 415 by a transfer method described later (B). Since the conductive thin film made of Cu formed by electrodeposition is formed as the electrode pads 403, 404 and the wiring 405 by transfer, fine processing of this portion is possible.
Then, the semiconductor element region (recess 402), the electrode pad 403 region for connection with the semiconductor element, and the electrode pad 404 for external terminals were exposed, and covered with a solder resist 406. After that, the surface of the electrode pad 404 for the external terminal exposed from the solder resist 406 is subjected to electrolytic gold plating 410. (C) Next, the semiconductor element 407 is formed in the recess 402 of the metal plate 401.
Was mounted with the terminal side exposed. (D) After mounting the semiconductor element in the recess 402, the semiconductor element 40
The terminal portion of No. 7 and the electrode pad 403 were bonded by a wire 408 made of a gold wire (E). After bonding connection, semiconductor element 407, wire 40
8. A predetermined region including the electrode pad 403 for connection with the semiconductor element was resin-sealed with a resin 409 made of epoxy having a low content of ionic impurities. (F) Next, a spherical solder 411 was produced on the gold-plated 410 portion on the external terminal electrode pad 404 portion exposed from the solder resist 406 (G) to obtain a surface-mounted semiconductor device. FIG. 2 corresponds to this state. The spherical solder 411 is produced by supplying flux to the gold-plated external terminal electrode pad 404, mounting a solder ball of about 0.8 mmφ, and performing reflow.

【００１３】次に、本発明の表面実装半導体装置の製造
方法の要部である、半導体素子との結線用電極パッドと
外部端子用電極パッドと、配線パターン等を転写形成す
る工程について、図５に基づいて説明する。まず、転写
用基板としての導電性基板５１１上にフオトレジストを
塗布してフオトレジスト層５１２を形成した（図５
（ａ））。そして所定のフオトマスク５１３を用いてフ
オトレジスト層５１２を密着露光し、現像して、フオト
レジストパターン５１２ａを形成し、導電性基板５１１
のうち電極パッドないし配線用パターン５１１ａを露出
させた（図５（ｃ））。転写用基板としての導電性基板
５１１としては、厚さ０．１５ｍｍのステンレス板（Ｓ
ＵＳ３０４ＭＡ材）を用い、フオトレジストとしては日
本合成ゴム（株）製感光性レジストＣＢＲ−Ｍ９０１の
１００ｃｐのものを用いて、１，０００ｒｐｍ、４０ｓ
ｅｃ条件で導電性基板５１１上にスピン塗布した。塗布
レジストを乾燥後、必要電極パターン部が遮光性のフオ
トマスク５１３を用いて密着露光し、現像、キュアし、
膜厚約５．０μｍの反転レジストパターンからなるフオ
トレジストパターン５１１ａを得た。Next, the process of transferring and forming the electrode pads for connection with the semiconductor element, the electrode pads for external terminals, the wiring pattern, etc., which is the main part of the method for manufacturing a surface-mounted semiconductor device of the present invention, will be described with reference to FIG. It will be described based on. First, a photoresist is applied on a conductive substrate 511 as a transfer substrate to form a photoresist layer 512 (FIG. 5).
(A)). Then, the photoresist layer 512 is closely exposed using a predetermined photomask 513 and developed to form a photoresist pattern 512a, and the conductive substrate 511 is formed.
Of these, the electrode pad or the wiring pattern 511a was exposed (FIG. 5C). As the conductive substrate 511 as the transfer substrate, a stainless steel plate (S
US304MA material), and using a photoresist of CBR-M901 100 cp manufactured by Japan Synthetic Rubber Co., Ltd. as a photoresist, 1,000 rpm, 40 s
The conductive substrate 511 was spin-coated under the ec condition. After drying the applied resist, contact exposure is performed using a photomask 513 having a required electrode pattern portion having a light-shielding property, development and curing are performed,
A photoresist pattern 511a consisting of a reverse resist pattern having a film thickness of about 5.0 μm was obtained.

【００１４】次に、導電性基板５１１の露出した電極パ
ッドないし配線用パターン５１１ａ部上にメッキ法によ
り銅からなる導電性薄膜５１４を形成した（図５
（ｄ））。ここでは、露出した電極パッドないし配線用
パターン５１１ａを配設した導電性基板５１１を表−１
に示すメッキ液組成およびメッキ条件でメッキ液に浸
漬、通電することにより、パターン部のみに約５．０μ
ｍ厚の銅メッキを施した。 （表−１） メッキ液組成 ピロリン酸銅 ９４ｇ／ｌ ピロリン酸カリウム ３４０ｇ／ｌ Ｐ比 ７．０ ＰＨ ８．８ 液温 ５５°Ｃ 電流密度 ５Ａ／ｄｍ2 時間 ５．０ｍｉｎNext, a conductive thin film 514 made of copper is formed on the exposed electrode pad or wiring pattern 511a of the conductive substrate 511 by a plating method (FIG. 5).
(D)). Here, the conductive substrate 511 on which the exposed electrode pad or wiring pattern 511a is arranged is shown in Table 1.
By immersing in the plating solution and energizing it with the plating solution composition and plating conditions shown in, about 5.0μ only in the pattern part.
m copper plating was applied. (Table-1) Plating liquid composition Copper pyrophosphate 94 g / l Potassium pyrophosphate 340 g / l P ratio 7.0 PH 8.8 Liquid temperature 55 ° C Current density 5 A / dm 2 hours 5.0 min

【００１５】その後、導電性薄膜５１４上に電着により
粘着性あるいは接着性のある絶縁性樹脂層５１５を形成
する（図５（ｅ））。これにより、電極パッド、配線用
の導電性薄膜５１４と絶縁樹脂層５１５とを有する、転
写版５１７が得られた。粘着性あるいは接着性の絶縁性
樹脂層５１５の形成は以下のようにして行った。導電性
薄膜５１４が配設された導電性基板５１１を水洗乾燥
後、後述する電着液（Ａ）に浸漬させ、導電性基板５１
１側を陽極に、同面積のステンレス板を陰極に載置し、
極板距離を５０ｍｍに対向させ、５０Ｖで導電性基板５
１１側を１０分間連続印加することにより、露出した電
極パッドないし配線パターン５１１ａ部の銅の上のみに
選択的にポリアミック酸薄膜からなる絶縁性樹脂層５１
５を形成した。電着液（Ａ）は、表−２に示す混合溶液
を室温にて１２時間反応させた後、トリエチルアミン３
部を添加し、室温にて約１時間反応させた液とメタノー
ルを１：１に混合して作製した。 （表−２） Ｎ、Ｎ−ジメチルホルムアミド １３５部 Ｐ−フエニルレジアミン ５部 ピロメリット酸二無水物 １０部After that, a sticky or adhesive insulating resin layer 515 is formed on the conductive thin film 514 by electrodeposition (FIG. 5 (e)). As a result, a transfer plate 517 having an electrode pad, a conductive thin film 514 for wiring, and an insulating resin layer 515 was obtained. The adhesive or adhesive insulating resin layer 515 was formed as follows. The conductive substrate 511 provided with the conductive thin film 514 is washed with water and dried, and then dipped in an electrodeposition liquid (A) described later to form the conductive substrate 51.
Place one side on the anode and the stainless plate of the same area on the cathode,
Conductive substrate 5 at 50V with the electrode plate distance facing 50 mm
By continuously applying the voltage on the 11 side for 10 minutes, the insulating resin layer 51 composed of the polyamic acid thin film is selectively formed only on the exposed electrode pad or the copper of the wiring pattern 511a.
5 was formed. The electrodeposition solution (A) was prepared by reacting the mixed solution shown in Table 2 at room temperature for 12 hours, and then using triethylamine 3
Was added, and the mixture was reacted at room temperature for about 1 hour and mixed with methanol in a ratio of 1: 1 to prepare a mixture. (Table-2) N, N-dimethylformamide 135 parts P-phenylrediamine 5 parts Pyromellitic dianhydride 10 parts

【００１６】次に、金属板５１７上に、上記転写版５１
６を絶縁樹脂層５１５が基板５１７に接するように熱プ
レスにて圧着した（図５（ｆ））。この圧着は、必要に
応じて、ローラ圧着、プレート圧着、真空圧着等、いず
れの方法にしたがっても良く、絶縁性樹脂層５１５が接
着性の絶縁性樹脂からなる場合には熱圧着を行うことも
できる。その後、導電性基板５１１を剥離して電極パッ
ドないし配線用パターン部５１１ａに形成された導電性
薄膜５１４と絶縁性樹脂層５１５とを絶縁性樹脂層５１
５を介して金属板５１７に転写することにより、電極パ
ッドないし配線部５１８を形成した（図５（ｇ））。こ
の時の電極パッドないし配線部５１８は下層にポリイミ
ド膜、上層に銅の２層構造となっている。熱プレスによ
る圧着は、絶縁性樹脂層５１５を形成した導電性基板５
１１を洗浄、乾燥後、金属板５１７の凹部形成面とパタ
ーン面を対向接触させ（図５（ｆ））、両裏面より、
１．０Ｋｇ／ｃｍ2 、２５０℃、１時間の条件で行っ
た。この後室温まで冷却した後、圧力を解除し、該電極
パターン原版と金属板５１７とを引き離して、該電極パ
ッドないし配線用パターン５１１ａ部の導電性薄膜層５
１４と絶縁性樹脂層５１５のみを金属板５１７側に転写
することができた。Next, the transfer plate 51 is placed on the metal plate 517.
6 was pressed by hot pressing so that the insulating resin layer 515 was in contact with the substrate 517 (FIG. 5 (f)). This pressure bonding may be performed by any method such as roller pressure bonding, plate pressure bonding, vacuum pressure bonding, etc., if necessary, and when the insulating resin layer 515 is made of an adhesive insulating resin, thermocompression bonding may be performed. it can. After that, the conductive substrate 511 is peeled off, and the conductive thin film 514 and the insulating resin layer 515 formed on the electrode pad or the wiring pattern portion 511a are separated from each other by the insulating resin layer 51.
The electrode pad or the wiring portion 518 was formed by transferring it to the metal plate 517 via 5 (FIG. 5G). At this time, the electrode pad or wiring portion 518 has a two-layer structure of a lower layer of a polyimide film and an upper layer of copper. The pressure bonding by hot pressing is performed by the conductive substrate 5 on which the insulating resin layer 515 is formed.
After cleaning and drying 11, the recess forming surface of the metal plate 517 and the pattern surface are brought into contact with each other (FIG. 5 (f)).
It was performed under the conditions of 1.0 Kg / cm 2 , 250 ° C., and 1 hour. Then, after cooling to room temperature, the pressure is released, the electrode pattern original plate and the metal plate 517 are separated, and the conductive thin film layer 5 of the electrode pad or the wiring pattern 511a is removed.
Only 14 and the insulating resin layer 515 could be transferred to the metal plate 517 side.

【００１７】尚、電極パッドないし配線用パターン５１
１ａ部の導電性薄膜層５１４形成の為のメッキ金属は、
Ｃｕ、Ａｕ、Ａｇ等の金属単体もしくは導電性電着樹
脂、あるいはこれら導電性電析物質を多層にしたもので
あっても良い。The electrode pad or wiring pattern 51 is used.
The plating metal for forming the conductive thin film layer 514 of the 1a part is
It may be a metal simple substance such as Cu, Au, Ag or the like, a conductive electrodeposition resin, or a multilayer of these conductive electrodeposition substances.

【００１８】又、上記ポリアミック酸薄膜に代表される
絶縁性樹脂層５１５材は、常温もしくは加熱により粘着
性もしくは接着性を示す電着性絶縁物質であれば良い。
例えば、使用する高分子としては、粘着性を有するアニ
オン性、またはカチオン性の合成高分子樹脂を挙げるこ
とができる。具体的には、アニオン性合成高分子樹脂と
しては、アクリル樹脂、ポリエステル樹脂、マレイン化
油樹脂、ポリブタジエン樹脂、エポキシ樹脂等を単独
で、あるいは、これらの樹脂の任意の組合せによる混合
物として使用できる。さらに、上記アニオン性合成高分
子樹脂とメラニン樹脂、フエノール樹脂、ウレタン樹脂
等の架橋性樹脂とを併用してもよい。また、カチオン性
の合成高分子樹脂として、アクリル樹脂、エポキシ樹
脂、ウレタン樹脂、ポリブタジエン樹脂、ポリアミド樹
脂、ポリイミド樹脂等を単独あるいは、これらの任意の
組合せによる混合物として使用できる。さらに、上記カ
チオン性合成高分子樹脂とポリエステル樹脂、ウレタン
樹脂等の架橋性樹脂とを併用しても良い。また、上記高
分子樹脂に粘着性を付与するためにロジン系、テンペル
系、石油樹脂系等の粘着付与樹脂を必要に応じて添加す
ることも可能である。上記高分子樹脂は、前述した本発
明の製造方法においてアルカリ性または酸性物質により
中和して水に可溶化された状態、または水分散状態で電
着法に供される。すなわち、アニオン性合成高分子樹脂
は、トリメチルアミン、ジメチルアミン、ジメチルエタ
ノールアミン、ジイソプロパノールアミン等のアミン
類、アンモニア、苛性カリ等の無機アルカリで中和す
る。また、カチオン性合成高分子樹脂は、酢酸、ギ酸、
プロピオン酸、乳酸等の酸で中和する。そして、中和さ
れ水に可溶化された高分子樹脂は、水分散型、または溶
解型として水に希釈された状態で使用される。そして、
本実施例の表面実装型半導体装置作製においては、上記
図５（ａ）〜図５（ｇ）の工程を電源配線、ＧＮＤ（グ
ランド）配線、信号配線の順に区別して、それぞれ別に
計３回、繰り返し行った。これにより、各配線は、半導
体素子と結線する電極パッドと外部端子用電極パッド間
の距離を略最短距離で結ぶように設計されているので、
少なくとも一部が重なる配線が形成された。金属基板５
１７に１番近い側の１層目を電源配線、中間の２層目を
ＧＮＤ（グランド）配線、外部に最も近い３層目を信号
配線である。以上の方法により、電着粘着性の絶縁層で
絶縁された導電性薄膜部からなる電極パッド、配線、外
部接続端子用電極パッドを、すくなくも配線の一部を重
なる状態に形成した、表面実装備型半導体装置が製造さ
れる。The insulating resin layer 515 material typified by the above polyamic acid thin film may be any electrodepositable insulating substance which exhibits tackiness or adhesiveness at room temperature or heating.
For example, as the polymer to be used, anionic or cationic synthetic polymer resin having adhesiveness can be mentioned. Specifically, as the anionic synthetic polymer resin, an acrylic resin, a polyester resin, a maleinized oil resin, a polybutadiene resin, an epoxy resin, or the like can be used alone or as a mixture of any combination of these resins. Furthermore, the anionic synthetic polymer resin and a crosslinkable resin such as a melanin resin, a phenol resin, and a urethane resin may be used in combination. As the cationic synthetic polymer resin, acrylic resin, epoxy resin, urethane resin, polybutadiene resin, polyamide resin, polyimide resin or the like can be used alone or as a mixture of any combination thereof. Further, the above cationic synthetic polymer resin may be used in combination with a crosslinkable resin such as polyester resin and urethane resin. In addition, a tackifying resin such as a rosin-based resin, a tempel-based resin, a petroleum resin-based resin or the like may be added as necessary to impart tackiness to the polymer resin. The polymer resin is subjected to the electrodeposition method in a state where it is solubilized in water by being neutralized with an alkaline or acidic substance in the above-mentioned production method of the present invention, or in a water dispersed state. That is, the anionic synthetic polymer resin is neutralized with amines such as trimethylamine, dimethylamine, dimethylethanolamine and diisopropanolamine, and inorganic alkali such as ammonia and caustic potash. Also, the cationic synthetic polymer resin is acetic acid, formic acid,
Neutralize with acids such as propionic acid and lactic acid. The polymer resin neutralized and solubilized in water is used in a state of being diluted with water as a water dispersion type or a dissolution type. And
In the fabrication of the surface mount type semiconductor device of the present embodiment, the steps of FIGS. 5A to 5G are distinguished in the order of the power supply wiring, the GND (ground) wiring and the signal wiring, respectively, and a total of three times, respectively. I went repeatedly. As a result, each wiring is designed to connect the electrode pad connected to the semiconductor element and the electrode pad for the external terminal with a substantially shortest distance,
At least a part of the wiring was formed so as to overlap. Metal substrate 5
The first layer on the side closest to 17 is the power supply wiring, the second intermediate layer is the GND (ground) wiring, and the third layer closest to the outside is the signal wiring. By the above method, the electrode pad, the wiring, and the electrode pad for the external connection terminal, which are made of the conductive thin film portion insulated by the electrodeposition adhesive insulating layer, are formed so that at least a part of the wiring is overlapped. An equipped semiconductor device is manufactured.

【００１９】[0019]

【発明の効果】本発明の表面実装型半導体装置は、以上
のように、従来のＢＧＡ（ボール・グリッド・アレイ）
のように、スルホールを設けた複雑で信頼性の低い構造
ではなく、金属基板の一方の面に半導体素子、半導体素
子との結線用、配線パターン、外部端子用電極パッドを
設けた比較的簡単な構造のもので、半導体素子の高集積
化、高機能化に対応でき、放熱性（熱放散性）に優れ、
微細化が可能な表面実装型半導体装置の提供を可能とす
るものである。詳しくは、従来のＢＧＡ（ボール・グリ
ッド・アレイ）に比べ、スルホールを用いたものでない
ため、製造コストを大幅に削減でき、信頼性も高くな
り、コア材として金属板を用いているため放熱性に優れ
たものとなる。特に、配線部は導電性薄膜からなる配線
と、該導電性薄膜と同形状の絶縁層を一体として、且
つ、配線をクロフオーバーないし多層に、少なくとも一
部が重なる状態に形成しており、全体の総厚を厚くしな
いで、信頼性の良い構造を可能としている。また、電源
配線、ＧＮＤ（グランド）配線、信号配線を多重に配線
することにより、配線のインダクタンスを小さくするこ
とが可能で、電気的特性にもすぐれた構造を可能として
いる。As described above, the surface mount type semiconductor device of the present invention has the conventional BGA (ball grid array).
It is not a complicated and unreliable structure with through holes, but a relatively simple structure with semiconductor elements, wiring for connecting to semiconductor elements, wiring patterns, and electrode pads for external terminals on one side of the metal substrate. With a structure, it can correspond to higher integration and higher functionality of semiconductor elements, and has excellent heat dissipation (heat dissipation),
It is possible to provide a surface mount semiconductor device that can be miniaturized. In detail, compared to the conventional BGA (ball grid array), it does not use through holes, so the manufacturing cost can be greatly reduced, the reliability is high, and the heat dissipation due to the use of a metal plate as the core material. Will be excellent. In particular, the wiring portion is formed by integrally forming a wiring made of a conductive thin film and an insulating layer having the same shape as the conductive thin film, and forming the wiring in a cloverover or a multilayer so that at least a part of the wiring overlaps. This enables a reliable structure without increasing the total thickness of the. In addition, since the power supply wiring, the GND (ground) wiring, and the signal wiring are multiply arranged, the inductance of the wiring can be reduced and a structure having excellent electrical characteristics can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図１】実施例表面実装型半導体装置の内部構造の要部
概略図FIG. 1 is a schematic view of a main part of an internal structure of a surface mount semiconductor device according to an embodiment.

【図２】実施例表面実装型半導体装置の平面図および断
面図FIG. 2 is a plan view and a sectional view of a surface mount semiconductor device according to an embodiment.

【図３】実施例表面実装型半導体装置の内部構造の概略
図FIG. 3 is a schematic diagram of an internal structure of an example surface mount semiconductor device.

【図４】本発明の表面実装型半導体装置の製造方法実施
例の工程図FIG. 4 is a process chart of an embodiment of a method for manufacturing a surface mount semiconductor device of the present invention.

【図５】本発明の表面実装型半導体装置の製造方法実施
例の要部である転写工程を説明するための図FIG. 5 is a diagram for explaining a transfer step which is a main part of the embodiment of the method for manufacturing the surface mount semiconductor device of the present invention.

【図６】従来の単層リードフレームを示す図FIG. 6 is a diagram showing a conventional single-layer lead frame.

【図７】従来の単層リードフレームを用いた半導体装置
の要部を示す図FIG. 7 is a diagram showing a main part of a semiconductor device using a conventional single-layer lead frame.

【符号の説明】[Explanation of symbols]

１ 表面実装型半導体装置 ２ 金属板 ３ 半導体素子 ３Ａ 半導体素子の端子 ４ 半導体素子搭載部 ５ ワイヤ ６ 樹脂部 ８ 半田 ９ ソルダーレジスト １２ 半導体素子との結線用電極パッド １３ 外部端子用電極パッド １４ 配線パターン １４Ａ 信号配線 １４Ｂ ＧＮＤ配線 １４Ｃ 電源配線 ４０１ 金属板 ４０２ 凹部 ４０３ 半導体素子との結線用電極パッド ４０４ 外部端子用電極パッド ４０５ 配線 ４０６ ソルダーレジスト ４０７ 半導体素子 ４０８ ワイヤ ４０９ 樹脂 ４１０ 金メッキ ４１１ 半田 ４１５ 絶縁層 ５１１ 導電性基板 ５１１ａ 電極パッドないし配線用パターン部 ５１２ フオトレジスト ５１２ａ フオトレジストパターン ５１３ フオトマスク ５１４ 導電性薄膜 ５１５ 絶縁性樹脂層 ５１６ 転写板 ５１７ 金属板 ５１８ 電極パッドないし配線 ６０１ 単層リードフレーム ６０２ ダイパッド ６０３ インナーリード ６０４ アウターリード ７０１ 単層リードフレーム ７０２ ダイパッド ７０３、７０３ａ インナーリード ７０５ 半導体素子 ７０６ ワイヤ 1 Surface mount semiconductor device 2 metal plate 3 Semiconductor element 3A Semiconductor element terminals 4 Semiconductor element mounting part 5 wires 6 Resin part 8 solder 9 Solder resist 12 Electrode pad for connection with semiconductor element 13 External terminal electrode pad 14 wiring pattern 14A signal wiring 14B GND wiring 14C power supply wiring 401 metal plate 402 recess 403 Electrode pad for connection with semiconductor element 404 External terminal electrode pad 405 wiring 406 Solder resist 407 Semiconductor element 408 wire 409 resin 410 gold plating 411 solder 415 insulating layer 511 conductive substrate 511a Electrode pad or wiring pattern portion 512 photoresist 512a photoresist pattern 513 photo mask 514 conductive thin film 515 Insulating resin layer 516 Transfer plate 517 metal plate 518 Electrode pad or wiring 601 single layer lead frame 602 die pad 603 Inner lead 604 outer lead 701 Single layer lead frame 702 die pad 703, 703a Inner lead 705 Semiconductor element 706 wire

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平８−37204（ＪＰ，Ａ) 特開 平７−335784（ＪＰ，Ａ) 特開 平８−97315（ＪＰ，Ａ) 特開 平８−78574（ＪＰ，Ａ) 特開 平６−177275（ＪＰ，Ａ) 特開 平４−49641（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/06 H01L 21/60 311 H01L 23/12 501 H01L 23/50 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-8-37204 (JP, A) JP-A-7-335784 (JP, A) JP-A-8-97315 (JP, A) JP-A-8- 78574 (JP, A) JP-A-6-177275 (JP, A) JP-A-4-49641 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/06 H01L 21 / 60 311 H01L 23/12 501 H01L 23/50

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体素子を搭載する金属板をベースと
する配線基板を用いた樹脂封止型の表面実装型半導体装
置であって、金属板の第一の面側に半導体素子を搭載す
るための半導体素子の厚みに略相当する凹部を設けて、
該凹部には半導体素子の端子が第一の面側に向くように
搭載されており、該金属板の第一の面側には半導体素子
と電気的に結線された電極パッドと、外部端子用電極パ
ッドと、前記半導体素子と電気的に結線された電極パッ
ドと外部端子用電極パッドとを電気的結線した配線とを
配し、上記半導体素子と、半導体素子と電気的結線され
た電極パッドと、外部端子電極パッドとの領域以外はソ
ルダーレジスト等の絶縁物によってマスキングされ、金
属板の第一の面側の半導体素子全体と、半導体素子と電
気的結線された電極パッドと、該半導体素子と電気的結
線された電極パッドと半導体素子との結線部とは樹脂封
止され、金属板の第二面は樹脂封止されずに露出してお
り、上記マスキングされていない外部端子用電極パッド
から略球状に、樹脂部より外側に突出した半田部が設け
られており、前記半導体素子と電気的結線された電極パ
ッド、外部端子用電極パッド、配線は、金属板上にそれ
ぞれ対応する同形状の絶縁層を介した導電性薄膜により
設けられ、且つ、絶縁層を介した導電性薄膜からなる配
線が互いに少なくとも一部が重なる多層状態で設けられ
ていることを特徴とする表面実装型半導体装置。1. A resin-sealed surface mount semiconductor device using a wiring board based on a metal plate on which a semiconductor element is mounted, wherein the semiconductor element is mounted on the first surface side of the metal plate. By providing a recess substantially corresponding to the thickness of the semiconductor element,
A terminal of a semiconductor element is mounted in the recess so as to face the first surface side, and an electrode pad electrically connected to the semiconductor element is provided on the first surface side of the metal plate and for an external terminal. An electrode pad, an electrode pad electrically connected to the semiconductor element, and a wiring electrically connected to the external terminal electrode pad are arranged, the semiconductor element, and an electrode pad electrically connected to the semiconductor element. , The whole semiconductor element on the first surface side of the metal plate, which is masked with an insulator such as a solder resist except for the area of the external terminal electrode pad, the electrode pad electrically connected to the semiconductor element, and the semiconductor element. The electrically connected electrode pad and the connection between the semiconductor element and the semiconductor element are resin-sealed, and the second surface of the metal plate is exposed without being resin-sealed. Almost spherical, tree A solder portion protruding outward from the portion is provided, and the electrode pad electrically connected to the semiconductor element, the external terminal electrode pad, and the wiring are formed on the metal plate through corresponding insulating layers of the same shape. Conductive thin film
Provided, and a surface mount type semiconductor device, wherein a wiring made of a conductive thin film through the insulating layer is provided at least partially overlap the multilayer with each other. 【請求項２】 電源配線、ＧＮＤ配線、信号配線は、そ
れぞれ各層に区分けされた状態で配線されていることを
特徴とする請求項１に記載の表面実装型半導体装置。2. The surface mount semiconductor device according to claim 1, wherein the power supply wiring, the GND wiring, and the signal wiring are wired in a state of being divided into respective layers. 【請求項３】 電源配線、ＧＮＤ配線は信号配線よりも
広い配線幅となっていることを特徴とする請求項２に記
載の表面実装型半導体装置。3. A power supply wiring, GND wiring serial it has a wider wiring width than the signal lines to claim 2, wherein
Surface mounting semiconductor device mounting. 【請求項４】 導電性薄膜からなる配線は、半導体素子
と結線する電極パッドと外部端子用電極パッド間の距離
を略最短距離で結ぶように配線されていることを特徴と
する請求項１ないし３のいずれかの項に記載の表面実装
型半導体装置。4. A composed of a conductive thin film wiring claims 1, characterized in that it is wired so as to connect the distance between the electrode pads and the electrode pads for external terminals of the semiconductor element and connected at substantially the shortest distance 4. The surface-mounted semiconductor device according to any one of item 3 above . 【請求項５】 導電性薄膜および絶縁層が電着により形
成されたものであることを特徴とする請求項１ないし４
のいずれかの項に記載の表面実装型半導体装置。 It 5. A conductive thin film and the insulating layers claims 1, characterized in that one formed by electrodeposition 4
The surface-mounted semiconductor device according to any one of 1 .
JP25730594A 1994-09-28 1994-09-28 Surface mount type semiconductor device Expired - Fee Related JP3453663B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25730594A JP3453663B2 (en) 1994-09-28 1994-09-28 Surface mount type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25730594A JP3453663B2 (en) 1994-09-28 1994-09-28 Surface mount type semiconductor device

Publications (2)

Publication Number Publication Date
JPH0897314A JPH0897314A (en) 1996-04-12
JP3453663B2 true JP3453663B2 (en) 2003-10-06

Family

ID=17304519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25730594A Expired - Fee Related JP3453663B2 (en) 1994-09-28 1994-09-28 Surface mount type semiconductor device

Country Status (1)

Country Link
JP (1) JP3453663B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2156839C2 (en) * 1996-03-06 2000-09-27 Мицубиси Рэйон Ко., Лтд. Fibril system filaments (versions), formed article, fibril system filament manufacture method, spinning die for manufacture of fibril system filaments
KR100209259B1 (en) * 1996-04-25 1999-07-15 이해규 Ic card and method for manufacture of the same
US6384471B1 (en) 1999-05-10 2002-05-07 Bull S.A. Pbga package with integrated ball grid
FR2793606B1 (en) * 1999-05-10 2003-06-13 Bull Sa PBGA HOUSING WITH INTEGRATED BILLING GRILLE
DE10039646A1 (en) 1999-08-18 2001-03-08 Murata Manufacturing Co Metal cover placed over and enclosing e.g. piezoelectric resonator on circuit substrate, includes insulating layer on and around edges bordering its open end
JP2011108818A (en) * 2009-11-17 2011-06-02 Mitsui High Tec Inc Manufacturing method of lead frame and manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JPH0897314A (en) 1996-04-12

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