JP3444832B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3444832B2
JP3444832B2 JP2000003103A JP2000003103A JP3444832B2 JP 3444832 B2 JP3444832 B2 JP 3444832B2 JP 2000003103 A JP2000003103 A JP 2000003103A JP 2000003103 A JP2000003103 A JP 2000003103A JP 3444832 B2 JP3444832 B2 JP 3444832B2
Authority
JP
Japan
Prior art keywords
manufacturing
semiconductor device
semiconductor
antimony
metal coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000003103A
Other languages
Japanese (ja)
Other versions
JP2001196393A (en
Inventor
眞▲覩▼ 横沢
耕慈 日高
裕司 加藤
敏明 室田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2000003103A priority Critical patent/JP3444832B2/en
Publication of JP2001196393A publication Critical patent/JP2001196393A/en
Application granted granted Critical
Publication of JP3444832B2 publication Critical patent/JP3444832B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法、特に、大電力用の半導体装置に適した製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method suitable for a high power semiconductor device.

【０００２】[0002]

【従来の技術】比較的大きな電力を扱うパワートランジ
スタのような大電力用の半導体装置は、所定の素子を形
成した半導体基板を分割して得た半導体素子（半導体チ
ップ）をリードフレームにはんだ材を用いて固定（ダイ
ボンディング）して製造される。この半導体装置は、さ
らに、プリント配線板等にはんだ付けして実装される。
このため、ダイボンディング用はんだ材には、実装の際
に適用される実装温度に耐え得る耐熱性を有することが
求められる。ダイボンディング用はんだ材としては、従
来、融点が３２０℃の９７Ｐｂ／３Ｓｎ合金（９７重量
％の鉛と３重量％の錫との合金；以下、合金の組成表示
に関しては上記と同様の表記により簡略化して示すこと
がある）が用いられてきた。2. Description of the Related Art A semiconductor device for high power such as a power transistor that handles a relatively large amount of power uses a semiconductor element (semiconductor chip) obtained by dividing a semiconductor substrate on which a predetermined element is formed as a solder material on a lead frame. It is manufactured by fixing (die bonding) using. This semiconductor device is further soldered and mounted on a printed wiring board or the like.
Therefore, the solder material for die bonding is required to have heat resistance capable of withstanding the mounting temperature applied during mounting. As a soldering material for die bonding, a 97Pb / 3Sn alloy having a melting point of 320 ° C. (an alloy of 97% by weight of lead and 3% by weight of tin) has been conventionally used. Have been used).

【０００３】近年、環境保護の観点から、各種電子機器
から環境負荷が大きい鉛を排除することが求められてい
る。半導体装置をプリント配線板上に実装するために用
いられてきた低融点のはんだ材（代表的はんだ材として
融点１８３℃の３７Ｐｂ／６３Ｓｎ）として鉛を排除し
た材料を用いると、はんだ材の融点が上昇する。このた
め、半導体装置の実装温度も上げざるを得ない。実装温
度を上げても、従来通り９７Ｐｂ／３Ｓｎ合金をダイボ
ンディング用はんだ材として使用できれば支障はない。
しかし、ダイボンディング用の材料からも鉛を排除する
ことが必要とされている。In recent years, from the viewpoint of environmental protection, it has been required to eliminate lead, which has a large environmental load, from various electronic devices. When a material excluding lead is used as a low melting point soldering material (a typical soldering material having a melting point of 183 ° C., 37Pb / 63Sn) that has been used for mounting a semiconductor device on a printed wiring board, the melting point of the soldering material is To rise. Therefore, the mounting temperature of the semiconductor device has to be raised. Even if the mounting temperature is raised, there will be no problem if the 97Pb / 3Sn alloy can be used as a solder material for die bonding as usual.
However, it is necessary to exclude lead from the material for die bonding.

【０００４】鉛を含まない高融点のはんだ材としては、
亜鉛、アルミニウムを主体とする合金が知られている
が、この合金は半導体素子とのぬれ性が悪くダイボンデ
ィング用はんだ材としては実用的ではない。実用的な鉛
フリーはんだとしては錫系合金が知られているが、錫系
合金は一般には融点が低く、むしろ低融点のはんだ材と
して使用されている。As a high melting point solder material containing no lead,
An alloy mainly composed of zinc and aluminum is known, but this alloy has poor wettability with a semiconductor element and is not practical as a solder material for die bonding. A tin-based alloy is known as a practical lead-free solder, but the tin-based alloy generally has a low melting point and is rather used as a low melting point solder material.

【０００５】錫系合金の中では、錫−アンチモン系合金
が比較的高融点となる。特開平５５−１２７０２７号公
報には、鉛フリー化に伴う実装温度上昇に対応するため
ではなく引っ張り強度を改善するためであるが、アンチ
モンを６．０〜１１．５重量％含有する錫合金をダイボ
ンディング用はんだ材として用いた半導体装置が開示さ
れている。この半導体装置は、図６に示すように、予め
ニッケル被膜１０２および金被膜１０３を形成した半導
体素子１０１を、上記錫合金をはんだ材１０４として、
ニッケル被膜１０５を形成したリードフレーム１０６に
固定したものである。Among the tin-based alloys, the tin-antimony-based alloy has a relatively high melting point. Japanese Patent Application Laid-Open No. 55-127027 discloses a tin alloy containing 6.0 to 11.5 wt% of antimony for the purpose of improving the tensile strength, not to cope with the mounting temperature rise accompanying lead-free. A semiconductor device used as a solder material for die bonding is disclosed. In this semiconductor device, as shown in FIG. 6, a semiconductor element 101 in which a nickel coating 102 and a gold coating 103 are formed in advance is used, and the tin alloy is used as a solder material 104.
It is fixed to the lead frame 106 on which the nickel coating 105 is formed.

【０００６】[0006]

【発明が解決しようとする課題】特開平５５−１２７０
２７号公報に記載のように、半導体素子の接合面にニッ
ケル被膜を形成すると接合部の機械的強度が向上する。
また、ニッケル被膜上にさらに金や銀の被膜を形成する
とはんだ材のぬれ性を改善できる。しかし、金や銀の被
膜を用いてはんだ材のぬれ性を改善したのでは、はんだ
材を溶融して半導体素子を接合する際に金や銀がはんだ
材に融合してはんだ材の融点が過度に低下する。その一
方、はんだ材とのぬれ性を改善しなければ、ボイドの多
発による接合不良を招きやすい。[Patent Document 1] Japanese Patent Application Laid-Open No. 55-1270
As described in Japanese Patent Publication No. 27, when a nickel film is formed on the joint surface of the semiconductor element, the mechanical strength of the joint portion is improved.
Further, the wettability of the solder material can be improved by further forming a gold or silver film on the nickel film. However, if the wettability of the solder material is improved by using a gold or silver coating, when the solder material is melted and the semiconductor element is joined, gold or silver is fused to the solder material and the melting point of the solder material becomes excessive. Fall to. On the other hand, unless the wettability with the solder material is improved, defective bonding is likely to occur due to frequent occurrence of voids.

【０００７】そこで、本発明は、鉛フリー化に伴う実装
温度の上昇に対応しながらも、はんだのぬれ性を改善し
て良好な接合特性が得られる半導体装置の製造方法を提
供することを目的とする。Therefore, the present invention aims to provide a method of manufacturing a semiconductor device which can improve solder wettability and obtain good bonding characteristics while coping with a rise in mounting temperature accompanying lead-free. And

【０００８】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明の第１の半導体装置の製造方法は、半導体支
持板との接合面となる表面に、第１の金属被膜と第２の
金属被膜とをこの順に形成した半導体素子を作製し、前
記半導体素子の前記接合面をはんだ材を用いて前記半導
体支持板上に接合するに際し、前記はんだ材とともに前
記第２の金属被膜を溶融して前記第２の金属被膜を前記
はんだ材に融合させて接合部を形成する半導体装置の製
造方法であって、前記第２の金属被膜を錫またはアンチ
モンを含む被膜とし、前記接合部を、錫を主成分とし、
アンチモンを１０重量％以上含有する合金とすることを
特徴とする。In order to achieve the above object, the first method for manufacturing a semiconductor device according to the present invention comprises a first metal film and a second metal film on a surface which is a bonding surface with a semiconductor supporting plate. A metal film is formed in this order to produce a semiconductor element, and when the bonding surface of the semiconductor element is bonded onto the semiconductor support plate using a solder material, the second metal film is melted together with the solder material. A method of manufacturing a semiconductor device in which the second metal coating is fused with the solder material to form a joint, wherein the second metal coating is a coating containing tin or antimony, and the joint is With tin as the main component,
The alloy is characterized by containing 10 wt% or more of antimony.

【０００９】上記第１の製造方法によれば、はんだ材の
融点の低下を抑制しながらも、第２の金属被膜がはんだ
材のぬれ性を改善するため、良好な接合特性を得ること
ができる。According to the first manufacturing method described above, the second metal coating improves the wettability of the solder material while suppressing the lowering of the melting point of the solder material, so that good bonding characteristics can be obtained. .

【００１０】本発明の第１の製造方法では、第２の金属
被膜を錫およびアンチモンを含有する被膜とすることが
好ましい。この場合は、第２の金属被膜に、半導体素子
に近くなるほどアンチモンの濃度が高くなる濃度分布を
付与するか、あるいは、第２の金属被膜を多層膜とし、
この多層膜における半導体素子に最も近い層を、錫を主
成分とし、アンチモンを１５重量％以上含有する層とす
ることが好ましい。このように、被膜中の半導体素子に
近い部分におけるアンチモン濃度を高くすると、この部
分での合金の融点が高くなる。このため、真空蒸着によ
って被膜形成する際に第２の金属被膜の溶融が少なくな
り、その後の工程に来る、例えば半導体基板をチップ分
割する際の作業性を改善できる。In the first manufacturing method of the present invention, it is preferable that the second metal coating is a coating containing tin and antimony. In this case, the second metal coating is provided with a concentration distribution in which the concentration of antimony increases toward the semiconductor element, or the second metal coating is a multilayer film,
The layer closest to the semiconductor element in this multilayer film is preferably a layer containing tin as a main component and antimony in an amount of 15% by weight or more. Thus, if the antimony concentration in the portion of the film close to the semiconductor element is increased, the melting point of the alloy in this portion increases. For this reason, when the film is formed by vacuum vapor deposition, the second metal film is less melted, and the workability in the subsequent step, for example, when the semiconductor substrate is divided into chips, can be improved.

【００１１】上記第１の製造方法では、第２の金属被膜
およびはんだ材に、それぞれ、錫およびアンチモンを含
有させることが好ましい。In the first manufacturing method, it is preferable that the second metal coating and the solder material contain tin and antimony, respectively.

【００１２】上記第１の製造方法では、接合部を２４０
℃以上の融点を有する合金とすることが好ましい。はん
だ材の鉛フリー化に伴って半導体装置の実装温度が高く
なっているためである。錫−アンチモン合金の融点は、
例えば９０Ｓｎ／１０Ｓｂ合金で２４６℃であり、アン
チモン含有量が増すにつれて融点（液相温度）が上昇す
る。In the first manufacturing method, the joint portion is
It is preferable to use an alloy having a melting point of not less than ° C. This is because the mounting temperature of the semiconductor device is increasing with the lead-free solder material. The melting point of tin-antimony alloy is
For example, the 90Sn / 10Sb alloy has a temperature of 246 ° C., and the melting point (liquidus temperature) rises as the antimony content increases.

【００１３】上記第１の製造方法では、第２の金属被膜
の厚さを０．５μｍ以上１０μｍ以下とすることが好ま
しい。第２の金属被膜の厚さが薄すぎるとボイドの減少
に対しての効果が十分得にくくなる。In the first manufacturing method described above, the thickness of the second metal coating is preferably 0.5 μm or more and 10 μm or less. If the thickness of the second metal coating is too thin, it becomes difficult to obtain a sufficient effect for reducing voids.

【００１４】上記第１の製造方法では、接合部の厚さを
１０μｍ以上４０μｍ以下とすることが好ましい。接合
部の厚さが薄すぎると半導体素子が破損するおそれがあ
り、厚すぎると後述する熱抵抗（ΔＶｂｅ）が増加する
ことがある。In the first manufacturing method described above, it is preferable that the thickness of the joint is 10 μm or more and 40 μm or less. If the thickness of the joint is too thin, the semiconductor element may be damaged, and if it is too thick, the thermal resistance (ΔVbe) described below may increase.

【００１５】また、本発明の第２の半導体装置の製造方
法は、半導体支持板との接合面となる表面に、第１の金
属被膜と、錫を主成分とし、アンチモンを１０重量％以
上含有する合金である第２の金属被膜とをこの順に形成
した半導体素子を作製し、前記半導体素子の前記接合面
を、前記第２の金属被膜を溶融して形成した接合部によ
り、前記半導体支持板上に接合するに際し、第１の製造
方法と同様の理由から、第２の金属被膜に、前記半導体
素子に近くなるほどアンチモンの濃度が高くなる濃度分
布を付与するか、あるいは、第２の金属被膜を多層膜と
し、この多層膜における前記半導体素子に最も近い層
を、錫を主成分とし、アンチモンを１５重量％以上含有
する層とすることを特徴とする。According to a second method of manufacturing a semiconductor device of the present invention, the first metal film, tin is a main component, and antimony is contained in an amount of 10% by weight or more on the surface serving as a bonding surface with the semiconductor support plate. A semiconductor element in which a second metal coating that is an alloy is formed in this order is manufactured, and the semiconductor support plate is formed by a bonding portion formed by melting the second metal coating on the bonding surface of the semiconductor element. When joining on top , the first production
For the same reason as the method, the second metal film is provided with the above semiconductor.
The concentration of antimony increases as it gets closer to the element.
A cloth is applied or the second metal coating is used as a multilayer film.
And the layer closest to the semiconductor element in this multilayer film
Contains tin as a main component and contains antimony in an amount of 15% by weight or more.
It is characterized in that it is a layer .

【００１６】上記第２の製造方法によれば、接合の際に
はんだ材に微量成分が混入することがなく、融点の低下
を防止できる。同時に、予め接合面にはんだ材となる被
膜を形成しているため、良好な接合特性を実現できる。According to the second manufacturing method, trace components are not mixed in the solder material at the time of joining, and the melting point can be prevented from lowering. At the same time, since a coating film serving as a solder material is formed on the joint surface in advance, good joint characteristics can be realized.

【００１７】上記第２の製造方法では、第２の金属被膜
の厚さを１０μｍ以上４０μｍ以下とすることが好まし
い。接合部を構成する第２の金属被膜の厚さが薄すぎる
と半導体素子が破損するおそれがあり、厚すぎると熱抵
抗（ΔＶｂｅ）が増加することがある。In the second manufacturing method, it is preferable that the thickness of the second metal coating is 10 μm or more and 40 μm or less. If the thickness of the second metal film forming the joint is too thin, the semiconductor element may be damaged, and if it is too thick, the thermal resistance (ΔVbe) may increase.

【００１８】また、上記第２の製造方法では、第２の金
属被膜が溶融して形成された接合部を、２４０℃以上の
融点を有する合金とすることが好ましい。In the second manufacturing method, it is preferable that the joint formed by melting the second metal coating is an alloy having a melting point of 240 ° C. or higher.

【００１９】[0019]

【発明の実施の形態】以下、本発明の好ましい形態につ
いて図面を参照しながら説明する。 （第１の実施形態）図１に示したように、本実施形態で
は、所定の素子を形成した半導体基板を分割して得た半
導体素子１の接合面に、第１の金属被膜２と第２の金属
被膜３とがこの順に形成されている。Preferred embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) As shown in FIG. 1, in the present embodiment, a first metal film 2 and a first metal film 2 are formed on a bonding surface of a semiconductor element 1 obtained by dividing a semiconductor substrate on which predetermined elements are formed. The metal coating 3 of 2 is formed in this order.

【００２０】第１の金属被膜２としては、ニッケルを主
成分とする被膜が好ましい。第１の金属被膜は多層膜と
してもよい。多層膜としては、例えば、半導体素子に近
い側の層をクロム、バナジウムなどの層とし、この層の
上にニッケル層を形成した膜が挙げられる。半導体素子
の表面は、元来、直接はんだ材と接着しないが、第１の
金属被膜を形成することによってはんだ材との接着性を
得る。すなわち、第１の金属被膜を形成することによ
り、半導体装置の機械的強度やオーミック特性が改善さ
れる。第１の金属被膜は、図２に示すように、基本的
に、ダイボンディングの後にも被膜として残存する。第
１の金属被膜２の厚さは、０．１μｍ以上１．０μｍ以
下が好ましい。The first metal coating 2 is preferably a coating containing nickel as a main component. The first metal coating may be a multilayer film. Examples of the multilayer film include a film in which a layer close to the semiconductor element is a layer of chromium, vanadium, or the like, and a nickel layer is formed on this layer. Originally, the surface of the semiconductor element does not directly adhere to the solder material, but the first metal film is formed to obtain the adhesiveness to the solder material. That is, by forming the first metal film, the mechanical strength and ohmic characteristics of the semiconductor device are improved. As shown in FIG. 2, the first metal film basically remains as a film even after die bonding. The thickness of the first metal coating 2 is preferably 0.1 μm or more and 1.0 μm or less.

【００２１】第２の金属被膜３としては、錫−アンチモ
ン合金を主成分とする被膜が好ましい。第２の金属被膜
は、ダイボンディングの際には、はんだ材と融合して接
合部を形成する。第２の金属被膜の組成は、接合部７の
組成が、錫を主成分とし、アンチモンを１０重量％以上
含有する合金となる範囲において、はんだ材の組成とと
もに調整される。このような第２の金属被膜を形成する
ことにより、接合部の融点を過度に低下させることな
く、はんだ材のぬれ性が改善され、接合部のボイド発生
も抑制される。The second metal coating 3 is preferably a coating containing a tin-antimony alloy as a main component. The second metal coating fuses with the solder material to form a joint during die bonding. The composition of the second metal film is adjusted together with the composition of the solder material so long as the composition of the joint 7 is an alloy containing tin as a main component and antimony in an amount of 10 wt% or more. By forming such a second metal coating, the wettability of the solder material is improved and the occurrence of voids in the joint is suppressed without excessively lowering the melting point of the joint.

【００２２】第１の金属被膜２および第２の金属被膜３
の形成方法については特に制限はなく、蒸着法、スパッ
タリング法、メッキなどを適用することができる。これ
らの被膜は、各素子へとチップ分割する前に予め半導体
基板上に成膜することが好ましい。First metal coating 2 and second metal coating 3
There is no particular limitation on the method of forming, and a vapor deposition method, a sputtering method, plating or the like can be applied. It is preferable that these films are formed in advance on the semiconductor substrate before the chip is divided into each element.

【００２３】はんだ材４も、第２の金属被膜と同様、錫
−アンチモン合金を主成分とすることが好ましい。はん
だ材の組成は、第２の金属被膜と同様、接合部の組成が
所定範囲となるように調整される。It is preferable that the solder material 4 also contains a tin-antimony alloy as a main component, like the second metal coating. Like the second metal coating, the composition of the solder material is adjusted so that the composition of the joint is within a predetermined range.

【００２４】接合部７は、第２の金属被膜３とはんだ材
４とが融合して形成される。この接合部７は、鉛フリー
化に伴う半導体装置の実装温度の上昇に対応できる耐熱
性を有する。半導体装置の実装温度は、具体的には、リ
フロー実装については２４０℃、フロー実装については
２６０℃が想定される。この温度が適用される実装工程
では、２６０℃、１０秒間の耐熱試験に耐え得ることが
求められる。この耐熱試験に耐える接合部を構成するた
めには、接合部を構成する合金の融点としては、概略２
４０℃以上が必要となる。The joint portion 7 is formed by fusing the second metal coating 3 and the solder material 4. The joint portion 7 has heat resistance that can cope with an increase in the mounting temperature of the semiconductor device due to the lead-free structure. Specifically, the mounting temperature of the semiconductor device is assumed to be 240 ° C. for reflow mounting and 260 ° C. for flow mounting. In the mounting process to which this temperature is applied, it is required to withstand a heat resistance test at 260 ° C. for 10 seconds. In order to form a joint that can endure this heat resistance test, the melting point of the alloy forming the joint is approximately 2
40 ° C or higher is required.

【００２５】接合部は、錫を主成分とし、アンチモンを
１２重量％以上含有する合金とすることが好ましい。上
記のように、９０Ｓｎ／１０Ｓｂ合金は２４６℃の融点
（液相温度）を有するが、８５Ｓｎ／１５Ｓｂ合金は２
５０℃を超える融点（液相温度）を有する。合金の融点
の上限は、本発明の目的が達成される限り制限されな
い。しかし、融点が上がりすぎてダイボンディングに支
障を生じさせないためには、融点を３３０℃以下とする
ことが好ましい。The joint is preferably made of an alloy containing tin as a main component and antimony in an amount of 12% by weight or more. As described above, the 90Sn / 10Sb alloy has a melting point (liquidus temperature) of 246 ° C., while the 85Sn / 15Sb alloy has a melting point of 2 ° C.
It has a melting point (liquidus temperature) of more than 50 ° C. The upper limit of the melting point of the alloy is not limited as long as the object of the present invention is achieved. However, in order not to raise the melting point so much that it hinders die bonding, it is preferable to set the melting point to 330 ° C. or less.

【００２６】なお、接合部は、実質的に錫−アンチモン
合金からなることが好ましいが、この合金の融点を基準
として融点の低下が１０℃を超えない範囲で、パラジウ
ム、銀、銅などの微量成分が含まれていてもよい。It is preferable that the joint portion is substantially made of a tin-antimony alloy, but a trace amount of palladium, silver, copper or the like is used as long as the lowering of the melting point does not exceed 10 ° C. based on the melting point of this alloy. Ingredients may be included.

【００２７】半導体支持板となるリードフレーム６の表
面にも、予め金属被膜５を形成しておくことが好まし
い。この金属被膜５も、ダイボンディングの後にも被膜
として残存する。金属被膜５としては、ニッケルを主成
分とする被膜が好ましいが、後に行うワイヤボンディン
グとの関連から、ワイヤーボンド部分は、銀などその他
の金属を主成分とする被膜としてもよい。It is preferable that the metal coating 5 is formed in advance on the surface of the lead frame 6 which will be the semiconductor support plate. This metal film 5 also remains as a film after die bonding. The metal film 5 is preferably a film containing nickel as a main component, but the wire bond portion may be a film containing other metal such as silver as a main component in connection with wire bonding to be performed later.

【００２８】半導体素子をリードフレームにダイボンデ
ィングした後、通常は、図５に示すように、半導体素子
１１を外部電極１２と導体ワイヤ１４により接続し（ワ
イヤボンディング）、さらに樹脂１３により、半導体素
子１１を接合部１７とともに封止して、リードフレーム
１６と一体化する（ただし、図５では第１の金属被膜の
図示を省略している）。こうして、鉛フリーはんだを用
いながらも、接合特性と耐熱性に優れた半導体装置が完
成する。After the semiconductor element is die-bonded to the lead frame, the semiconductor element 11 is usually connected to the external electrode 12 by the conductor wire 14 (wire bonding) as shown in FIG. 11 is sealed together with the joint portion 17 and integrated with the lead frame 16 (however, the illustration of the first metal coating is omitted in FIG. 5). In this way, a semiconductor device having excellent bonding characteristics and heat resistance is completed while using lead-free solder.

【００２９】（第２の実施形態）図３に示したように、
本実施形態においても、所定の素子を形成した半導体基
板を分割して得た半導体素子１の接合面に、第１の金属
被膜２と第２の金属被膜８とがこの順に形成されてい
る。ダイボンディング後の断面形状も、図２と同様とな
る。(Second Embodiment) As shown in FIG.
Also in this embodiment, the first metal coating 2 and the second metal coating 8 are formed in this order on the bonding surface of the semiconductor element 1 obtained by dividing the semiconductor substrate on which predetermined elements are formed. The cross-sectional shape after die bonding is the same as in FIG.

【００３０】しかし、本実施形態では、第２の金属被膜
８がはんだ材として使用されるため、ダイボンディング
後の接合部７が、実質的に第２の金属被膜のみから構成
される。したがって、本実施形態では、第２の金属被膜
の組成を、接合部の組成が上記で説明した範囲となるよ
うに調整すればよい。また、本実施形態では、第２の金
属被膜をはんだ材として機能する程度に厚膜化される。
第２の金属被膜の膜厚は、１０μｍ以上４０μｍ以下、
特に２０μｍ以上３０μｍ以下が好適である。However, in this embodiment, since the second metal coating 8 is used as a solder material, the joint portion 7 after die bonding is substantially composed of only the second metal coating. Therefore, in the present embodiment, the composition of the second metal film may be adjusted so that the composition of the joint portion is in the range described above. Further, in the present embodiment, the second metal film is made thick enough to function as a solder material.
The thickness of the second metal coating is 10 μm or more and 40 μm or less,
In particular, it is preferably 20 μm or more and 30 μm or less.

【００３１】本実施形態のようにはんだ材を用いない形
態は、第１の実施形態よりもダイボンド工程の簡易化と
いう点で優れ、比較的小型の半導体素子に適している。
一方、第１の実施形態は、接合部のボイド発生を減少さ
せるという点で本実施形態よりも有利であり、比較的大
型の半導体素子に適している。The form using no solder material as in this embodiment is superior to the first embodiment in that the die bonding process is simplified, and is suitable for a relatively small semiconductor element.
On the other hand, the first embodiment is more advantageous than the present embodiment in that the occurrence of voids in the joint is reduced, and is suitable for a relatively large semiconductor element.

【００３２】本実施形態も、上記で説明した点を除いて
は、第１の実施形態と同様にして実施できる。This embodiment can also be implemented in the same manner as the first embodiment except for the points described above.

【００３３】なお、上記両実施形態では、第２の金属被
膜３，８において、半導体素子１側が相対的にアンチモ
ン濃度が高くなるように濃度分布を付与することが好ま
しい。このような濃度分布は、例えば、錫−アンチモン
合金を蒸着法により成膜する際に、アンチモンと錫との
蒸気圧の差を利用することにより形成できる。また例え
ば、スパッタリング法により成膜する際に、各ターゲッ
トへの電圧印加を調整することにより濃度分布を形成し
てもよい。In both of the above embodiments, it is preferable that the second metal coatings 3 and 8 have a concentration distribution so that the semiconductor element 1 side has a relatively high antimony concentration. Such a concentration distribution can be formed, for example, by utilizing the difference in vapor pressure between antimony and tin when forming a film of a tin-antimony alloy by a vapor deposition method. Further, for example, when forming a film by the sputtering method, the concentration distribution may be formed by adjusting the voltage application to each target.

【００３４】これに代えて、第２の金属被膜３，８を２
層以上の層からなる多層膜とし、半導体素子に最も近い
層のアンチモン濃度を１５重量％以上とした形態も好ま
しい。多層膜を２層膜として、第２の実施形態に適用し
た場合の例を、図４に示す。この例では、２層の被膜８
ａ，８ｂのうち、半導体素子に近い層８ａを、錫を主成
分とし、アンチモンを１５重量％以上含む層とする。Instead of this, the second metal coatings 3 and 8 are formed into two layers.
It is also preferable that the multi-layered film is composed of more than one layer, and the antimony concentration of the layer closest to the semiconductor element is 15% by weight or more. FIG. 4 shows an example in which the multilayer film is a two-layer film and is applied to the second embodiment. In this example, the two-layer coating 8
Of the layers a and 8b, the layer 8a close to the semiconductor element is a layer containing tin as a main component and antimony in an amount of 15% by weight or more.

【００３５】第２の金属被膜３，８を、第１の金属被膜
とともに、チップ分割前の半導体基板に形成する場合、
半導体素子に近い側の膜の融点がより高いと、チップ分
割の際の作業性が向上する。第２の金属被膜に、上記の
ような濃度分布または多層構成として素子側のアンチモ
ン濃度を上昇させると、製造加工歩留まりが向上する。When the second metal coatings 3 and 8 are formed together with the first metal coating on the semiconductor substrate before chip division,
If the melting point of the film on the side closer to the semiconductor element is higher, the workability at the time of chip division is improved. By increasing the concentration of antimony on the element side in the second metal film in the above-mentioned concentration distribution or in the multilayer structure, the manufacturing processing yield is improved.

【００３６】[0036]

【実施例】以下、本発明の実施例によりさらに詳細に説
明するが、本発明は以下の実施例に制限されるものでは
ない。EXAMPLES The present invention will now be described in more detail by way of examples, but the present invention is not limited to the following examples.

【００３７】図５に示した装置と同様の半導体装置を、
（表１）に示した被膜、接合用はんだ材、および接合法
を用いて作製した。半導体素子としては、３ｍｍ角のｎ
ｐｎトランジスタを用いた。この半導体素子の接合面に
は、第１の金属被膜として厚さ０．３μｍのニッケル被
膜を真空蒸着法により成膜した。なお、半導体支持板と
しては表面に予めメッキによりニッケル被膜を成膜した
リードフレームを用いた。A semiconductor device similar to the device shown in FIG.
The coating film, the solder material for joining, and the joining method shown in (Table 1) were used for the production. As a semiconductor element, n of 3 mm square
A pn transistor was used. On the bonding surface of this semiconductor element, a nickel coating having a thickness of 0.3 μm was formed as a first metal coating by a vacuum vapor deposition method. As the semiconductor supporting plate, a lead frame having a nickel film formed on the surface by plating in advance was used.

【００３８】表１に示した組成を有する第２の金属被膜
は、蒸着法によりニッケル被膜上に成膜した。ただし、
サンプル１３については第２の金属被膜の成膜を省略し
た。また、サンプル６については、第２の金属被膜をト
ランジスタに近い側から７０Ｓｎ／３０Ｓｂ合金層と９
５Ｓｎ／５Ｓｂ合金層とからなる２層膜とした。さら
に、サンプル７については、第２の金属被膜を、トラン
ジスタに最も近い部分が７０Ｓｎ／３０Ｓｂ合金とな
り、最も遠い部分が９５Ｓｎ／５Ｓｂ合金となるように
アンチモン濃度がほぼ連続的に変化する濃度分布を有す
る膜とした。The second metal coating having the composition shown in Table 1 was formed on the nickel coating by the vapor deposition method. However,
For Sample 13, the formation of the second metal coating was omitted. In addition, in Sample 6, the second metal coating was formed on the side closer to the transistor as a 70Sn / 30Sb alloy layer and
A two-layer film composed of a 5Sn / 5Sb alloy layer was formed. Furthermore, for sample 7, the second metal coating was formed with a concentration distribution in which the antimony concentration changed substantially continuously such that the portion closest to the transistor was the 70Sn / 30Sb alloy and the farthest portion was the 95Sn / 5Sb alloy. The film has.

【００３９】接合（ダイボンディング）の方法は、以下
の方法Ａ、方法Ｂのいずれかとした。 ・方法Ａ；所定組成を有するはんだ箔（厚さ０．１ｍ
ｍ、３．２ｍｍ角）を用いて３４０℃に加熱してダイボ
ンディングした。 ・方法Ｂ；所定組成を有するはんだワイヤ（直径１ｍ
ｍ）を用いて３３０℃に加熱してダイボンディングし
た。The method of joining (die bonding) was either method A or method B below.・ Method A: Solder foil having a predetermined composition (thickness 0.1 m
m, 3.2 mm square) and heated to 340 ° C. for die bonding. -Method B: Solder wire having a predetermined composition (diameter 1 m
m) was used to heat to 330 ° C. for die bonding.

【００４０】ただし、サンプル８および９では、厚膜化
した第２金属被膜自体をはんだ材として用いたため、接
合用はんだ材は使用していない。すなわちこの場合は、
以下の方法Ｃにより接合した。 ・方法Ｃ；蒸着法により形成した第２の電極被膜を３６
０℃に加熱して直接ダイボンディングした。However, in Samples 8 and 9, since the thickened second metal film itself was used as the solder material, the solder material for joining was not used. That is, in this case,
It joined by the following method C. Method C: 36 second electrode film formed by vapor deposition
It was heated to 0 ° C. and directly die-bonded.

【００４１】さらに、直径２５０μｍのアルミニウム細
線を用いて、超音波溶接法により外部電極と半導体素子
をワイヤボンディングし、さらにオルソラッククレゾー
ルノボラック系エポキシ樹脂を用い、型締めしながら１
８０℃で３分間加熱して半導体素子を封止し、さらに１
８０℃で１０時間熱処理した。Further, an aluminum fine wire having a diameter of 250 μm is used to wire-bond the external electrode and the semiconductor element by an ultrasonic welding method, and an ortholac cresol novolac epoxy resin is used to clamp the die 1
Heat the semiconductor element at 80 ° C for 3 minutes to seal the semiconductor element.
Heat treatment was performed at 80 ° C. for 10 hours.

【００４２】 （表１） ―――――――――――――――――――――――――――――――――― サンプル 第２の金属被膜 接合用はんだ材 接合法 成 分 重量[mg] 成 分 重量[mg] ―――――――――――――――――――――――――――――――――― １ 100Sn 0.19 71Sn/29Sb 18 Ａ ２ 95Sn/5Sb 0.12 80Sn/20Sb 12 Ａ ３ 91.5Sn/8.5Sb 0.06 85Sn/15Sb 18 Ａ ４ 90Sn/10Sb 0.12 90Sn/10Sb 18 Ａ ５ 85Sn/15Sb 0.12 90Sn/10Sb 18 Ａ ６ 70Sn/30Sb-95Sn/5Sb 0.12 90Sn/10Sb 18 Ａ ７ 70Sn/30Sb-95Sn/5Sb 0.12 90Sn/10Sb 18 Ａ ８ 75Sn/15Sb 14 − Ｃ ９ 75Sn/15Sb 30 − Ｃ 10 75Sn/15Sb 0.12 90Sn/10Sb 18 Ｂ 11 90Sn/10Sb 0.12 90Sn/10Sb 18 Ｂ 12 Ag 0.05 85Sn/15Sb 18 Ａ 13 − 85Sn/15Sb 18 Ａ ―――――――――――――――――――――――――――――――――― ＊表中、サンプル６および７の第２金属被膜は、上記の
ように、それぞれ２層膜および濃度分布を有する膜であ
り、いずれも表示左側が半導体素子に近い層（最も近い
部分）の組成、表示右側が半導体素子から遠い層（最も
遠い部分）の組成である。(Table 1) ―――――――――――――――――――――――――――――――――― Sample 2nd metal film Solder for joining Material Joining method Component weight [mg] Component weight [mg] ―――――――――――――――――――――――――――――――――― 1 100Sn 0.19 71Sn / 29Sb 18 A 2 95Sn / 5Sb 0.12 80Sn / 20Sb 12 A 3 91.5Sn / 8.5Sb 0.06 85Sn / 15Sb 18 A 4 90Sn / 10Sb 0.12 90Sn / 10Sb 18 A 5 85Sn / 15Sb 0.12 90Sn / 10Sb 18 A 6 70Sn / 30Sb-95Sn / 5Sb 0.12 90Sn / 10Sb 18 A 7 70Sn / 30Sb-95Sn / 5Sb 0.12 90Sn / 10Sb 18 A 8 75Sn / 15Sb 14-C 9 75Sn / 15Sb 30-C 10 75Sn / 15Sb 0.12 90Sn / 10Sb 18 B 11 90Sn / 10Sb 0.12 90Sn / 10Sb 18 B 12 Ag 0.05 85Sn / 15Sb 18 A 13 − 85Sn / 15Sb 18 A ―――――――――――――――――――――――――― ―――――――――― * In the table, the second metal films of Samples 6 and 7 are two-layer film and In each case, the left side of the display is the composition of the layer (closest portion) to the semiconductor element, and the right side is the composition of the layer farthest from the semiconductor element (the farthest portion).

【００４３】なお、表１において、第２の金属被膜の重
量０．１ｍｇは、ほぼ膜厚０．３μｍに相当する。ま
た、各サンプルとも、接合部の膜厚は、約３０μｍであ
った。In Table 1, the weight of the second metal coating of 0.1 mg corresponds to a thickness of about 0.3 μm. Further, in each sample, the film thickness of the joint portion was about 30 μm.

【００４４】こうして得た各半導体装置について、以下
の項目について評価した。 ・ボイドの状態：Ｘ線透視像によりボイド数を確認し
た。大きなボイドの発生の有無によって良否を判定し
た。 ・ΔＶｂｅ法による耐熱不良率；２７０℃に保持した３
７Ｐｂ／６３Ｓｎ合金中に１０秒間浸漬させた後の熱抵
抗値（４０Ｗの電力を０．１秒間印加）を測定し、ΔＶ
ｂｅ値が２５０ｍＶを超えたものを耐熱不良と判定し
た。この基準に基づき、各サンプルについて２０個の測
定を行い、その不良率を測定した。 ・耐熱温度；所定温度の３７Ｐｂ／６３Ｓｎ合金中に１
０秒間浸漬させた後の熱抵抗値（ΔＶｂｅ）を測定し、
ボイド観察を行った。浸漬前後でのΔＶｂｅ値およびボ
イドが変化しない上限温度を耐熱温度とした。さらに、
製造検査におけるΔＶｂｅ不良率と最終検査における熱
抵抗（ΔＶｂｅ）不良率を測定した。The following items were evaluated for each semiconductor device thus obtained. -Void state: The number of voids was confirmed by an X-ray fluoroscopic image. The quality was judged by the presence or absence of large voids.・ Heat resistance failure rate by ΔVbe method; held at 270 ° C. 3
The thermal resistance value (40 W of electric power was applied for 0.1 second) after immersion in a 7Pb / 63Sn alloy for 10 seconds was measured, and ΔV
Those having a be value of more than 250 mV were judged to have poor heat resistance. Based on this standard, 20 measurements were made for each sample and the defective rate was measured.・ Heat-resistant temperature; 1 in 37Pb / 63Sn alloy at specified temperature
Measure the thermal resistance value (ΔVbe) after soaking for 0 seconds,
Void observation was performed. The upper limit temperature at which the ΔVbe value before and after the immersion and the void did not change was defined as the heat resistant temperature. further,
The ΔVbe defect rate in the manufacturing inspection and the thermal resistance (ΔVbe) defect rate in the final inspection were measured.

【００４５】 （表２） ―――――――――――――――――――――――――――――――――― サンプル 接合部組成 耐熱温度 ボイド 製造検査時 ΔＶbe ［℃］ のΔＶbe 耐熱不良率 不良率[％] [％] ―――――――――――――――――――――――――――――――――― １ 71Sn/29Sb ２７０ ○ ０．５５ ０ ２ 80Sn/20Sb ２６５ ○ ０．５０ ５ ３ 85Sn/15Sb ２６０ ○ ０．４０ １５ ４ 90Sn/10Sb ２６０ ○ ０．４１ １５ ５ 90Sn/10Sb ２６０ ○ ０．３５ １０ ６ 90Sn/10Sb ２６０ ○ ０．３６ １５ ７ 90Sn/10Sb ２６０ ○ ０．３５ １０ ８ 85Sn/15Sb ２６０ ○ ０．４５ ２０ ９ 85Sn/15Sb ２６０ ○ ０．５０ ３０ 10 90Sn/10Sb ２６０ ○ ０．３０ １５ 11 90Sn/10Sb ２６０ ○ ０．３０ １０ 12 85Sn/15Sb ２４０ ○ ０．３０ １００ 13 85Sn/15Sb ２６０ × １２．５ １０ ――――――――――――――――――――――――――――――――――[0045]   (Table 2)   ――――――――――――――――――――――――――――――――――   Sample Joint composition Heat-resistant temperature Void Manufacturing inspection ΔVbe                              [° C] ΔVbe heat failure rate                                               Defect rate [%] [%]   ――――――――――――――――――――――――――――――――――       1 71Sn / 29Sb 270 ○ 0.55 0       2 80Sn / 20Sb 265 ○ 0.50 5       3 85Sn / 15Sb 260 ○ 0.40 15       4 90Sn / 10Sb 260 ○ 0.41 15       5 90Sn / 10Sb 260 ○ 0.35 10       6 90Sn / 10Sb 260 ○ 0.36 15       7 90Sn / 10Sb 260 ○ 0.35 10       8 85Sn / 15Sb 260 ○ 0.45 20       9 85Sn / 15Sb 260 ○ 0.50 30       10 90Sn / 10Sb 260 ○ 0.30 15       11 90Sn / 10Sb 260 ○ 0.30 10       12 85Sn / 15Sb 240 ○ 0.30 100       13 85Sn / 15Sb 260 x 12.5 10   ――――――――――――――――――――――――――――――――――

【００４６】サンプル１２では、第２の金属被膜として
Ａｇ膜を用いたため、耐熱温度が２４０℃にまで低下し
ている。サンプル１３では、第２の金属被膜を形成しな
かったため、ボイドの発生が顕著であった。ボイド２１
の発生が抑制された良好な接合面２２と大きなボイド２
１が発生している接合面２２（サンプル１３）とをＸ線
透視像で観察した結果を、それぞれ図７および図８とし
て示す。In Sample 12, since the Ag film was used as the second metal film, the heat resistance temperature was lowered to 240 ° C. In sample 13, since the second metal coating was not formed, the occurrence of voids was remarkable. Void 21
Good joint surface 22 and large void 2 in which the occurrence of cracks is suppressed
7 and 8 show the results of observing the joint surface 22 (Sample 13) in which 1 occurred with an X-ray fluoroscopic image, respectively.

【００４７】[0047]

【発明の効果】以上説明したように、本発明によれば、
鉛フリー化に伴う実装温度の上昇に対応できる耐熱性を
有し、かつ、はんだのぬれ性を改善して良好な接合特性
が得られる半導体装置を提供できる。As described above, according to the present invention,
It is possible to provide a semiconductor device having heat resistance capable of coping with an increase in mounting temperature due to lead-free, and improving solder wettability to obtain good bonding characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の半導体装置の製造方法の一形態を説
明するための断面図である。FIG. 1 is a sectional view for explaining one embodiment of a method for manufacturing a semiconductor device of the present invention.

【図２】 本発明の製造方法により接合された半導体素
子の状態を示す断面図である。FIG. 2 is a cross-sectional view showing a state of a semiconductor element bonded by the manufacturing method of the present invention.

【図３】 本発明の半導体装置の製造方法の別の一形態
を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining another mode of the method for manufacturing a semiconductor device of the present invention.

【図４】 本発明の半導体装置の製造方法のまた別の一
形態を説明するための断面図である。FIG. 4 is a cross-sectional view for explaining still another mode of the method for manufacturing a semiconductor device of the present invention.

【図５】 本発明の製造方法により得られる半導体装置
の一形態の断面図である。FIG. 5 is a cross-sectional view of one form of a semiconductor device obtained by the manufacturing method of the present invention.

【図６】 従来の半導体装置の製造方法を説明するため
の断面図である。FIG. 6 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

【図７】 本発明の製造方法により接合された接合面の
状態を示す図である。FIG. 7 is a diagram showing a state of a joint surface joined by the manufacturing method of the present invention.

【図８】 従来の製造方法により接合された接合面の状
態を示す図である。FIG. 8 is a diagram showing a state of a joint surface joined by a conventional manufacturing method.

【符号の説明】[Explanation of symbols]

１，１１ 半導体素子 ２ 第１の金属被膜 ３，８ 第２の金属被膜 ４ （接合用）はんだ材 ５ 金属被膜 ６，１６ リードフレーム ７，１７ 接合部 １２ 電極端子 １３ 封止樹脂 １４ 導体ワイヤ ２１ ボイド ２２ 接合面 1,11 Semiconductor element 2 First metal coating 3,8 Second metal coating 4 Soldering material (for joining) 5 metal coating 6,16 Lead frame 7,17 Joint 12 electrode terminals 13 Sealing resin 14 conductor wire 21 void 22 Bonding surface

───────────────────────────────────────────────────── フロントページの続き (72)発明者 室田 敏明 大阪府高槻市幸町１番１号 松下電子工 業株式会社内 (56)参考文献 特開 昭52−6468（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/52 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Murota 1-1 Sachimachi, Takatsuki City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd. (56) References JP-A-52-6468 (JP, A) (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/52

Claims (12)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体支持板との接合面となる表面に、
第１の金属被膜と第２の金属被膜とをこの順に形成した
半導体素子を作製し、前記半導体素子の前記接合面をは
んだ材を用いて前記半導体支持板上に接合するに際し、
前記はんだ材とともに前記第２の金属被膜を溶融して前
記第２の金属被膜を前記はんだ材に融合させて接合部を
形成する半導体装置の製造方法であって、前記第２の金
属被膜を錫またはアンチモンを含む被膜とし、前記接合
部を、錫を主成分とし、アンチモンを１０重量％以上含
有する合金とすることを特徴とする半導体装置の製造方
法。1. A surface to be a joint surface with a semiconductor support plate,
When a semiconductor element in which a first metal coating and a second metal coating are formed in this order is produced and the joining surface of the semiconductor element is joined onto the semiconductor support plate using a solder material,
A method of manufacturing a semiconductor device, wherein the second metal coating is melted together with the solder material to fuse the second metal coating with the solder material to form a joint portion, wherein the second metal coating is tin. Alternatively, a method of manufacturing a semiconductor device is characterized in that a coating film containing antimony is used, and the joint portion is made of an alloy containing tin as a main component and containing 10% by weight or more of antimony. 【請求項２】 第２の金属被膜を錫およびアンチモンを
含有する被膜とする請求項１に記載の半導体装置の製造
方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal film is a film containing tin and antimony. 【請求項３】 第２の金属被膜に、半導体素子に近くな
るほどアンチモンの濃度が高くなる濃度分布を付与する
請求項２に記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein the second metal film is provided with a concentration distribution in which the concentration of antimony increases as it gets closer to the semiconductor element. 【請求項４】 第２の金属被膜を多層膜とし、この多層
膜における半導体素子に最も近い層を、錫を主成分と
し、アンチモンを１５重量％以上含有する層とする請求
項２に記載の半導体装置の製造方法。4. The second metal coating is a multilayer film, and the layer closest to the semiconductor element in the multilayer film is a layer containing tin as a main component and antimony in an amount of 15% by weight or more. Manufacturing method of semiconductor device. 【請求項５】 第２の金属被膜およびはんだ材に、それ
ぞれ、錫およびアンチモンを含有させる請求項２〜４の
いずれかに記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 2, wherein the second metal coating and the solder material contain tin and antimony, respectively. 【請求項６】 接合部を２４０℃以上の融点を有する合
金とする請求項１〜５のいずれかに記載の半導体装置の
製造方法。6. The method of manufacturing a semiconductor device according to claim 1, wherein the joint is made of an alloy having a melting point of 240 ° C. or higher. 【請求項７】 第２の金属被膜の厚さを０．５μｍ以上
１０μｍ以下とする請求項１〜６のいずれかに記載の半
導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the second metal coating is 0.5 μm or more and 10 μm or less. 【請求項８】 接合部の厚さを１０μｍ以上４０μｍ以
下とする請求項１〜７のいずれかに記載の半導体装置の
製造方法。8. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the joint portion is 10 μm or more and 40 μm or less. 【請求項９】 半導体支持板との接合面となる表面に、
第１の金属被膜と、錫を主成分とし、アンチモンを１０
重量％以上含有する合金である第２の金属被膜とをこの
順に形成した半導体素子を作製し、前記半導体素子の前
記接合面を、前記第２の金属被膜を溶融して形成した接
合部により、前記半導体支持板上に接合する半導体装置
の製造方法であって、前記第２の金属被膜に、前記半導
体素子に 近くなるほどアンチモンの濃度が高くなる濃度
分布を付与することを特徴とする半導体装置の製造方
法。9. A surface to be a joint surface with a semiconductor support plate,
The first metal film and tin as a main component, antimony 10
A semiconductor element in which a second metal coating that is an alloy containing at least wt% is formed in this order, and the joint surface of the semiconductor element is formed by a joint formed by melting the second metal coating. Semiconductor device bonded on the semiconductor support plate
The method of manufacturing
Concentration of antimony increases as it gets closer to the body element
A method of manufacturing a semiconductor device, characterized by providing a distribution . 【請求項１０】 半導体支持板との接合面となる表面
に、第１の金属被膜と、錫を主成分とし、アンチモンを
１０重量％以上含有する合金である第２の金属被膜とを
この順に形成した半導体素子を作製し、前記半導体素子
の前記接合面を、前記第２の金属被膜を溶融して形成し
た接合部により、前記半導体支持板上に接合する半導体
装置の製造方法であって、前記第２の金属被膜を多層膜
とし、この多層膜における前記半導体素子に最も近い層
を、錫を主成分とし、アンチモンを１５重量％以上含有
する層とすることを特徴とする半導体装置の製造方法。10. A first metal film and a second metal film, which is an alloy containing tin as a main component and containing antimony in an amount of 10% by weight or more, are formed in this order on a surface to be a bonding surface with a semiconductor support plate. the formed semiconductor device manufactured, the said junction surface of the semiconductor element, the joint formed by melting the second metal film, a semiconductor joined to the semiconductor supporting board
A method for manufacturing a device, comprising:
And the layer closest to the semiconductor element in this multilayer film
Contains tin as a main component and contains antimony in an amount of 15% by weight or more.
A method for manufacturing a semiconductor device, comprising: 【請求項１１】 第２の金属被膜の厚さを１０μｍ以上
４０μｍ以下とする請求項９または１０に記載の半導体
装置の製造方法。11. The method according to claim 9 or 10 the thickness of the second metal film and 10μm or 40μm or less. 【請求項１２】 接合部を、２４０℃以上の融点を有す
る合金とする請求項９〜１１のいずれかに記載の半導体
装置の製造方法。12. The junction method of manufacturing a semiconductor device according to any of claims 9-11 to an alloy having a melting point of at least 240 ° C..
JP2000003103A 2000-01-12 2000-01-12 Method for manufacturing semiconductor device Expired - Fee Related JP3444832B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8944310B2 (en) * 2013-02-14 2015-02-03 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor device

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Publication number Priority date Publication date Assignee Title
US7644855B2 (en) 2002-09-19 2010-01-12 Sumitomo Metal Mining Co., Ltd. Brazing filler metal, assembly method for semiconductor device using same, and semiconductor device
JP2004119944A (en) * 2002-09-30 2004-04-15 Toyota Industries Corp Semiconductor module and mounting substrate
KR102133765B1 (en) 2017-10-31 2020-07-14 센주긴조쿠고교 가부시키가이샤 Solder joint and method of forming solder joint
EP4140635A1 (en) * 2021-08-31 2023-03-01 Infineon Technologies AG Semiconductor device with a ni comprising layer and method for fabricating the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8944310B2 (en) * 2013-02-14 2015-02-03 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor device

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