JP3395304B2 - Inspection method for semiconductor integrated circuit - Google Patents
Inspection method for semiconductor integrated circuitInfo
- Publication number
- JP3395304B2 JP3395304B2 JP31629393A JP31629393A JP3395304B2 JP 3395304 B2 JP3395304 B2 JP 3395304B2 JP 31629393 A JP31629393 A JP 31629393A JP 31629393 A JP31629393 A JP 31629393A JP 3395304 B2 JP3395304 B2 JP 3395304B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- burn
- wafer
- pad
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路のウエハ
状態での一括検査及びバーンインスクリーニングを行う
ための検査方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection method for performing a batch inspection and a burn-in screening in a wafer state of a semiconductor integrated circuit.
【０００２】[0002]
【従来の技術】近年、半導体集積回路装置を登載した電
子機器の小型化・低価格化の進歩は目ざましく、半導体
集積回路装置に対しても小型化低下価格化の要求が強
い。通常半導体集積回路装置は樹脂またはセラミクスに
モールドされた形で供給されプリント基板に実装される
が、電子機器の小型化の要求からベアチップを直接回路
基板に実装する方法が開発され、品質保証された半導体
集積回路ベアチップの低価格での供給が望まれている。
しかしながら現状の品質保証は、樹脂またはセラミクス
にモールドされた後バーンインスクリーニングを行うこ
とで行われており、ベアチップでの品質保証を行う為に
は、ウエハ状態またはベアチップ状態でこのバーンイン
を行う必要がある。しかしベアチップでのバーンインは
ウエハ状態でのバーンインに比べ、取扱が非常に複雑に
なり低価格化の要求に答えられない。そこでウエハ状態
でのバーンインスクリーニングをおこなうことが重要と
なる。2. Description of the Related Art In recent years, there have been remarkable advances in miniaturization and cost reduction of electronic equipment incorporating semiconductor integrated circuit devices, and there is a strong demand for miniaturization and price reduction of semiconductor integrated circuit devices. Normally, semiconductor integrated circuit devices are supplied in a form molded in resin or ceramics and mounted on a printed circuit board. However, due to the demand for miniaturization of electronic devices, a method for directly mounting a bare chip on a circuit board has been developed and its quality has been guaranteed. It is desired to supply bare chips of a semiconductor integrated circuit at a low price.
However, current quality assurance is performed by performing burn-in screening after molding in resin or ceramics, and in order to perform quality assurance with bare chips, it is necessary to perform this burn-in in a wafer state or bare chip state. . However, the burn-in with bare chips is much more complicated to handle than the burn-in with a wafer, and it cannot meet the demand for cost reduction. Therefore, it is important to perform burn-in screening in a wafer state.
【０００３】ウエハ状態でのバーンインを行うには、同
一ウエハ上に形成された複数のチップに同時に電源や信
号を印加し動作させる必要がある。しかしながらこれら
の電源や信号を各々のチップに対し独立に供給する為に
は何千何万もの配線をウエハ上から引き回す必要があり
コスト的な点から現実的でない。そこでできるだけ多く
の電極を共通化し独立して引き出す必要のある配線の数
を減らす必要がある。しかしながら配線を共通化するこ
とにより、共通配線されたチップの１つに異常電流が流
れたりすると、他のチップにもその影響が及び、正常な
バーンインを実施することが困難となる。これを解決す
るためには、異常なチップを共通配線から電気的に切り
放す必要がある。In order to perform burn-in in a wafer state, it is necessary to simultaneously apply power and signals to a plurality of chips formed on the same wafer to operate them. However, in order to independently supply these power supplies and signals to the respective chips, it is necessary to route tens of thousands of wirings from the wafer, which is not practical in terms of cost. Therefore, it is necessary to reduce the number of wirings that need to be shared by as many electrodes as possible and lead independently. However, by making the wiring common, if an abnormal current flows in one of the commonly wired chips, the influence is exerted on the other chips, and it becomes difficult to perform normal burn-in. In order to solve this, it is necessary to electrically disconnect the abnormal chip from the common wiring.
【０００４】以下図面を参照しながら、上記した従来の
ウエハ状態でのバーンインスクリーニングの一例とし
て、例えば、特開平１−２２７４６７号公報に記載され
たものについて説明する。An example of the above-mentioned conventional burn-in screening in a wafer state will be described below with reference to the drawings, for example, the one disclosed in Japanese Patent Laid-Open No. 1-227467.
【０００５】図４は半導体基板（ウエハ）上に複数個形
成された半導体集積回路（以下チップと略す）の１つを
示したもので、従来の半導体集積回路の検査方法を説明
するものである。図４において、４０はチップ、４３は
チップの電源パッド、４４はチップのＧＮＤパッドを示
す。４１はバーンイン用電源パッド、４２はＰチャンネ
ルトランジスタで、そのドレインはバーンイン用電源パ
ッド４１に、ソースはチップ４０の電源パッド４３に接
続されている。４５ａはトランジスタ１０のゲートに接
続されたパッドである。４５ｂ、４５ｃはそれぞれパッ
ド４５ａと細い（例えば３ｕｍ幅）アルミパターンで接
続されたパッドである。４６ａはチップ２のＧＮＤパッ
ド４４とパッド４５ｂとの間に設けられた抵抗であり、
その抵抗値は比較的低い値（例えば１０ｋΩ）となって
いる。４６ｂはバーンイン用電源パッド９とパッド４５
ｃとの間に設けられた抵抗であり、その抵抗値は比較的
高い値（例えば１００ｋΩ）となっている。FIG. 4 shows one of a plurality of semiconductor integrated circuits (hereinafter abbreviated as chips) formed on a semiconductor substrate (wafer), and illustrates a conventional method for inspecting a semiconductor integrated circuit. . In FIG. 4, 40 is a chip, 43 is a power supply pad of the chip, and 44 is a GND pad of the chip. 41 is a burn-in power supply pad, 42 is a P-channel transistor, and its drain is connected to the burn-in power supply pad 41 and its source is connected to the power supply pad 43 of the chip 40. 45a is a pad connected to the gate of the transistor 10. 45b and 45c are pads connected to the pad 45a by a thin (for example, 3 μm wide) aluminum pattern. 46a is a resistor provided between the GND pad 44 and the pad 45b of the chip 2,
The resistance value is relatively low (for example, 10 kΩ). 46b is a burn-in power supply pad 9 and a pad 45
It is a resistance provided between the resistance c and c, and its resistance value is relatively high (for example, 100 kΩ).
【０００６】次に従来の動作について図４を用いて説明
する。まずバーンイン前のウエハテストについては、外
部測定装置（図示せず）に接続された固定プローブ針
（図示せず）でチップ４０のパッド４６ａ、４６ｂ、４
５ａ、４５ｂ，４５ｃ及び他の必要パッド（図示せす）
へプロービングする。外部測定装置によりパッド４３に
電源電圧、パッド４４及びパッド４１をＧＮＤ、パッド
４５ａに”Ｈ”レベルを与える。この条件のもとでは該
チップのトランジスタ４３はオフ状態であるためパッド
４３とパッド４１との間に電流は流れずチップ４０の試
験が可能である。試験結果、該チップが良品であれば直
ちに次のチップへ移動し、不良品であれば、パッド４５
ａとパッド４５ｂとの間に外部測定装置により大電流
（例えば１００ｍＡ）を流してパッド４５ａとパッド４
５ｂとの間の細いアルミパターンを溶解させ、次のチッ
プへ移動する。Next, the conventional operation will be described with reference to FIG. First, for the wafer test before burn-in, the pads 46a, 46b, 4 of the chip 40 are fixed by a fixed probe needle (not shown) connected to an external measuring device (not shown).
5a, 45b, 45c and other necessary pads (not shown)
Probing to. An external measuring device supplies a power supply voltage to the pad 43, GND to the pads 44 and 41, and “H” level to the pad 45a. Under this condition, since the transistor 43 of the chip is in the off state, no current flows between the pad 43 and the pad 41, and the chip 40 can be tested. As a result of the test, if the chip is a non-defective product, the chip immediately moves to the next chip.
A large current (for example, 100 mA) is caused to flow between a and the pad 45b by an external measuring device, and the pads 45a and 4
The thin aluminum pattern between 5b and 5b is melted and moved to the next chip.
【０００７】このようにバーンイン前のウエハテストを
行うことにより、バーンイン時に各チップに共通に接続
されたバーンイン用電源パッド４１に電圧が印加された
場合、良品と判定されたチップは、トランジスタ４２の
ゲート電位が抵抗４６ａ、４６ｂの比により決定され
る。ここでは抵抗４６ａに比して抵抗４６ｂの方の抵抗
値が十分大きいため電位は”Ｌ”レベルとなりトランジ
スタ４２はオン状態となる。そのためバーンイン電圧は
トランジスタ４２を通してチップの電源パッド４３に供
給される。一方該チップがバーンイン前の試験で不良品
と判定されたチップは、パッド４５ａとパッド４５ｂと
の間は溶断され、解放となるため、トランジスタ４２の
ゲート電位は”Ｈ”レベルとなりトランジスタ４２はオ
フ状態となる。そのためバーンイン電圧はチップ４０の
電源パッド４３に供給されず電流は全く流れない。By performing the wafer test before burn-in in this way, when a voltage is applied to the burn-in power supply pad 41 commonly connected to each chip at the time of burn-in, the chip determined to be a non-defective one is the transistor 42. The gate potential is determined by the ratio of the resistors 46a and 46b. Here, since the resistance value of the resistor 46b is sufficiently larger than that of the resistor 46a, the potential becomes "L" level and the transistor 42 is turned on. Therefore, the burn-in voltage is supplied to the power supply pad 43 of the chip through the transistor 42. On the other hand, if the chip is judged to be defective in the test before burn-in, the pad 45a and the pad 45b are fused and released, so that the gate potential of the transistor 42 becomes "H" level and the transistor 42 is turned off. It becomes a state. Therefore, the burn-in voltage is not supplied to the power supply pad 43 of the chip 40 and no current flows.
【０００８】このようにして、電源不良チップに対し共
通に接続されたバーンイン用電源パッド９に同時に電圧
を印加しても、不良チップに対しては電源電流は流れ
ず、その他の良品チップのバーンインに対して悪影響を
及ぼすことがない。In this way, even if a voltage is simultaneously applied to the burn-in power supply pads 9 commonly connected to the defective chips, the power supply current does not flow to the defective chips, and the burn-in of other good chips is performed. Does not have an adverse effect on.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、余計な素子（トランジスタ４２、抵抗４
６ａ・４６ｂ、パッド４１・４５ａ・４５ｂ・４５ｃ、
ヒューズとしてのアルミ配線）を同一チップ内に形成す
る必要があるばかりでなく、このためにバーンイン時に
トランジスタ４２を介して電圧を印加することになり、
共通電源パッド４１に印加された電圧がそのまま内部電
源に印加されず電圧降下を引き起こすなどの問題点を有
していた。However, in the above structure, extra elements (transistor 42, resistor 4
6a / 46b, pads 41 / 45a / 45b / 45c,
Aluminum wiring as a fuse) must be formed in the same chip, and for this reason, a voltage is applied via the transistor 42 at the time of burn-in.
The voltage applied to the common power supply pad 41 is not applied to the internal power supply as it is, causing a voltage drop.
【００１０】本発明は上記問題点に鑑み、簡便でかつ確
実に不良チップへの電源供給を遮断する半導体集積回路
の検査方法及び検査装置を提供するものである。In view of the above problems, the present invention provides a method and an apparatus for inspecting a semiconductor integrated circuit, which simply and surely cut off the power supply to a defective chip.
【００１１】[0011]
【課題を解決するための手段】上記問題点を解決するた
めに本発明の半導体集積回路の検査方法は、試験の前に
各チップを事前検査する工程と、事前検査の結果不具合
いが検出されたチップに対し、各チップの各電極に対し
共通の電源線または信号線の接続される電極部分を覆う
ように不導体層を形成する工程と、その後、各チップの
各電極に対し共通の電源線または信号線を有するプロー
ブ手段により同一ウエハ上に同時形成された半導体装置
の少なくとも一部を同時に試験する工程とを備えたもの
である。In order to solve the above problems, a semiconductor integrated circuit inspection method of the present invention includes a step of pre-inspecting each chip before the test, and a defect is detected as a result of the pre-inspection. chips to, and forming a nonconductive layer so as to cover the connected thereto electrode portion <br/> common power line or a signal line to the electrodes of each chip, then the chips
And a step of simultaneously testing at least a part of semiconductor devices simultaneously formed on the same wafer by a probe means having a common power supply line or signal line for each electrode .
【００１２】[0012]
【作用】本発明は上記した構成によって、不良チップの
電源線または信号線の接続される電極部分を覆うように
硬化性不導体液を塗布することにより、余計なスイッチ
ング素子を介することなく確実かつ簡便に電源供給を遮
断することが可能となる。また、余計なスイッチング素
子を設けることなく電源線のみならず任意の信号線に対
しても電気的接続を断つことができる。According to the present invention, with the above-described structure, the curable non-conductive liquid is applied so as to cover the electrode portion of the defective chip to which the power supply line or the signal line is connected. It is possible to easily cut off the power supply. Further, it is possible to disconnect the electrical connection not only to the power supply line but also to an arbitrary signal line without providing an extra switching element.
【００１３】[0013]
【実施例】以下本発明の一実施例の半導体装置の検査方
法について、図面を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device inspection method according to an embodiment of the present invention will be described below with reference to the drawings.
【００１４】図１は本発明の実施例における半導体装置
のウエハ状態を示すものである。図１において、１はウ
エハ、２はチップ、３はスクライブライン、４は電源パ
ッド、５は不導体樹脂塗布部を示す。図２は図１のウエ
ハ上に複数個同時形成されたチップのうちの１つを示す
ものである。図２において、６はＧＮＤパッド、１０は
他の信号線パッドを示す。図３は電源パッド部分とプロ
ーブカードの接触部分の断面を示す図である。同図
（ａ）は良品チップの接続状態を示し、（ｂ）は不良チ
ップの接続を遮断した部分を示す。５は不導体樹脂を示
し、７はポリイミド基板、８はプローブカード配線、８
ａはバンプ、９は半導体装置の表面保護膜を示す。FIG. 1 shows a wafer state of a semiconductor device according to an embodiment of the present invention. In FIG. 1, 1 is a wafer, 2 is a chip, 3 is a scribe line, 4 is a power supply pad, and 5 is a non-conductive resin coating portion. FIG. 2 shows one of a plurality of chips simultaneously formed on the wafer of FIG. In FIG. 2, 6 is a GND pad and 10 is another signal line pad. FIG. 3 is a view showing a cross section of a contact portion between the power supply pad portion and the probe card. FIG. 7A shows a connection state of non-defective chips, and FIG. 9B shows a portion in which connection of a defective chip is cut off. 5 is a non-conductive resin, 7 is a polyimide substrate, 8 is a probe card wiring, 8
Reference numeral a denotes a bump, and 9 denotes a surface protective film of the semiconductor device.
【００１５】まずバーンイン前のウエハテストについて
図１を用いて説明する。外部測定装置（図示せず）に接
続された固定プローブ針（図示せず）でチップ２の電源
パッド４及びその他の必要パッド１０（図２参照）にプ
ロービングする。外部測定装置によりプロービングした
パッドを通し必要なバーンイン前ウエハテストを実施す
る。バーンイン前ウエハテストでは電源、ＧＮＤ間のシ
ョート及び各パッドの電源・ＧＮＤとのショートを中心
に、簡単な動作試験及び内部に自己試験回路（ＢＩＳＴ
回路）を有しこれによりバーンインを行う場合はこの回
路の試験等を行う。この試験の結果不良品と判断された
チップには、電源パッド４に不導体樹脂を塗布する。不
導体樹脂は揮発性溶剤に解けたもので塗布後乾燥するし
た時の体積収縮率の大きいものが好ましい。これは、不
導体樹脂層の膜厚を薄膜化しやすい為である。First, a wafer test before burn-in will be described with reference to FIG. A fixed probe needle (not shown) connected to an external measuring device (not shown) is used to probe the power supply pad 4 of the chip 2 and other necessary pads 10 (see FIG. 2). Perform the required pre-burn-in wafer test through the pad probed by an external measuring device. In the pre-burn-in wafer test, a simple operation test and internal self-test circuit (BIST) centering on the short circuit between the power supply and GND and the power supply / GND of each pad.
If a circuit is provided and burn-in is performed using this circuit, the circuit is tested. The power supply pad 4 is coated with a non-conductive resin on the chip determined to be defective as a result of this test. The non-conductive resin is preferably a resin that is dissolved in a volatile solvent and has a large volume shrinkage when dried after coating. This is because it is easy to reduce the thickness of the non-conductive resin layer.
【００１６】不導体樹脂の塗布方法としては、通常不良
チップにマーキングを行うマーカを使用する。また、同
一チップ内に複数箇所不導体樹脂を塗布する必要がある
場合には、マーカを複数個用意するか、ウェハまたはマ
ーカを移動させる事により塗布する。不導体樹脂は従来
の不良チップのマーキングの際と同様に赤色などで着色
したものを用いる事で不良チップの選別と共用する事が
できる。As a method of applying the non-conductive resin, a marker for marking a defective chip is usually used. When it is necessary to apply the non-conductive resin to the same chip at a plurality of locations, a plurality of markers are prepared or the wafer or the markers are moved to apply the resin. The non-conductive resin can be shared with the selection of the defective chips by using the one colored with red or the like as in the conventional marking of the defective chips.
【００１７】次にバーンインについて説明する。バーン
イン時にはウエハ全面を同時にプロービングするためシ
ート状の基板に配線層とパッドへのコンタクトを取るた
めのバンプを形成したプローブカードを用いる。バーン
イン時のプローブカードを図５に示す。同図（ａ）はプ
ローブカードの全体を示すもので、１はウエハ、２はチ
ップ、５０はプローブカード基板、５５は配線層を示
す。また同図（ｂ）は１チップ箇所のプローブカードの
拡大図であり、５１は電源配線、５２はＧＮＤ配線、５
３は各チップ独立の信号線、５４ａ〜ｄは各チップ共通
の信号線、５６はウエハ１との接続を行うために形成さ
れたバンプ部分を示す。基板材料としては比較的熱膨張
係数が小さく設計されたポリイミド系材料や負の膨張係
数をもつアラミド等が好ましい。Next, burn-in will be described. At the time of burn-in, a probe card in which bumps for making contact with a wiring layer and a pad are formed on a sheet-shaped substrate is used for probing the entire surface of the wafer at the same time. The probe card at the time of burn-in is shown in FIG. FIG. 1A shows the entire probe card, where 1 is a wafer, 2 is a chip, 50 is a probe card substrate, and 55 is a wiring layer. Further, FIG. 2B is an enlarged view of the probe card at one chip portion, 51 is power wiring, 52 is GND wiring, 5
3 is a signal line independent of each chip, 54a to d are signal lines common to each chip, and 56 is a bump portion formed for connection with the wafer 1. As the substrate material, a polyimide material designed to have a relatively small thermal expansion coefficient or aramid having a negative expansion coefficient is preferable.
【００１８】このプローブカードをシリコンゴムの様な
柔らかいものでウエハに押し当てる事によりウエハ全面
の同時プロービングを行う。この際図３（ｂ）に示すよ
うに、前述のバーンイン前ウエハテストにおいて不良と
判断されたチップは電源パッド４に不導体樹脂５が塗布
されているためバンプ１１が直接電源パッド４に接続さ
れることがない。一方良品と判断されたチップは図３
（ａ）に示すようにバンプは電源パッド４に接続されチ
ップ２は電源が供給される。このようにして良品と不良
品が混在したウエハの良品チップのみバーンインが可能
となる。Simultaneous probing of the entire surface of the wafer is performed by pressing the probe card against the wafer with a soft material such as silicon rubber. At this time, as shown in FIG. 3B, since the non-conductive resin 5 is applied to the power supply pad 4 of the chip judged to be defective in the pre-burn-in wafer test, the bump 11 is directly connected to the power supply pad 4. Never. On the other hand, the chips judged to be non-defective are shown in Fig. 3.
As shown in (a), the bump is connected to the power supply pad 4 and the chip 2 is supplied with power. In this way, burn-in can be performed only on non-defective chips of a wafer in which non-defective products and defective products are mixed.
【００１９】以上のように本実施例によれば、各チップ
の各電極に対し共通の電源線または信号線を有するプロ
ーブ手段により同一ウエハ上に同時形成された半導体の
少なくとも一部を同時にバーンイン等の試験を行う方法
において、バーンイン前ウエハテストの結果不良と判断
されたチップに対し、前記各チップの各電極に対し共通
の電源線または信号線の接続されるパッド部分の一部ま
たは全てを覆うように不導体層を形成する工程を備える
ことにより、不良チップへの電源及び信号の供給を遮断
し、良品チップのみ電圧を供給することができる。As described above, according to this embodiment, each chip
In the method of simultaneously performing a test such as burn-in on at least a part of semiconductors simultaneously formed on the same wafer by the probe means having a common power supply line or signal line for each electrode, it is determined as a result of a wafer test before burn-in. A defective chip by providing a step of forming a non-conductive layer on the formed chip so as to cover a part or all of a pad portion to which a common power line or signal line is connected to each electrode of each chip. It is possible to cut off the power supply and the signal supply to the chip and supply the voltage only to the non-defective chip.
【００２０】[0020]
【発明の効果】以上のように本実施例によれば、各チッ
プの各電極に対し共通の電源線または信号線を有するプ
ローブ手段により同一ウエハ上に同時形成された半導体
の少なくとも一部を同時にバーンイン等の試験を行う方
法において、バーンイン前ウエハテストの結果不良と判
断されたチップに対し、前記各チップの各電極に対し共
通の電源線または信号線の接続されるパッド部分の一部
または全てを覆うように不導体層を形成する工程を備え
ることにより、不良チップへの電源及び信号の供給を遮
断し、良品チップのみ電圧を供給することができる。As described above, according to this embodiment, at least a part of the semiconductors simultaneously formed on the same wafer is simultaneously formed by the probe means having the common power supply line or signal line for each electrode of each chip. In a method of performing a test such as burn-in, for a chip determined to be defective as a result of a wafer test before burn-in, a pad portion to which a common power line or signal line is connected to each electrode of each chip By providing the step of forming the non-conductive layer so as to cover a part or all of the above, it is possible to cut off the power supply and the signal supply to the defective chip and supply the voltage only to the non-defective chip.
【図１】本発明の第１の実施例におけるウエハバーンイ
ン用ウエハを示す図FIG. 1 is a diagram showing a wafer for wafer burn-in according to a first embodiment of the present invention.
【図２】同実施例のウエハバーンイン用ウエハのチップ
を説明するための拡大図FIG. 2 is an enlarged view for explaining a chip of the wafer for wafer burn-in of the same embodiment.
【図３】同実施例における動作説明のための半導体集積
回路装置のパッド部分の拡大図FIG. 3 is an enlarged view of a pad portion of the semiconductor integrated circuit device for explaining the operation in the embodiment.
【図４】従来のウエハバーンイン用ウエハの半導体集積
回路装置の動作説明図FIG. 4 is an operation explanatory view of a conventional semiconductor integrated circuit device for a wafer for wafer burn-in.
【図５】本発明の第１の実施例におけるウエハバーンイ
ン用のプローブカードを示す構成図FIG. 5 is a configuration diagram showing a probe card for wafer burn-in according to the first embodiment of the present invention.
１ ウエハ ２ 半導体集積回路装置（チップ） ３ スクライブライン ４ 電源パッド ５ 不導体樹脂塗布部 ７ プローブカード基板（ポリイミド基板） １１ バンプ 1 wafer 2 Semiconductor integrated circuit device (chip) 3 scribe lines 4 power pad 5 Non-conductive resin coating part 7 Probe card board (polyimide board) 11 bumps
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−122537（ＪＰ，Ａ) 特開 平１−218037（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/66 G01R 31/26 G01R 31/28 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-122537 (JP, A) JP-A 1-218037 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/66 G01R 31/26 G01R 31/28
Claims (2)
と、事前検査の結果不具合いが検出されたチップに対
し、各チップの各電極に対し共通の電源線または信号線
の接続される電極部分を覆うように不導体層を形成する
工程と、その後、各チップの各電極に対し共通の電源線
または信号線を有するプローブ手段により同一ウエハ上
に同時形成された半導体装置の少なくとも一部を同時に
試験する工程とを備えた半導体集積回路の検査方法。1. A step of pre-inspecting each chip before the test, and a common power line or signal line is connected to each electrode of each chip for the chip in which a defect is detected as a result of the pre-inspection. A step of forming a non-conductive layer so as to cover the electrode portion, and thereafter, at least a part of a semiconductor device simultaneously formed on the same wafer by a probe means having a common power supply line or signal line for each electrode of each chip. A method for inspecting a semiconductor integrated circuit, comprising:
溶剤を塗布しこれを硬化させることによりこの不導体層
を形成することを特徴とする請求項１記載の半導体集積
回路の検査方法。2. The method for inspecting a semiconductor integrated circuit according to claim 1, wherein in the step of forming the non-conductor layer, the non-conductor layer is formed by applying a liquid solvent and curing the solvent. .
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31629393A JP3395304B2 (en) | 1993-12-16 | 1993-12-16 | Inspection method for semiconductor integrated circuit |
| KR1019940032588A KR0140034B1 (en) | 1993-12-16 | 1994-12-02 | Semiconductor wafer case, connection method and apparatus, and inspection method for semiconductor integrated circuit, probe card, and its manufacturing method |
| US08/609,150 US5945834A (en) | 1993-12-16 | 1996-02-29 | Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method |
| US08/837,954 US6005401A (en) | 1993-12-16 | 1997-04-14 | Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method |
| US09/396,884 US6323663B1 (en) | 1993-12-16 | 1999-09-16 | Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31629393A JP3395304B2 (en) | 1993-12-16 | 1993-12-16 | Inspection method for semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07169806A JPH07169806A (en) | 1995-07-04 |
| JP3395304B2 true JP3395304B2 (en) | 2003-04-14 |
Family
ID=18075505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31629393A Expired - Lifetime JP3395304B2 (en) | 1993-12-16 | 1993-12-16 | Inspection method for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3395304B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3142801B2 (en) | 1997-09-04 | 2001-03-07 | 松下電器産業株式会社 | Inspection method for semiconductor integrated circuit, probe card and burn-in board |
| EP2273279A1 (en) | 2005-04-27 | 2011-01-12 | Aehr Test Systems, Inc. | Apparatus for testing electronic devices |
| KR100655689B1 (en) | 2005-08-30 | 2006-12-08 | 삼성전자주식회사 | Probe method, probe card used for the probe method, and probe apparatus having the probe card for performing the method |
| JP5379527B2 (en) | 2009-03-19 | 2013-12-25 | パナソニック株式会社 | Semiconductor device |
| TWI729056B (en) * | 2016-01-08 | 2021-06-01 | 美商艾爾測試系統 | Tester apparatus and method of testing microelectronic devices |
| KR20230021177A (en) | 2017-03-03 | 2023-02-13 | 에어 테스트 시스템즈 | Electronics tester |
| CN116457670A (en) | 2020-10-07 | 2023-07-18 | 雅赫测试***公司 | Electronic tester |
-
1993
- 1993-12-16 JP JP31629393A patent/JP3395304B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07169806A (en) | 1995-07-04 |
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