JP3362566B2 - Method of forming Si3N4 film - Google Patents
Method of forming Si3N4 filmInfo
- Publication number
- JP3362566B2 JP3362566B2 JP17445395A JP17445395A JP3362566B2 JP 3362566 B2 JP3362566 B2 JP 3362566B2 JP 17445395 A JP17445395 A JP 17445395A JP 17445395 A JP17445395 A JP 17445395A JP 3362566 B2 JP3362566 B2 JP 3362566B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- mask pattern
- photoresist
- sulfuric acid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＭＩＳ型半導体素子の
絶縁膜として好適に使用されるＳｉ3 Ｎ4 膜を半導体基
板上に形成する方法に関し、更に詳細には、熱硫酸過水
でウェハを洗浄して、Ｓｉ3 Ｎ4 膜をパターニングした
時にマスクとして使用したレジスト膜を除去する際に、
Ｓｉ3 Ｎ4 膜の膜べりを抑制することができるＳｉ3 Ｎ
4 膜の形成方法及び膜減りのないＳｉ3 Ｎ4 膜を有する
ＭＩＳ型半導体素子に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a Si 3 N 4 film, which is preferably used as an insulating film of a MIS type semiconductor device, on a semiconductor substrate, and more specifically, to a wafer using hot sulfuric acid / hydrogen peroxide mixture. And removing the resist film used as a mask when patterning the Si 3 N 4 film,
Si 3 and N 4 film of film loss can be suppressed Si 3 N
It relates MIS type semiconductor device having a 4 layer forming method and film reduction without the Si 3 N 4 film of.
【０００２】[0002]
【従来の技術】ＭＩＳキャパシタ（Capacitor)の半導体
基板上に形成される絶縁膜（誘電体）として、従来から
Ｓｉ3 Ｎ4 膜が採用されている。従来のＳｉ3 Ｎ4 膜形
成方法は、図５（ａ）に示すように、半導体基板１０上
にＳｉ3 Ｎ4 膜１８をＣＶＤ法により形成し、次いで、
図５（ｂ）に示すように、ホトレジスト膜のマスクパタ
ーン２２を形成した後、Ｓｉ3 Ｎ4 膜１８をエッチング
する。次に、マスクとして使用したホトレジスト膜２２
を熱硫酸過水で除去して、図５（ｃ）に示すように、基
板１０上の電極形成領域１６にパターニングされたＳｉ
3 Ｎ4 膜１８を得ている。図５中、１２はＬＯＣＯＳ
膜、１４はＳｉＯ2 膜である。2. Description of the Related Art A Si 3 N 4 film has been conventionally used as an insulating film (dielectric) formed on a semiconductor substrate of a MIS capacitor (Capacitor). As shown in FIG. 5A, a conventional Si 3 N 4 film forming method is to form a Si 3 N 4 film 18 on a semiconductor substrate 10 by a CVD method, and then,
As shown in FIG. 5B, after the mask pattern 22 of the photoresist film is formed, the Si 3 N 4 film 18 is etched. Next, the photoresist film 22 used as a mask
Is removed by hot sulfuric acid / hydrogen peroxide mixture, and Si patterned on the electrode forming region 16 on the substrate 10 is formed as shown in FIG.
A 3 N 4 film 18 is obtained. In FIG. 5, 12 is LOCOS
The film, 14 is a SiO 2 film.
【０００３】[0003]
【発明が解決しようとする課題】従来のＳｉ3 Ｎ4 膜の
形成方法では、ホトレジスト膜を除去するために１２０
°C から１４０°C の温度範囲にあるボイル状態の熱硫
酸過水でウェハを洗浄しようとすると、Ｓｉ3 Ｎ4 膜が
熱硫酸過水により侵されて、膜減りが著しく、膜厚が
０．１ｎｍ〜１．０ｎｍ位減少すると言う問題があっ
た。According to the conventional method of forming a Si 3 N 4 film, it is necessary to remove 120 in order to remove the photoresist film.
When the wafer is cleaned with hot sulfuric acid / hydrogen peroxide solution in the boiling state in the temperature range of ° C to 140 ° C, the Si 3 N 4 film is attacked by the hot sulfuric acid / hydrogen peroxide solution, and the film thickness is significantly reduced. There was a problem that it decreased by about 1 nm to 1.0 nm.
【０００４】ところで、膜減り量が大きいと、第１に
は、ＭＩＳ型半導体素子にデバイス特性のバラツキが発
生する。ＭＩＳ型半導体素子、例えばＭＩＳキャパシタ
に正確な静電容量を与えるためには、誘電体として使用
されるＳｉ3 Ｎ4 膜を正確に設定膜厚で形成することが
必要であるが、膜減り量が大きいと正確に設定膜厚に形
成することができないので、静電容量が所定値から変化
してしまう。第２には、ホトリソグラフィ工程での問題
である。例えば、ホトリソグラフィ工程において予期し
ない事情が発生して露光操作をやり直す必要が生じた場
合でも、膜減り量が大きいと、Ｓｉ3 Ｎ4 膜の膜厚が減
少するために、ホトリソグラフィ工程を再実施すること
が難しいと言う問題があった。By the way, if the amount of film reduction is large, firstly, variations in device characteristics occur in the MIS type semiconductor element. In order to give an accurate capacitance to a MIS type semiconductor device, for example, a MIS capacitor, it is necessary to form a Si 3 N 4 film used as a dielectric with an accurately set film thickness. If it is large, the film thickness cannot be accurately formed to the set film thickness, so that the capacitance changes from the predetermined value. Second, there is a problem in the photolithography process. For example, even if an unexpected situation occurs in the photolithography process and it is necessary to repeat the exposure operation, if the film reduction amount is large, the film thickness of the Si 3 N 4 film is reduced, and therefore the photolithography process is restarted. There was a problem that it was difficult to implement.
【０００５】以上のような理由から、従来は、温度の低
い硫酸過水、即ちボイルしていない８０°C 前後の硫酸
過水でウェハを洗浄せざるを得なかった。しかし、従来
は、ボイルしていない硫酸過水を使用するために、ホト
レジストの剥離能力が低く、長時間の洗浄を必要とし、
しかも完全に除去できないと言う問題があった。換言す
れば、従来のＳｉ3 Ｎ4 膜形成方法では、硫酸過水の洗
浄によりホトレジストを除去する際に、高い温度のボイ
ル状態の熱硫酸過水を使用して洗浄効率を上げることが
難しかった。また、ボイルしていない硫酸過水を使用す
るために、薬役ライフも短く、コストが嵩むと言う問題
もあった。For the above reasons, conventionally, the wafer had to be washed with a sulfuric acid / hydrogen peroxide mixture having a low temperature, that is, a sulfuric acid / hydrogen peroxide mixture at about 80 ° C. without boiling. However, in the past, since unboiled sulfuric acid / hydrogen peroxide was used, the photoresist stripping ability was low, requiring long-term cleaning,
Moreover, there was a problem that it could not be completely removed. In other words, in the conventional Si 3 N 4 film forming method, when removing the photoresist by washing with sulfuric acid / hydrogen peroxide, it is difficult to increase the washing efficiency by using hot sulfuric acid / hydrogen peroxide in a high temperature boil state. . In addition, since unsoiled sulfuric acid / hydrogen peroxide is used, the medicinal life is short and the cost is high.
【０００６】そこで、本発明の目的は、熱硫酸過水でウ
ェハを洗浄して、Ｓｉ3Ｎ4膜をパターニングした時にマ
スクとして使用したレジスト膜を除去する際に、Ｓｉ3
Ｎ4膜の膜減りを抑制することができるＳｉ3Ｎ4膜の形
成方法を提供することである。 An object of the present invention is to clean the wafer with thermal SPM, when removing the resist film used as a mask when patterning the the Si 3 N 4 film, Si 3
To provide a the Si 3 N 4 film formation method which can suppress N 4 film of film loss.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明に係るＳｉ3 Ｎ4 膜の形成方法は、Ｓｉ3Ｎ
4 膜を半導体基板上に形成する方法であって、Ｓｉ3 Ｎ
4 膜を半導体基板上に成膜する工程と、酸素プラズマ処
理又は熱酸化処理をウェハに施してＳｉ3 Ｎ4 膜の表面
を酸化し、Ｓｉ3 Ｎ4 膜の表面に極く薄いＳｉＯ2 膜を
形成する工程と、ホトレジスト膜のマスクパターンを形
成する工程と、マスクパターンをマスクにして薄いＳｉ
Ｏ2 膜及びＳｉ3 Ｎ4 膜をエッチングする工程と、熱硫
酸過水でマスクパターンのホトレジストを除去する工程
とを備えることを特徴としている。To achieve the above object, according to the Invention The method of forming the Si 3 N 4 film according to the present invention, Si 3 N
A method for forming four films on a semiconductor substrate, comprising: Si 3 N
4 a step of forming a film on a semiconductor substrate, an oxygen plasma treatment or thermal oxidation treatment by subjecting the wafer to oxidize the surface of the Si 3 N 4 film, a very thin SiO 2 film on the surface of the Si 3 N 4 film A step of forming a mask pattern of a photoresist film, and a step of forming a thin Si film using the mask pattern as a mask.
The method is characterized by including a step of etching the O 2 film and the Si 3 N 4 film and a step of removing the photoresist of the mask pattern with hot sulfuric acid / hydrogen peroxide mixture.
【０００８】酸素プラズマ処理は、プラズマアッシング
装置を使用して、通常のプラズマアッシング条件で処理
される。または、熱酸化処理は、熱酸化炉を使用し、温
度９００°C 前後で酸化処理することにより行われる。
Ｓｉ3 Ｎ4 膜表面に形成するＳｉＯ2 膜の膜厚は、極く
薄く、例えば１ｎｍ以下であって、処理時間を規制する
ことにより、ＳｉＯ2 膜の膜厚を所望の膜厚に制御でき
る。また、本発明方法で使用する熱硫酸過水は、ボイル
状態の硫酸過水であって、１２０°C から１４０°C の
温度範囲に設定する。これにより、ホトレジストの除去
作業の能率が、従来法に比べて格段に向上する。The oxygen plasma treatment is performed under normal plasma ashing conditions using a plasma ashing device. Alternatively, the thermal oxidation treatment is performed by using a thermal oxidation furnace at a temperature of about 900 ° C.
The film thickness of the SiO 2 film formed on the surface of the Si 3 N 4 film is extremely thin, for example, 1 nm or less, and the film thickness of the SiO 2 film can be controlled to a desired film thickness by regulating the processing time. . The hot sulfuric acid / hydrogen peroxide used in the method of the present invention is boiling sulfuric acid / hydrogen peroxide, and is set in the temperature range of 120 ° C to 140 ° C. As a result, the efficiency of the photoresist removing operation is significantly improved as compared with the conventional method.
【０００９】また、マスクパターンを除去する工程にお
いて、プラズマアッシング法によりマスクパターンを除
去し、更に熱硫酸過水で洗浄、除去することもできる。
本発明方法は、半導体基板と絶縁膜と電極とで構成され
るＭＩＳ型半導体素子の絶縁膜として使用されるＳｉ3
Ｎ4 膜の形成に好適に適用できる。Further, in the step of removing the mask pattern, the mask pattern may be removed by plasma ashing method, and then further washed and removed with hot sulfuric acid / hydrogen peroxide mixture.
According to the method of the present invention, Si 3 used as an insulating film of a MIS type semiconductor element composed of a semiconductor substrate, an insulating film and an electrode is used.
It can be suitably applied to the formation of N 4 film.
【００１０】[0010]
【００１１】[0011]
【実施例】以下、添付図面を参照し、実施例に基づいて
本発明をより詳細に説明する。図１（ａ）から（ｃ）及
び図２（ｄ）から（ｆ）は、それぞれＭＩＳキャパシタ
の絶縁膜としてＳｉ3 Ｎ4 膜を成膜するために本発明方
法を実施する際の各工程毎の基板層構造を示す断面図で
あり、図２（Ｉ）は図２（ｄ）に示すＳｉ3 Ｎ4 膜の拡
大断面図である。先ず、図１（ａ）に示すように、ＬＯ
ＣＯＳ膜１２が形成されている半導体基板１０に通常の
熱酸化法によりＳｉＯ2 膜１４を形成し、次いで、図１
（ｂ）に示すように、ＳｉＯ2 膜１４に窓を開けて、電
極形成領域１６とする。次いで、図１（ｃ）に示すよう
に、膜厚５０ｎｍになるようにＳｉ3 Ｎ4 膜１８を基板
１０全面に通常の条件でＣＶＤ法により形成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail based on embodiments with reference to the accompanying drawings. FIGS. 1 (a) to 1 (c) and FIGS. 2 (d) to (f) show each step in carrying out the method of the present invention for forming a Si 3 N 4 film as an insulating film of a MIS capacitor. 2 (I) is an enlarged cross-sectional view of the Si 3 N 4 film shown in FIG. 2 (d). First, as shown in FIG.
An SiO 2 film 14 is formed on the semiconductor substrate 10 on which the COS film 12 is formed by a normal thermal oxidation method, and then, as shown in FIG.
As shown in (b), a window is opened in the SiO 2 film 14 to form an electrode formation region 16. Next, as shown in FIG. 1C, a Si 3 N 4 film 18 is formed on the entire surface of the substrate 10 by a CVD method under normal conditions so as to have a film thickness of 50 nm.
【００１２】Ｓｉ3 Ｎ4 膜１８を基板１０上に成膜した
後、プラズマアッシング装置を使用して次の条件で酸素
プラズマ処理を１バッチ５０枚のウェハに対してバッチ
操作で施し、図２（ｄ）に示すように、Ｓｉ3 Ｎ4 膜１
８の表面を酸化して膜厚１ｎｍ以下の超薄膜のＳｉＯ2
膜２０（図２（Ｉ）参照）を形成する。
圧力：１０６ｋPa（８００mmTorr）
温度：８０°C
ガス：Ｏ2 ＝８００sccm
処理時間：１０分
ＲＦ出力：１ｋＷAfter depositing the Si 3 N 4 film 18 on the substrate 10, an oxygen plasma treatment is performed on 50 wafers in a batch by a batch operation using the plasma ashing apparatus under the following conditions. As shown in (d), Si 3 N 4 film 1
Of the ultra-thin SiO 2 film with a thickness of 1 nm or less by oxidizing the surface of No. 8
A film 20 (see FIG. 2 (I)) is formed. Pressure: 106kPa (800mmTorr) Temperature: 80 ° C Gas: O 2 = 800sccm Processing time: 10 minutes RF output: 1kW
【００１３】次いで、ホトレジストのマスクパターン２
２を使用して、通常のホトリソグラフィ法により、図２
（ｅ）に示すように、薄いＳｉＯ2 膜２０を表面に有す
るＳｉ3 Ｎ4 膜１８をエッチングする。最後に、マスク
パターン２２のホトレジストを１２０°C から１４０°
C の範囲の温度の熱硫酸過水で洗浄して除去し、図２
（ｆ）に示すようなＭＩＳ型半導体素子の絶縁膜として
最適に使用できるＳｉ3 Ｎ4 膜を得る。Next, a photoresist mask pattern 2
2 by the conventional photolithographic method using FIG.
As shown in (e), the Si 3 N 4 film 18 having the thin SiO 2 film 20 on the surface is etched. Finally, remove the photoresist of mask pattern 22 from 120 ° C to 140 ° C.
After removing by washing with hot sulfuric acid / hydrogen peroxide mixture at a temperature in the range of C,
A Si 3 N 4 film that can be optimally used as an insulating film of a MIS type semiconductor element as shown in (f) is obtained.
【００１４】プラズマアッシング装置を使用してＳｉ3
Ｎ4 膜１８に施す酸素プラズマ処理に代えて、熱酸化炉
でウェハを約９００°C に約１０分間維持することによ
り、図１（ｃ）に示すように、Ｓｉ3 Ｎ4 膜の表面を酸
化して膜厚１ｎｍ以下のＳｉＯ2 膜を形成することもで
きる。また、マスクパターン２２のホトレジストを熱硫
酸過水で洗浄して除去する前に、プラズマアッシング装
置によりアッシングして硬化したホトレジストを除去す
ることもできる。Si 3 using a plasma ashing device
Instead of the oxygen plasma treatment applied to the N 4 film 18, the surface of the Si 3 N 4 film is removed as shown in FIG. 1C by maintaining the wafer at about 900 ° C. for about 10 minutes in a thermal oxidation furnace. It is also possible to oxidize to form a SiO 2 film having a film thickness of 1 nm or less. Further, before the photoresist of the mask pattern 22 is removed by washing with hot sulfuric acid / hydrogen peroxide solution, the photoresist hardened by ashing with a plasma ashing device can be removed.
【００１５】実験例１
本発明方法を評価するために、上述の方法によりＳｉ3
Ｎ4 膜を酸化して得た薄いＳｉＯ2 膜とＳｉ3 Ｎ4 膜と
を有する本発明ウェハ試料を１１０°C から１４０°C
の間の異なる温度の熱硫酸過水でそれぞれ１０分間洗浄
し、Ｓｉ3 Ｎ4膜の膜減り量を計測した。一方、従来の
方法でＳｉ3 Ｎ4 膜のみを備えた従来法ウェハ試料を本
発明ウェハ試料と同様にして洗浄し、そのＳｉ3 Ｎ4 膜
の膜減り量を計測した。測定結果は、図３に示す通りで
あった。図３では、横軸に熱硫酸過水の温度を、縦軸に
Ｓｉ3 Ｎ4 膜の膜減り量を取った。 Experimental Example 1 In order to evaluate the method of the present invention, Si 3
A wafer sample of the present invention having a thin SiO 2 film obtained by oxidizing an N 4 film and a Si 3 N 4 film was tested at 110 ° C. to 140 ° C.
The film was washed with hot sulfuric acid / hydrogen peroxide mixture at different temperatures for 10 minutes, and the amount of Si 3 N 4 film loss was measured. On the other hand, the conventional method wafer sample having only the Si 3 N 4 film was washed by the conventional method in the same manner as the wafer sample of the present invention, and the film reduction amount of the Si 3 N 4 film was measured. The measurement result was as shown in FIG. In FIG. 3, the horizontal axis represents the temperature of hot sulfuric acid / hydrogen peroxide mixture, and the vertical axis represents the amount of reduction of the Si 3 N 4 film.
【００１６】実験例２
更に、本発明方法を評価するために、上述の方法により
Ｓｉ3 Ｎ4 膜を酸化して得た薄いＳｉＯ2 膜とＳｉ3 Ｎ
4 膜とを有する本発明ウェハ試料を１２０°Cの熱硫酸
過水で１０分間から４０分間にわたる異なる時間の間洗
浄し、Ｓｉ3 Ｎ4 膜の膜減り量を計測した。一方、従来
の方法でＳｉ3 Ｎ4 膜のみを備えた従来法ウェハ試料を
本発明ウェハ試料と同様にして洗浄し、そのＳｉ3 Ｎ4
膜の膜減り量を計測した。測定結果は、図４に示す通り
であった。図４では、横軸に洗浄時間を、縦軸にＳｉ3
Ｎ4 膜の膜減り量を取った。 Experimental Example 2 Further, in order to evaluate the method of the present invention, a thin SiO 2 film and Si 3 N 4 obtained by oxidizing the Si 3 N 4 film by the above-mentioned method.
The wafer sample of the present invention having 4 films was washed with hot sulfuric acid / hydrogen peroxide mixture at 120 ° C. for different times from 10 minutes to 40 minutes, and the amount of Si 3 N 4 film loss was measured. On the other hand, the conventional method wafer sample having only the Si 3 N 4 film was washed by the conventional method in the same manner as the wafer sample of the present invention, and the Si 3 N 4
The amount of film loss of the film was measured. The measurement result was as shown in FIG. In FIG. 4, the horizontal axis represents the cleaning time and the vertical axis represents Si 3
It took the film reduction amount of N 4 film.
【００１７】以上の結果から、本発明方法では、熱硫酸
過水の温度が高くなっても、また洗浄時間が長くなって
も、膜減り量が殆ど増加せず、また、熱硫酸過水の温度
が高い程、また洗浄時間が長い程、従来法に比べて、Ｓ
ｉ3 Ｎ4 膜の絶対的な膜減り量の減少が著しい。よっ
て、本発明方法によってＳｉ3 Ｎ4 膜を形成すれば、温
度の高い熱硫酸過水を使用して洗浄することにより、洗
浄時間を短縮することができ、更には硫酸過水の薬役ラ
イフが長くなり、薬役コストを軽減できる。また、長時
間洗浄していても、膜減り量が増大しないので、ホトレ
ジストを完全に除去することができる。From the above results, in the method of the present invention, even if the temperature of the hot sulfuric acid / hydrogen peroxide mixture becomes high and the washing time becomes long, the amount of film loss hardly increases, and the hot sulfuric acid / hydrogen peroxide mixture water is not added. The higher the temperature and the longer the cleaning time, the more S
The absolute reduction of the i 3 N 4 film is remarkably reduced. Therefore, if the Si 3 N 4 film is formed by the method of the present invention, the cleaning time can be shortened by cleaning with hot sulfuric acid / hydrogen peroxide having a high temperature, and further, the chemical life of the sulfuric acid / hydrogen peroxide can be shortened. Can be longer, and the medicinal cost can be reduced. Further, even if it is washed for a long time, the amount of film reduction does not increase, so that the photoresist can be completely removed.
【００１８】本実施例のＭＩＳ型半導体素子３０は、半
導体基板と電極との間の誘電体が、半導体基板上に形成
されたＳｉ3 Ｎ4 膜と、Ｓｉ3 Ｎ4 膜の電極側の表面を
酸素プラズマ処理又は熱酸化処理により酸化して形成し
た薄いＳｉＯ2 膜とで形成されている。本実施例の半導
体素子３０は、Ｓｉ3 Ｎ4 膜をパターニングした時に使
用したマスクパターンのホトレジストを除去する際のＳ
ｉ3 Ｎ4 膜の膜減り量が小さいので、所定膜厚のＳｉ3
Ｎ4 膜を備えることにより、所定の静電容量を有する。
よって、半導体素子３０は、キャパシタとして最適なＭ
ＩＳ型半導体素子である。In the MIS type semiconductor element 30 of this embodiment, the dielectric between the semiconductor substrate and the electrode is the Si 3 N 4 film formed on the semiconductor substrate and the surface of the Si 3 N 4 film on the electrode side. And a thin SiO 2 film formed by oxidizing oxygen plasma treatment or thermal oxidation treatment. The semiconductor element 30 of the present embodiment is S for removing the photoresist of the mask pattern used when patterning the Si 3 N 4 film.
Since the amount of i 3 N 4 film loss is small, Si 3
By having the N 4 film, it has a predetermined capacitance.
Therefore, the semiconductor element 30 has the optimum M
It is an IS type semiconductor device.
【００１９】[0019]
【発明の効果】本発明方法によれば、Ｓｉ3Ｎ4膜を半導
体基板上に形成する際に、Ｓｉ3Ｎ4膜を半導体基板上に
成膜した後、酸素プラズマ処理又は熱酸化処理を施し、
Ｓｉ3Ｎ4膜の表面を酸化して薄いＳｉＯ2膜を形成する
ことにより、Ｓｉ3Ｎ4膜のパターニングに使用したマス
クパターンのホトレジストを熱硫酸過水で洗浄、除去す
る際に発生するＳｉ3Ｎ4膜の膜減り量を従来法に比べて
大幅に減少させることができる。よって、本発明を使用
すれば、第１には、Ｓｉ3Ｎ4膜の膜厚を正確に所定膜厚
に維持することにより、所定値の静電容量を有し、バラ
ツキの無いデバイス特性を備えたＭＩＳ型半導体素子を
実現させることができる。第２には、ボイル状態の熱硫
酸過水を使用してホトレジストを除去できるので、洗浄
作業の作業能率を向上させることができる。また、ホト
リソグラフィ工程において予期しない事情により露光操
作をやり直す必要が生じた場合でも、Ｓｉ3Ｎ4膜の小さ
い膜減り量を維持しつつホトリソグラフィ工程を繰り返
し再実施することができる。According to the present invention a method according to the present invention, when forming a Si 3 N 4 film on a semiconductor substrate, after forming a the Si 3 N 4 film on a semiconductor substrate, an oxygen plasma treatment or thermal oxidation treatment Giving,
Si generated when the photoresist of the mask pattern used for patterning the Si 3 N 4 film is washed and removed with hot sulfuric acid / hydrogen peroxide by oxidizing the surface of the Si 3 N 4 film to form a thin SiO 2 film. The amount of 3 N 4 film loss can be greatly reduced compared to the conventional method. Therefore, according to the present invention, firstly, by accurately maintaining the film thickness of the Si 3 N 4 film at a predetermined film thickness, the device characteristics having a predetermined value of capacitance and no variation can be obtained. The provided MIS type semiconductor device can be realized. Second, it is possible to remove the photoresist using heat SPM Boyle states, it is possible to improve the working efficiency of the cleaning operation. Further, even when it is necessary to redo the exposure operation due to an unexpected situation in the photolithography process, the photolithography process can be re-executed repeatedly while maintaining a small film reduction amount of the Si 3 N 4 film.
【図１】図１（ａ）から（ｃ）は、それぞれ、ＭＩＳキ
ャパシタの絶縁膜としてＳｉ3Ｎ4 膜を成膜するため
に、本発明方法を実施する際の各工程毎の基板層構造を
示す断面図である。1 (a) to 1 (c) are respectively substrate layer structures of respective steps when carrying out the method of the present invention for forming a Si 3 N 4 film as an insulating film of a MIS capacitor. FIG.
【図２】図２（ｄ）から（ｆ）は、図１（ｃ）に続い
て、それぞれ、ＭＩＳキャパシタの絶縁膜としてＳｉ3
Ｎ4 膜を成膜するために、本発明方法を実施する際の各
工程毎の基板層構造を示す断面図であり、図２（Ｉ）は
図２（ｄ）に示すＳｉ3 Ｎ4 膜の拡大断面図である。2 (d) to 2 (f) are the same as FIG. 1 (c), but Si 3 is used as an insulating film of the MIS capacitor.
FIG. 2 (I) is a cross-sectional view showing a substrate layer structure in each step when carrying out the method of the present invention to form an N 4 film, and FIG. 2 (I) is a Si 3 N 4 film shown in FIG. 2 (d). FIG.
【図３】実験例１で得た、硫酸過水の温度とＳｉ3 Ｎ4
膜の膜減り量との関係を示すグラフである。FIG. 3 shows the temperature of sulfuric acid / hydrogen peroxide solution and Si 3 N 4 obtained in Experimental Example 1.
It is a graph which shows the relationship with the film thickness reduction amount of a film.
【図４】実験例２で得た、硫酸過水洗浄時間とＳｉ3 Ｎ
4 膜の膜減り量との関係を示すグラフである。FIG. 4 is a sulfuric acid / hydrogen peroxide cleaning time and Si 3 N obtained in Experimental Example 2.
It is a graph which shows the relationship with the amount of film loss of four films.
【図５】図５（ａ）から（ｃ）は、それぞれ、ＭＩＳキ
ャパシタの絶縁膜としてＳｉ3Ｎ4 膜を成膜するため
に、従来法を実施する際の各工程毎の基板層構造を示す
断面図である。5 (a) to 5 (c) respectively show a substrate layer structure in each step when performing a conventional method for forming a Si 3 N 4 film as an insulating film of a MIS capacitor. It is sectional drawing shown.
１０ 半導体基板 １２ ＬＯＣＯＳ膜 １４ ＳｉＯ2 膜 １６ 電極形成領域 １８ Ｓｉ3 Ｎ4 膜 ２０ ＳｉＯ2 膜 ２２ マスクパターン10 semiconductor substrate 12 LOCOS film 14 SiO 2 film 16 electrode forming region 18 Si 3 N 4 film 20 SiO 2 film 22 mask pattern
Claims (4)
法であって、 Ｓｉ3Ｎ4膜を半導体基板上に成膜する工程と、 酸素プラズマ処理又は熱酸化処理をウェハに施してＳｉ
3Ｎ4膜の表面を酸化し、Ｓｉ3Ｎ4膜の表面に極く薄いＳ
ｉＯ2膜を形成する工程と、 ホトレジスト膜のマスクパターンを形成する工程と、 マスクパターンをマスクにして薄いＳｉＯ2膜及びＳｉ3
Ｎ4膜をエッチングする工程と、 熱硫酸過水でマスクパターンのホトレジストを除去する
工程とを備えることを特徴とするＳｉ3Ｎ4膜の形成方
法。1. A method of forming a Si 3 N 4 film on a semiconductor substrate, the method comprising: forming a Si 3 N 4 film on a semiconductor substrate; and performing oxygen plasma treatment or thermal oxidation treatment on the wafer. Si
The surface of the 3 N 4 film is oxidized to form an extremely thin S on the surface of the Si 3 N 4 film.
a step of forming an iO 2 film, a step of forming a mask pattern of a photoresist film, and a thin SiO 2 film and Si 3 film using the mask pattern as a mask.
A method of forming a Si 3 N 4 film, comprising: a step of etching the N 4 film; and a step of removing the photoresist of the mask pattern with hot sulfuric acid / hydrogen peroxide mixture.
ストを除去する工程において、１２０℃から１４０℃の
温度範囲の熱硫酸過水を使用することを特徴とする請求
項１に記載のＳｉ3Ｎ4膜の形成方法。2. A process of removing the photoresist mask pattern in thermal SPM, according to claim 1, characterized by using a 140 ° C. temperature range of the thermal SPM from 120 ° C. Si 3 N 4 Method of forming film.
て、プラズマアッシング法によりマスクパターンのホト
レジストを除去し、更に熱硫酸過水で洗浄、除去するこ
とを特徴とする請求項１に記載のＳｉ3Ｎ4膜の形成方
法。 3. The Si 3 N 4 according to claim 1, wherein in the step of removing the mask pattern, the photoresist of the mask pattern is removed by a plasma ashing method, and further washed and removed with hot sulfuric acid / hydrogen peroxide solution. Method of forming a film.
るＭＩＳ型半導体素子の絶縁膜として使用されるＳｉ3
Ｎ4膜を形成することを特徴とする請求項１又は２に記
載のＳｉ3Ｎ4膜の形成方法。4. Si 3 used as an insulating film of a MIS type semiconductor element composed of a semiconductor substrate, an insulating film and an electrode.
The Si 3 N 4 film formation method according to claim 1 or 2, characterized in that to form the N 4 film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17445395A JP3362566B2 (en) | 1995-06-16 | 1995-06-16 | Method of forming Si3N4 film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17445395A JP3362566B2 (en) | 1995-06-16 | 1995-06-16 | Method of forming Si3N4 film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH098034A JPH098034A (en) | 1997-01-10 |
| JP3362566B2 true JP3362566B2 (en) | 2003-01-07 |
Family
ID=15978764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17445395A Expired - Fee Related JP3362566B2 (en) | 1995-06-16 | 1995-06-16 | Method of forming Si3N4 film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3362566B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02125757A (en) * | 1988-07-11 | 1990-05-14 | Ngk Spark Plug Co Ltd | Substrate for inclined type thermal head and preparation thereof |
| JP4704629B2 (en) * | 2001-09-07 | 2011-06-15 | 株式会社リコー | Thin film transistor and manufacturing method thereof |
| JP2004153037A (en) | 2002-10-31 | 2004-05-27 | Renesas Technology Corp | Method for manufacturing semiconductor device |
| TWI409934B (en) | 2005-10-12 | 2013-09-21 | Semiconductor Energy Lab | Semiconductor device |
| JP5454108B2 (en) | 2009-11-30 | 2014-03-26 | 東京エレクトロン株式会社 | Substrate processing apparatus, substrate processing method, and storage medium |
-
1995
- 1995-06-16 JP JP17445395A patent/JP3362566B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH098034A (en) | 1997-01-10 |
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