JP3354221B2 - Method of forming bump electrode - Google Patents
Method of forming bump electrodeInfo
- Publication number
- JP3354221B2 JP3354221B2 JP19685093A JP19685093A JP3354221B2 JP 3354221 B2 JP3354221 B2 JP 3354221B2 JP 19685093 A JP19685093 A JP 19685093A JP 19685093 A JP19685093 A JP 19685093A JP 3354221 B2 JP3354221 B2 JP 3354221B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- electrode
- bump
- bump electrode
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、セラミック多層配線基
板上に形成するバンプ電極の形成方法に関するものであ
る。The present invention relates to a Monodea method for forming a bump electrode to be formed on the ceramic multi-layer wiring board
You .
【０００２】[0002]
【従来の技術】従来、セラミック多層配線基板上に形成
するバンプ電極としては、クリームはんだ、及びはんだ
ボールを用いて形成する方法が一般的であった。2. Description of the Related Art Heretofore, bump electrodes formed on a ceramic multilayer wiring board have generally been formed by using cream solder and solder balls.
【０００３】かかるバンプ電極の形成方法は、先ずセラ
ミック多層配線基板上のバンプ電極形成部に導体パター
ンを形成し、該導体パターン上にクリームはんだを印
刷、或いは塗布し、その面上にはんだボールを搭載して
大気中で加熱溶融する方法であった。In such a method of forming a bump electrode, first, a conductor pattern is formed on a bump electrode formation portion on a ceramic multilayer wiring board, cream solder is printed or applied on the conductor pattern, and a solder ball is formed on the surface. It was a method of mounting and heating and melting in the atmosphere.
【０００４】ここで、上記方法により形成されたバンプ
電極は、その大部分がはんだで構成されているため、該
バンプ電極の大きさは、上記クリームはんだの印刷或い
は塗布量、及びはんだボールの大きさによってほぼ決定
され、またバンプ電極の形状は、溶融した際のはんだの
表面張力の影響で、概ね図５に示したような球型の一部
形状を呈したものとなっていた。[0004] Here, most of the bump electrodes formed by the above-mentioned method are made of solder. Therefore, the size of the bump electrodes depends on the amount of printing or application of the cream solder and the size of the solder balls. The shape of the bump electrode was substantially determined by the influence of the surface tension of the solder when it was melted, and the shape of the bump electrode was almost spherical, as shown in FIG.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上述し
た従来の方法で形成されたバンプ電極１０１を有するセ
ラミック多層配線基板１０２を、マザーボード１０３に
実装する際においては、バンプ電極１０１は上記したよ
うにその大部分がはんだで構成されているため、マザー
ボード１０３への実装のための再加熱時にその全体が溶
融し、形状を維持することができないため、接合する両
基板間隔を一定に保つことが非常に困難となり、図６に
示したように、両基板が斜めに接合されることによる隣
接したバンプ電極間のショート、或いは両基板電極間の
接続不良等の問題が発生し易い構造のものであった。However, when the ceramic multilayer wiring board 102 having the bump electrodes 101 formed by the above-mentioned conventional method is mounted on the motherboard 103, the bump electrodes 101 are not Since most parts are made of solder, the entire part is melted during reheating for mounting on the motherboard 103, and the shape cannot be maintained. becomes difficult, as shown in FIG. 6, it is of a structure easy a potential issue for improper connections between short-circuit between adjacent bump electrodes, or both substrates electrodes due to both substrates are bonded obliquely Was.
【０００６】また、上述した従来方法により形成された
バンプ電極は、その大きさ及び形状が、上記したように
クリームはんだの印刷或いは塗布量、及びはんだボール
の大きさによって左右されると共に、はんだの溶融時の
ダレ等によって大きく変化するものであるため、高さ及
び幅の均一なバンプ電極を得ることが困難であり、図７
に示したように、該バンプ電極１０１を有するセラミッ
ク多層配線基板１０２と、マザーボード１０３とが一定
の間隔を保って接合できた場合においても、その高さ及
び幅の不均一性故に隣接したバンプ電極間のショート、
或いは両基板電極間の接続不良等の問題が依然として発
生し易いものであった。In addition, the size and shape of the bump electrode formed by the above-described conventional method depend on the printing or application amount of the cream solder and the size of the solder ball as described above. Since it greatly changes due to sagging during melting, it is difficult to obtain a bump electrode having a uniform height and width.
As shown in the figure, even when the ceramic multilayer wiring board 102 having the bump electrodes 101 and the mother board 103 can be joined at a constant interval, the bump electrodes adjacent to each other due to the non-uniformity of the height and the width. Short between,
Or connection problems such as poor between the substrates electrodes Yi were those liable to occur as a natural.
【０００７】さらに、上記した問題は、今後さらにセラ
ミック多層配線基板を用いたモジュールの高集積化、及
び高密度化が図られる中で、これらのセラミック多層配
線基板をマザーボードへ実装する際、より顕著に現れ、
製品の歩留りを悪化させることが危惧されていた。Further, the above-mentioned problems are more remarkable when these ceramic multilayer wiring boards are mounted on a motherboard, as modules using ceramic multilayer wiring boards are to be further integrated and densified in the future. Appears in
It was feared that it would lower product yield.
【０００８】本発明は、上述した従来技術が有する課題
に鑑みなされたものであって、その目的は、バンプ電極
を有したセラミック多層配線基板をマザーボードに実装
する際、両基板間隔を一定に保つことが可能で、且つ高
密度なバンプ電極による接続が可能な、セラミック多層
配線基板上に形成する新規なバンプ電極の形成方法を提
供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to maintain a constant distance between both substrates when a ceramic multilayer wiring board having bump electrodes is mounted on a motherboard. it is possible, which can be connected by and high density bump electrodes, is to provide a method of forming a novel bump electrodes formed on the ceramic multi-layer wiring board.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記目的を達
成するため、セラミック多層配線基板に形成されたバイ
ア導体直上に、はんだより融点の高い金属から成る導体
ペーストをスクリーン印刷し、焼成して所望のコア電極
を形成した後、該コア電極の表面に、はんだメッキ層を
形成するバンプ電極の形成方法とした。According to the present invention, in order to attain the above object, a conductor made of a metal having a melting point higher than that of solder is placed directly on a via conductor formed in a ceramic multilayer wiring board.
After the paste is screen-printed and fired to form a desired core electrode, a solder plating layer is formed on the surface of the core electrode.
The method for forming the bump electrode to be formed was adopted.
【００１０】上記した本発明にかかるバンプ電極の形成
方法によれば、はんだより融点の高いコア電極と、該コ
ア電極の表面を被覆するはんだ層とから成るバンプ電極
を形成でき、該バンプ電極を有するセラミック多層配線
基板をマザーボードに実装する際、その実装のための加
熱温度（はんだ溶融温度）では溶融しないコア電極がス
ペーサの役割を果たし、両基板を一定間隔に保った状態
で接合することが可能となると共に、両基板の接合に寄
与するはんだは、上記コア電極の表面に層として設けら
れた少量のものであるため、かなり近接してバンプ電極
を形成しても、ショート等の問題が起きにくい構造とな
り、高密度なバンプ電極による接続が可能となる。 Formation of the bump electrode according to the present invention described above
According to the method, a core electrode having a melting point higher than that of solder
A bump electrode comprising a solder layer covering the surface of the electrode
Ceramic wiring having the bump electrode
When mounting the board on the motherboard,
A core electrode that does not melt at heat temperature (solder melting temperature)
Plays the role of a pacer and keeps both substrates at a constant distance
To join the two substrates.
The solder to be applied is provided as a layer on the surface of the core electrode.
The bump electrode is very close
Even if it is formed, a structure such as a short circuit is unlikely to occur.
Therefore, connection by high-density bump electrodes becomes possible.
【００１１】また、本発明にかかるバンプ電極の形成方
法は、上記したスペーサの役割を果 たすコア電極を、い
わゆる型を使用したスクリーン印刷により形成すること
としたため、その形成されるコア電極の高さ及び幅は均
一なものとすることが容易となり、スペーサとしての信
頼性が高いコア電極を有するバンプ電極の形成が可能と
なる。 Also, a method of forming a bump electrode according to the present invention
Law, the core electrodes fulfilling the role of a spacer as described above, have
Forming by screen printing using a so-called mold
Therefore, the height and width of the formed core electrode are uniform.
It is easy to achieve a uniform
Can form bump electrodes with highly reliable core electrodes
Become.
【００１２】ここで、上記バイア導体直上にスクリーン
印刷により形成するコア電極の寸法形状としては、高さ
５０〜５００μｍ、底面径１００〜１０００μｍ、底面
径に対する高さのアスペクト比０．２５〜１．０の断面
台形形状のコア電極とすることが望ましい。これは、こ
のような寸法形状のコア電極とすることにより、該コア
電極がマザーボードへの実装時にスペーサとしての役割
を有効に果たし得る強度を有するものとなると共に、高
密度な接続に対応可能なコア電極となるためである。 Here, a screen is provided directly above the via conductor.
The dimensions and shape of the core electrode formed by printing
50-500 μm, bottom diameter 100-1000 μm, bottom
Cross section of height to diameter aspect ratio of 0.25 to 1.0
It is desirable to use a trapezoidal core electrode. This is
By forming a core electrode having such dimensions as
Electrodes function as spacers when mounted on motherboard
Has a strength that can effectively fulfill
This is because the core electrode becomes a core electrode that can support high-density connection.
【００１３】また、上記コア電極を形成するためのスク
リーン印刷は、所定形状、例えばコア電極の所望とする
高さの１．０〜１．３倍の高さを有し、コア電極の所望
とする底面径の０．８〜１．２倍の径を有する貫通孔が
形成されたメタルマスクを用いて行われることが望まし
い。これは、メタルマスクは、スクリーン型として強度
及び形状安定性に優れているために、所望のコア電極を
安定的に形成できるために望ましい。このようなメタル
マスクは、例えばアディティブ法により作製できる。 Further, a screen for forming the core electrode is provided.
Lean printing is a desired shape, for example a core electrode
Having a height of 1.0 to 1.3 times the height, and
Through hole having a diameter of 0.8 to 1.2 times the bottom diameter
It is desirable that the process be performed using the formed metal mask.
No. This is because the metal mask is as strong as the screen type
Because of its excellent shape stability,
It is desirable because it can be formed stably. Such metal
The mask can be manufactured by, for example, an additive method.
【００１４】また、上記メタルマスクの加工面に、自己
潤滑性を有するフッ素系化合物の被膜が形成されている
ことが望ましい。これは、メタルマスクの加工面に施し
た上記自己潤滑性を有するフッ素化合物の被膜の存在に
より、導体ペーストの印刷時のメタルマスク裏面へのダ
レ込み防止、及び印刷した導体ペーストのメタルマスク
からの抜け性について、良好な結果が得られるために望
ましい。 In addition, a self-processed surface of the metal mask
Fluorine compound film with lubricity is formed
It is desirable. This is applied to the processing surface of the metal mask
Of the self-lubricating fluorine compound coating
From the back of the metal mask when printing conductive paste.
Prevents sinking and prints conductive paste metal mask
For good results.
Good.
【００１５】なお、印刷後及び乾燥時の導体ペーストの
ダレは、該ペーストのチクソトロピー性を高めること
と、ペースト化する際に樹脂系バインダーを使用しない
ことで ダレ抑制効果が得られる。 The conductor paste after printing and during drying
Sagging to increase the thixotropic properties of the paste
And do not use resin binder when pasting
Thereby , the sag suppressing effect can be obtained.
【００１６】上記のようにして形成されたコア電極の表
面に、フラックスを塗布し、例えばはんだ溶融槽中に浸
漬することではんだメッキ層をコア電極表面に形成す
る。このような溶融浸漬法によるはんだメッキ層の形成
は、マザーボードへの実装時にダレ等の発生が少ない均
一な薄膜のはんだ層を、簡易にコア電極表面上に形成す
ることが可能となる。 Table of core electrodes formed as described above
Apply flux to the surface and immerse it in, for example, a solder melting bath.
To form a solder plating layer on the core electrode surface
You. Formation of solder plating layer by such melting and dipping method
Is less likely to cause sagging when mounted on the motherboard
A simple thin solder layer is easily formed on the core electrode surface.
It becomes possible.
【００１７】そして、更に必要に応じて、上記はんだ層
の表面に、例えば無電解金メッキ液に浸漬する方法にて
金メッキ層を形成する。はんだ層の表面に形成された金
メッキ層は、はんだの表面酸化を防ぐことができ、長期
間保存しても基板実装時のはんだの濡れ性を良好に保つ
ことが可能となり、さらに接合の信頼性の高いバンプ電
極を提供できる。 なお、ここでは、一般に市販されてい
るフラックス、はんだ並びに無電解金メッキ液を使用す
ることができる。 Further , if necessary, a gold plating layer is formed on the surface of the solder layer by, for example , a method of dipping in an electroless gold plating solution. Gold formed on the surface of the solder layer
The plating layer can prevent oxidation of the solder surface,
Keeps solder wettability during board mounting
And a bump electrode with high bonding reliability.
Can provide poles. Here, generally the flux which is commercially available, can be used a solder and an electroless gold plating solution.
【００１８】[0018]
【実施例】以下、上記した本発明にかかるバンプ電極の
形成方法の実施例を、図面を参照しながら説明する。EXAMPLES Hereinafter, the examples of <br/> forming method of the bump electrodes according to the present invention described above will be described with reference to the drawings.
【００１９】ここで、図１は本発明の実施例におけるセ
ラミック多層配線基板上への高密度なバンプ電極形成後
の断面図であり、かかるバンプ電極は、そのバンプ径が
３００μｍ、バンプ高さが２５０μｍ、バンプピッチが
５００μｍに形成されたバンプ電極である。FIG. 1 is a cross-sectional view after forming a high-density bump electrode on a ceramic multilayer wiring board according to an embodiment of the present invention. The bump electrode has a bump diameter of 300 μm and a bump height of 300 μm. The bump electrode is formed to have a pitch of 250 μm and a bump pitch of 500 μm.
【００２０】図１において、１はセラミック多層配線基
板、２はバイア導体（Ａｇ）、３はコア電極（２０％Ｐ
ｄ−Ａｇ）、４ははんだ層（６２Ｓｎ／３６Ｐｂ／２Ａ
ｇ）、５は金メッキ層である。In FIG. 1, 1 is a ceramic multilayer wiring board, 2 is a via conductor (Ag), 3 is a core electrode (20% P
d-Ag), 4 is a solder layer (62Sn / 36Pb / 2A)
g) Reference numeral 5 denotes a gold plating layer.
【００２１】上記バンプ電極の形成方法を、以下に説明
する。The method for forming the bump electrode will be described below.
【００２２】先ず、コア電極形成用ペースト（２０％Ｐ
ｄ含有Ａｇペースト、ＢＰＭ−１０５：日本セメント株
式会社製）を、図３に示したメタル厚３００μｍ、貫通
孔６の底面径が２８０μｍのアディティブ法で作製した
メタルマスク７を用いて、セラミック多層配線基板に形
成されたバイア導体直上に、硬度７０の角スキージを用
いてスクリーン印刷し、７０°Ｃで１０分間乾燥後、ベ
ルト焼成炉にて大気中、ピーク温度８５０°Ｃで１０分
間保持し、且つ全工程が６０分のプロファイルで焼成を
行った。なお、上記メタルマスク７の加工面には、フッ
素系化合物の被膜８が形成されている。First, a paste for forming a core electrode (20% P
d-containing Ag paste, BPM-105: manufactured by Nippon Cement Co., Ltd.) using a metal mask 7 produced by an additive method with a metal thickness of 300 μm and a bottom diameter of the through hole 6 of 280 μm shown in FIG. Immediately above the via conductor formed on the substrate, screen printing was performed using a square squeegee having a hardness of 70, dried at 70 ° C. for 10 minutes, and held in a belt firing furnace in the air at a peak temperature of 850 ° C. for 10 minutes. In addition, all the processes were fired with a profile of 60 minutes. In addition, on the processed surface of the metal mask 7, a coating 8 of a fluorine-based compound is formed.
【００２３】次に、焼成後の上記コア電極表面に、フラ
ックス（Ｒ５００３：日本アルファメタルズ株式会社
製）を塗布し、１５０°Ｃで３０秒間予備加熱した後、
２３０°Ｃに溶融されたはんだ（６２Ｓｎ／３６Ｐｂ／
２Ａｇはんだ、Ｓ−２０６２：千住金属株式会社製）浴
槽中に該コア電極を５秒間浸漬し、コア電極表面にはん
だ層を形成した。上記塗布したフラックス洗浄は、エタ
ノール＋酢酸ブチルの混合液中で浸漬攪拌３０秒を行う
ことにより実施した。Next, a flux (R5003: manufactured by Nippon Alpha Metals Co., Ltd.) is applied to the surface of the core electrode after firing, and preheated at 150 ° C. for 30 seconds.
Solder melted at 230 ° C (62Sn / 36Pb /
2Ag solder, S-2062: manufactured by Senju Metal Co., Ltd.) The core electrode was immersed in a bath for 5 seconds to form a solder layer on the surface of the core electrode. The applied flux washing was performed by immersing and stirring for 30 seconds in a mixed solution of ethanol and butyl acetate.
【００２４】その後、得られたコア電極のはんだ層表面
に、無電解金メッキ（Ｋ２４Ｎ：高純度化学株式会社
製）を用いて、メッキ液温９０°Ｃ±５°Ｃで１分間浸
漬することにより、膜厚約１００オングストロームの金
メッキ層を形成した。Thereafter, the surface of the obtained solder layer of the core electrode is immersed for 1 minute at a plating solution temperature of 90 ° C. ± 5 ° C. using electroless gold plating (K24N: manufactured by Kojundo Chemical Co., Ltd.). A gold plating layer having a thickness of about 100 Å was formed.
【００２５】以上、記載した本発明にかかるバンプ電極
の形成方法により得られたバンプ電極の寸法データを、
図４に示す。The dimensional data of the bump electrode obtained by the method for forming a bump electrode according to the present invention described above is
As shown in FIG.
【００２６】図４から明らかなように、本発明にかかる
バンプ電極の形成方法によれば、該バンプ電極の径、及
び高さが±５％以内のバラツキ範囲内で形成できること
が判明する。As apparent from FIG. 4, according to the method for forming a bump electrode according to the present invention, the diameter and height of the bump electrode can be formed within a variation range of ± 5% or less.
【００２７】次に、上記した本発明で得られたバンプ電
極と、従来法で得られたバンプ電極との性能を比較する
ため、バンプ径３００μｍ、バンプ高さ２５０μｍ、バ
ンプピッチ５００μｍのバンプ９００個を形成したセラ
ミック多層配線基板を、従来法と上記した本発明におけ
る方法で各々３０基板作製し、それらの基板をＡｕ電極
が形成されたアルミナ多層配線基板（マザーボード）上
に位置合わせして搭載後、バンプ部のはんだを溶融する
ことで両基板を実装した。Next, in order to compare the performance of the above-described bump electrode obtained by the present invention with the performance of the bump electrode obtained by the conventional method, 900 bumps having a bump diameter of 300 μm, a bump height of 250 μm, and a bump pitch of 500 μm were used. The ceramic multi-layered wiring board on which 30 was formed was manufactured by the conventional method and the method of the present invention described above, and each of the substrates was aligned and mounted on an alumina multi-layered wiring board (mother board) on which Au electrodes were formed. Then, both substrates were mounted by melting the solder of the bump portions.
【００２８】得られた実装基板において、従来法、及び
本発明における方法で作製した基板のバンプ部接続歩留
りを求めたところ、従来法で形成したバンプ電極形成基
板の実装歩留りは６７％であり、本発明における方法で
形成したバンプ電極形成基板の実装歩留りは９３％であ
った。When the bump connection yield of the substrate manufactured by the conventional method and the method of the present invention was determined for the obtained mounting substrate, the mounting yield of the bump electrode forming substrate formed by the conventional method was 67%. The mounting yield of the bump electrode forming substrate formed by the method of the present invention was 93%.
【００２９】[0029]
【発明の効果】以上、説明した本発明にかかるバンプ電
極の形成方法によれば、バンプ電極を有したセラミック
多層配線基板のマザーボードへの実装歩留まりの向上
と、高密度なバンプ電極接続に対応可能なセラミック多
層配線基板上のバンプ電極の形成が可能となる。Effect of the Invention] According to the method of forming a bump electrode according to the present invention described, the improvement of the mounting yield of the ceramic multi-layer wiring board motherboard having a bump electrode, adaptable to high-density bump electrode connection It is possible to form a bump electrode on a simple ceramic multilayer wiring board.
【図１】本発明の実施例におけるバンプ電極を形成した
セラミック多層配線基板の断面図である。FIG. 1 is a cross-sectional view of a ceramic multilayer wiring board on which bump electrodes are formed according to an embodiment of the present invention.
【図２】本発明の実施例におけるバンプ電極を形成した
セラミック多層配線基板のマザーボードへの実装後の断
面図である。FIG. 2 is a cross-sectional view after mounting a ceramic multilayer wiring board on which bump electrodes are formed according to an embodiment of the present invention on a motherboard.
【図３】本発明においてバンプ電極の形成に用いるメタ
ルマスクの断面図である。FIG. 3 is a cross-sectional view of a metal mask used for forming a bump electrode in the present invention.
【図４】本発明の実施例によって得られたバンプ電極の
寸法データを示したグラフである。FIG. 4 is a graph showing dimension data of a bump electrode obtained according to an example of the present invention.
【図５】従来法におけるバンプ電極を形成したセラミッ
ク多層配線基板の断面図である。FIG. 5 is a cross-sectional view of a conventional ceramic multilayer wiring board on which bump electrodes are formed.
【図６】従来法におけるバンプ電極を形成したセラミッ
ク多層配線基板のマザーボードへの実装後の断面図であ
る。FIG. 6 is a cross-sectional view after mounting a ceramic multilayer wiring board on which bump electrodes are formed in a conventional method on a motherboard.
【図７】従来法におけるバンプ電極を形成したセラミッ
ク多層配線基板のマザーボードへの実装後の断面図であ
る。FIG. 7 is a cross-sectional view after mounting a ceramic multilayer wiring board on which bump electrodes are formed on a motherboard according to a conventional method.
１ セラミック多層配線基板 ２ バイア導体 ３ コア電極 ４ はんだ層 ５ 金メッキ層 ６ 貫通孔 ７ メタルマスク ８ フッ素系化合物の被膜 ９ マザーボード DESCRIPTION OF SYMBOLS 1 Ceramic multilayer wiring board 2 Via conductor 3 Core electrode 4 Solder layer 5 Gold plating layer 6 Through hole 7 Metal mask 8 Fluorine compound coating 9 Motherboard
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平４−32253（ＪＰ，Ａ) 特開 昭61−279138（ＪＰ，Ａ) 特開 昭60−68637（ＪＰ，Ａ) 特開 平５−74778（ＪＰ，Ａ) 特開 平４−22131（ＪＰ，Ａ) 特開 平６−125162（ＪＰ，Ａ) 特公 昭51−4633（ＪＰ，Ｂ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 3/32 - 3/34 H05K 3/46 H01L 21/60 H01L 21/92 H01L 23/12 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-32253 (JP, A) JP-A-61-279138 (JP, A) JP-A-60-68637 (JP, A) JP-A 5- 74778 (JP, A) JP-A-4-22131 (JP, A) JP-A-6-125162 (JP, A) JP-B-51-4633 (JP, B1) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 3/32-3/34 H05K 3/46 H01L 21/60 H01L 21/92 H01L 23/12
Claims (5)
イア導体直上に、はんだより融点の高い金属から成る導
体ペーストをスクリーン印刷し、焼成して所望のコア電
極を形成した後、該コア電極の表面に、はんだメッキ層
を形成することを特徴とするバンプ電極の形成方法。1. A conductor made of a metal having a melting point higher than that of a solder directly above a via conductor formed on a ceramic multilayer wiring board.
After the body paste is screen printed and fired to form a desired core electrode, on the surface of the core electrodes, the method of forming the bump electrode, and forming a solder plating layer.
電極が、高さ５０〜５００μｍ、底面径１００〜１００
０μｍ、底面径に対する高さのアスペスト比０．２５〜
１．０の断面台形形状のコア電極であることを特徴とす
る、請求項１記載のバンプ電極の形成方法。2. A core formed by screen printing.
The electrode has a height of 50 to 500 μm and a bottom diameter of 100 to 100
0 μm, Aspect ratio of height to bottom diameter 0.25
2. The method for forming a bump electrode according to claim 1, wherein the core electrode has a trapezoidal cross section of 1.0 .
ン印刷が、所定形状の貫通孔が形成されたメタルマスク
を用いて行われることを特徴とする、請求項１又は２記
載のバンプ電極の形成方法。3. A screen for forming said core electrode.
Metal mask with through-holes of predetermined shape
3. The method according to claim 1 , wherein the step is performed by using
Method of forming the above-mentioned bump electrode.
性を有するフッ素系化合物の被膜が形成されていること
を特徴とする、請求項３記載のバンプ電極の形成方法。4. The method for forming a bump electrode according to claim 3, wherein a coating of a fluorine-based compound having self-lubricating properties is formed on a processed surface of said metal mask.
層を形成することを特徴とする、請求項１、２、３又は
４記載のバンプ電極の形成方法。The surface according to claim 5 wherein the solder layer, characterized in that it further forming a gold plating layer, according to claim 1, 3 or
5. The method for forming a bump electrode according to 4 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19685093A JP3354221B2 (en) | 1993-07-14 | 1993-07-14 | Method of forming bump electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19685093A JP3354221B2 (en) | 1993-07-14 | 1993-07-14 | Method of forming bump electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0730244A JPH0730244A (en) | 1995-01-31 |
| JP3354221B2 true JP3354221B2 (en) | 2002-12-09 |
Family
ID=16364702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19685093A Expired - Fee Related JP3354221B2 (en) | 1993-07-14 | 1993-07-14 | Method of forming bump electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3354221B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3859963B2 (en) * | 2000-11-29 | 2006-12-20 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
| JP2005064251A (en) * | 2003-08-12 | 2005-03-10 | Nippon Mektron Ltd | Printing tool for printed circuit board |
| JP2006269972A (en) * | 2005-03-25 | 2006-10-05 | Mitsumi Electric Co Ltd | Semiconductor device |
| JP4624172B2 (en) * | 2005-04-28 | 2011-02-02 | 三菱電機株式会社 | High frequency circuit module |
| JP2009054741A (en) * | 2007-08-27 | 2009-03-12 | Powertech Technology Inc | Semiconductor package |
| JP6156136B2 (en) * | 2013-12-27 | 2017-07-05 | 三菱マテリアル株式会社 | Core paste for forming sintered cores of solder bumps |
| JP6379342B2 (en) * | 2014-07-09 | 2018-08-29 | 三菱マテリアル株式会社 | Semiconductor device and manufacturing method thereof |
-
1993
- 1993-07-14 JP JP19685093A patent/JP3354221B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0730244A (en) | 1995-01-31 |
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