JP3346693B2 - Glass-ceramic sintered body and wiring board using the same - Google Patents

Glass-ceramic sintered body and wiring board using the same

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Publication number
JP3346693B2
JP3346693B2 JP30562295A JP30562295A JP3346693B2 JP 3346693 B2 JP3346693 B2 JP 3346693B2 JP 30562295 A JP30562295 A JP 30562295A JP 30562295 A JP30562295 A JP 30562295A JP 3346693 B2 JP3346693 B2 JP 3346693B2
Authority
JP
Japan
Prior art keywords
glass
package
circuit board
sintered body
thermal expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30562295A
Other languages
Japanese (ja)
Other versions
JPH09142880A (en
Inventor
武志 窪田
浩一 山口
紀彰 浜田
秀人 米倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP30562295A priority Critical patent/JP3346693B2/en
Priority to US08/623,979 priority patent/US5763059A/en
Publication of JPH09142880A publication Critical patent/JPH09142880A/en
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Publication of JP3346693B2 publication Critical patent/JP3346693B2/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、高熱膨張の回路基
板に実装される半導体素子等を搭載した配線基板等に好
適なガラス−セラミック焼結体およびそれを用いた配線
基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a glass-ceramic sintered body suitable for a wiring board or the like on which a semiconductor element or the like mounted on a circuit board having a high thermal expansion is mounted, and a wiring board using the same.

【０００２】[0002]

【従来技術】従来、配線基板は、絶縁基板の表面あるい
は内部にメタライズ配線層が配設された構造からなる。
また、この配線基板を用いた代表的な例として、半導体
素子、特にＬＳＩ（大規模集積回路素子）等の半導体集
積回路素子を収容するための半導体素子収納用パッケー
ジが挙げられる。2. Description of the Related Art Conventionally, a wiring board has a structure in which a metallized wiring layer is disposed on the surface or inside of an insulating substrate.
A typical example using the wiring substrate is a semiconductor element housing package for housing a semiconductor element, particularly a semiconductor integrated circuit element such as an LSI (large-scale integrated circuit element).

【０００３】また、かかる半導体素子収納用パッケージ
は、外部電気回路基板の配線導体と接続するには、パッ
ケージの絶縁基板に接続された接続端子と外部電気回路
基板の配線導体とを半田等により電気的に接続すること
ができる。Further, in such a package for housing a semiconductor element, in order to connect with a wiring conductor of an external electric circuit board, a connection terminal connected to an insulating substrate of the package and a wiring conductor of the external electric circuit board are electrically connected by soldering or the like. Can be connected.

【０００４】一般に、半導体素子の集積度が高まるほ
ど、半導体素子に形成される電極数も増大するが、これ
に伴いこれを収納する半導体収納用パッケージにおける
接続端子数も増大することになる。ところが、電極数が
増大するに伴いパッケージ自体の寸法を大きくするにも
限界があるため、パッケージにおける接続端子の密度を
高くすることが必要となる。In general, as the degree of integration of a semiconductor device increases, the number of electrodes formed on the semiconductor device also increases. As a result, the number of connection terminals in a semiconductor housing package for housing the semiconductor device also increases. However, as the number of electrodes increases, there is a limit in increasing the dimensions of the package itself. Therefore, it is necessary to increase the density of connection terminals in the package.

【０００５】これまでのパッケージにおける端子の密度
を高めるための構造としては、パッケージの下面にコバ
ールなどの金属ピンを接続したピングリッドアレイ（Ｐ
ＧＡ）が最も一般的であるが、最近では、パッケージの
４つの側面に導出されたメタライズ配線層にガルウィン
グ状（Ｌ字状）の金属ピンが接続されたタイプのクワッ
ドフラットパッケージ（ＱＦＰ）、パッケージの４つの
側面に電極パッドを備え、リードピンがないリードレス
チップキャリア（ＬＣＣ）、さらに絶縁基板の下面に半
田からなる球状端子を多数配置したボールグリッドアレ
イ（ＢＧＡ）等があり、これらの中でもＢＧＡが最も高
密度化が可能であると言われている。[0005] As a structure for increasing the terminal density in a conventional package, a pin grid array (P) in which metal pins such as Kovar are connected to the lower surface of the package is known.
GA) is the most common, but recently, a quad flat package (QFP) and a package in which gull-wing (L-shaped) metal pins are connected to metallized wiring layers led to four sides of the package. There is a leadless chip carrier (LCC) having electrode pads on the four sides and no lead pins, and a ball grid array (BGA) having a large number of spherical terminals made of solder on the lower surface of the insulating substrate. It is said that the highest density is possible.

【０００６】このボールグリッドアレイ（ＢＧＡ）は接
続端子を接続パッドに半田などのロウ材からなる球状端
子をロウ付けした端子により構成し、この球状端子を外
部電気回路基板の配線導体上に載置当接させ、しかる
後、この端子を約２５０〜４００℃の温度で加熱溶融
し、球状端子を配線導体に接合させることによって外部
電気回路基板上に実装することが行われている。このよ
うな実装構造により、半導体素子収納用パッケージの内
部に収容されている半導体素子はその各電極がメタライ
ズ配線層及び接続端子を介して外部電気回路に電気的に
接続される。In this ball grid array (BGA), connection terminals are constituted by terminals in which spherical terminals made of a brazing material such as solder are soldered to connection pads, and the spherical terminals are mounted on wiring conductors of an external electric circuit board. After that, the terminal is heated and melted at a temperature of about 250 to 400 ° C., and the spherical terminal is bonded to a wiring conductor to be mounted on an external electric circuit board. With such a mounting structure, each electrode of the semiconductor element housed in the semiconductor element housing package is electrically connected to an external electric circuit via the metallized wiring layer and the connection terminal.

【０００７】また、半導体素子収納用パッケージにおけ
る絶縁基板としては、これまでアルミナやムライトなど
の焼結体が用いられているが、最近では、低温で焼結が
可能で、配線層として安価なＣｕやＡｇ等を用いること
ができるとして、ガラス−セラミックスなどの焼結体
が、例えば、特開昭５０−１１９８１４号、特開昭５８
−１７６６５１号、特公平３−５９０２９号、特公平３
−３７７５８号等にて提案されている。Further, a sintered body such as alumina or mullite has been used as an insulating substrate in a package for housing a semiconductor element, but recently, it is possible to sinter at a low temperature and to use an inexpensive Cu as a wiring layer. Sintered bodies such as glass-ceramics can be used, for example, as disclosed in Japanese Patent Application Laid-Open Nos.
No. 1766651, No. 3-59029, No. 3
No. 37758 and the like.

【０００８】[0008]

【発明が解決しようとする課題】これらのパッケージに
おける絶縁基板として一般に使用されているアルミナ、
ムライトなどのセラミックスは、２００ＭＰａ以上の高
強度を有するものの、その熱膨張係数は約４〜７ｐｐｍ
／℃程度であるのに対して、外部電気回路基板として最
も多用されるガラス−エポキシなどのプリント基板の熱
膨張係数は１２〜１８ｐｐｍ／℃と非常に大きい。Alumina generally used as an insulating substrate in these packages,
Ceramics such as mullite have a high strength of 200 MPa or more, but have a coefficient of thermal expansion of about 4 to 7 ppm.
/ ° C., whereas the thermal expansion coefficient of a printed circuit board such as glass-epoxy, which is most frequently used as an external electric circuit board, is as large as 12 to 18 ppm / ° C.

【０００９】そのため、半導体素子収納用パッケージを
上記プリント基板などの外部電気回路基板に実装した場
合、作動時に発する熱が絶縁基板と外部電気回路基板の
両方に繰り返し印加されると絶縁基板と外部電気回路基
板との間の熱膨張係数差に起因する大きな熱応力が発生
する。この熱応力は、パッケージにおける端子数が３０
０以下の比較的少なく、パッケージ自体が小型である場
合には影響は小さいが、端子数が増大するとともにパッ
ケージが大型化するに従い、その影響が増大する傾向に
ある。Therefore, when the package for housing the semiconductor element is mounted on an external electric circuit board such as the above-mentioned printed circuit board, if the heat generated during operation is repeatedly applied to both the insulating substrate and the external electric circuit board, the insulating board and the external electric A large thermal stress occurs due to a difference in thermal expansion coefficient between the circuit board and the circuit board. This thermal stress is caused when the number of terminals in the package is 30.
If the package itself is small, the effect is small, but the influence tends to increase as the number of terminals increases and the package increases in size.

【００１０】例えば、半導体装置の作動および停止の繰
り返しにより熱応力が繰り返し印加されると、この熱応
力がパッケージの絶縁基板下面の接続端子や、接続端子
と外部電気回路基板の配線導体との接合界面に作用し、
その結果、接続端子が絶縁基板より剥離したり、接続端
子が回路基板の配線導体から剥離し、半導体素子収納用
パッケージの接続端子を外部電極回路の配線導体に長期
にわたり安定に電気的接続させることができないという
欠点を有していた。For example, when thermal stress is repeatedly applied by repeating the operation and stop of the semiconductor device, the thermal stress is applied to the connection terminals on the lower surface of the insulating substrate of the package, or to the connection between the connection terminals and the wiring conductors of the external electric circuit board. Acts on the interface,
As a result, the connection terminals are separated from the insulating substrate or the connection terminals are separated from the wiring conductor of the circuit board, and the connection terminals of the package for housing the semiconductor element are stably electrically connected to the wiring conductor of the external electrode circuit for a long time. Had the drawback that it could not be done.

【００１１】このような傾向は、パッケージ構造上、接
続端子や金属ピンからなるＰＧＡの場合にはピン自体が
応力を緩衝するが、前述したＱＦＰ、ＢＧＡなどのよう
に外部電気回路基板に直接的に接続される構造のパッケ
ージをにおいては、基板が大型化した場合には致命的な
欠点となっていた。In the case of PGA composed of connection terminals and metal pins due to the package structure, such a tendency is such that the pins themselves buffer the stress, but are directly connected to an external electric circuit board such as the above-mentioned QFP and BGA. In the case of a package having a structure to be connected to a semiconductor device, a fatal drawback occurs when the size of the substrate is increased.

【００１２】また、上述した公報により提案される従来
のガラスセラミミック焼結体においても、Ｓｉ基板から
なる半導体素子との熱膨張係数の整合が重視されるた
め、それらの熱膨張係数はせいぜい８ｐｐｍ／℃程度で
あり、プリント基板との熱膨張係数差にかかる問題につ
いてはほとんど検討されていないのが現状であった。Also, in the conventional glass ceramic sintered body proposed in the above-mentioned publication, matching of the coefficient of thermal expansion with the semiconductor element made of the Si substrate is important, so that their coefficient of thermal expansion is at most 8 ppm. / ° C., and there has been almost no study on the problem relating to the difference in thermal expansion coefficient from the printed circuit board.

【００１３】従って、本発明は、高熱膨張特性を有する
絶縁基板の表面あるいは内部にメタライズ配線層を具備
する配線基板や、高熱膨張特性を有し且つ半導体素子が
収納された半導体素子収納用パッケージをガラス−エポ
キシ樹脂等を絶縁体とする外部電気回路に対して、強固
に且つ長期にわたり安定した接続状態を維持できる高信
頼性の配線基板になりうるガラス−セラミック焼結体
と、それを用いた配線基板とを提供することを目的とす
るものである。Accordingly, the present invention provides a wiring board having a metallized wiring layer on the surface or inside of an insulating substrate having high thermal expansion characteristics, and a semiconductor element storage package having high thermal expansion characteristics and housing semiconductor elements. A glass-ceramic sintered body that can be a highly reliable wiring board capable of maintaining a stable and stable connection state for a long time with respect to an external electric circuit using glass-epoxy resin or the like as an insulator, and using the same. It is an object to provide a wiring board.

【００１４】[0014]

【課題を解決するための手段】本発明のガラスセラミッ
ク焼結体は、結晶相５０〜９９重量％と、ガラス相１〜
５０重量％から構成され、前記結晶相として、フォルス
テライト及びエンスタタイトを合計で２０〜８５重量％
含有するとともに、４０〜４００℃における熱膨張係数
が８〜１８ｐｐｍ／℃であることを特徴とするガラス−
セラミック焼結体であり、さらには結晶相中にはリチウ
ムシリケートを含むことを特徴とするものである。According to the present invention, there is provided a glass ceramic sintered body having a crystal phase of 50 to 99% by weight and a glass phase of 1 to 99% by weight.
50% by weight, and forsterite and enstatite in a total amount of 20 to 85% by weight as the crystal phase.
A glass characterized by containing and having a coefficient of thermal expansion at 40 to 400 ° C. of 8 to 18 ppm / ° C.
It is a ceramic sintered body, and is further characterized in that the crystal phase contains lithium silicate.

【００１５】また、本発明によれば、絶縁基板の表面あ
るいは内部にメタライズ配線層が配設された配線基板に
おいて、絶縁基板が、結晶相５０〜９９重量％と、ガラ
ス相１〜５０重量％から構成され、前記結晶相として、
フォルステライト及びエンスタタイトを合計で２０〜８
５重量％含有するとともに、４０〜４００℃における熱
膨張係数が８〜１８ｐｐｍ／℃のガラス−セラミック焼
結体からなることを特徴とするものである。Further, according to the present invention, in a wiring board having a metallized wiring layer disposed on the surface or inside of the insulating substrate, the insulating substrate has a crystal phase of 50 to 99% by weight and a glass phase of 1 to 50% by weight. And, as the crystal phase,
20-8 total forsterite and enstatite
It is characterized by comprising a glass-ceramic sintered body containing 5% by weight and having a coefficient of thermal expansion at 40 to 400 ° C of 8 to 18 ppm / ° C.

【００１６】[0016]

【作用】本発明では、ガラス−エポキシ基板などのプリ
ント基板からなる外部電気回路に対して実装される半導
体素子収納用パッケージ等の配線基板における絶縁基板
として４０〜４００℃の温度範囲における線熱膨張係数
が８〜１８ｐｐｍ／℃のセラミックスを用いることによ
り、絶縁基板と外部電気回路基板との間に両者の線熱膨
張係数の差が小さくなり、その結果、絶縁基板と外部電
気回路基板の線熱膨張係数の相違に起因する熱応力によ
って端子が外部電気回路の配線導体とが接続不良を起こ
すことがなく、これによっても容器内部に収容する半導
体素子と外部電気回路とを長期間にわたり正確に、且つ
強固に電気的接続させることが可能となる。According to the present invention, a linear thermal expansion in a temperature range of 40 to 400 ° C. is used as an insulating substrate in a wiring board such as a package for storing semiconductor elements mounted on an external electric circuit formed of a printed board such as a glass-epoxy board. By using a ceramic having a coefficient of 8 to 18 ppm / ° C., the difference in linear thermal expansion coefficient between the insulating substrate and the external electric circuit board is reduced, and as a result, the linear heat of the insulating substrate and the external electric circuit board is reduced. The terminal does not cause a connection failure between the terminal and the wiring conductor of the external electric circuit due to the thermal stress caused by the difference in the expansion coefficient, and thus the semiconductor element and the external electric circuit housed in the container can be accurately connected for a long time. In addition, it is possible to make a strong electrical connection.

【００１７】本発明において結晶相を構成するフォルス
テライトは、それ自体が１０ｐｐｍ／℃、エンスタタイ
トは９ｐｐｍ／℃、リチウムシリケートは１２ｐｐｍ／
℃の高熱膨張係数を有するため、これらの結晶相とガラ
ス相によって、焼結体の熱膨張係数を８〜１８ｐｐｍ／
℃の範囲で容易に制御することができる。In the present invention, forsterite constituting the crystal phase itself is 10 ppm / ° C., enstatite is 9 ppm / ° C., and lithium silicate is 12 ppm / ° C.
° C, the thermal expansion coefficient of the sintered body is from 8 to 18 ppm /
It can be easily controlled in the range of ° C.

【００１８】なお、ガラスセラミック焼結体において、
結晶相としてフォルステライトに加えて、エンスタタイ
トを含有せしめることによりガラスとフォルステライト
の結合を高め、焼結性を高めることができる。即ち、エ
ンスタタイトの一部はガラスとフォルステライトとの反
応によって生成したものであり、リチウムシリケートを
ガラス相からの析出させることにより、ガラス相の強化
することができる。In the glass ceramic sintered body,
By adding enstatite in addition to forsterite as a crystal phase, the binding between glass and forsterite can be enhanced, and sinterability can be enhanced. That is, part of enstatite is generated by the reaction between glass and forsterite, and the glass phase can be strengthened by depositing lithium silicate from the glass phase.

【００１９】また、本発明のガラスセラミック焼結体
は、８００〜１０００℃の低温で焼成することができる
ため、配線基板や半導体素子収納用パッケージにおける
配線層として、Ｃｕ、Ａｇなどの安価な導体により形成
することができるため、製品のコストを低減することが
できる。Further, since the glass ceramic sintered body of the present invention can be fired at a low temperature of 800 to 1000 ° C., it can be used as an inexpensive conductor such as Cu or Ag as a wiring layer in a wiring board or a package for housing a semiconductor element. Therefore, the cost of the product can be reduced.

【００２０】[0020]

【発明の実施の形態】以下、本発明を一実施例を示す添
付図面に基づき詳細に説明する。図１及び図２はボール
グリッドアレイ（ＢＧＡ）型の半導体素子収納用パッケ
ージとその実装構造の一実施例を示し、Ａは半導体素子
収納用パッケージ、Ｂは外部電気回路基板である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings showing an embodiment. 1 and 2 show one embodiment of a ball grid array (BGA) type semiconductor element storage package and its mounting structure, wherein A is a semiconductor element storage package, and B is an external electric circuit board.

【００２１】半導体素子収納用パッケージＡは、絶縁基
板１と蓋体２とメタライズ配線層３と端子４およびパッ
ケージの内部に収納される半導体素子５により構成さ
れ、絶縁基板１及び蓋体２は半導体素子５を内部に気密
に収容するための容器６を構成する。つまり、絶縁基板
１は上面中央部に半導体素子５が載置収容される凹部１
ａが設けてあり、凹部１ａ底面には半導体素子５はガラ
ス、樹脂等の接着剤を介して接着固定される。A package A for housing a semiconductor element is composed of an insulating substrate 1, a lid 2, a metallized wiring layer 3, terminals 4, and a semiconductor element 5 housed inside the package. A container 6 for hermetically housing the element 5 therein is formed. In other words, the insulating substrate 1 has a concave portion 1 in which the semiconductor element 5 is placed and accommodated in the center of the upper surface.
The semiconductor element 5 is bonded and fixed to the bottom surface of the concave portion 1a via an adhesive such as glass or resin.

【００２２】また、絶縁基板１には半導体素子５が載置
収容される凹部１ａの周辺から下面にかけて複数個のメ
タライズ配線層３が被着形成されている。更に絶縁基板
１の下面には図２に示すように多数の凹部１ｂが設けら
れており、凹部１ｂの底面にはメタライズ配線層３と電
気的に接続された接続パッド３ａが被着形成されてい
る。この接続パッド３ａの表面には、外部電気回路基板
Ｂの表面に形成された配線導体８との接続端子として、
半田（錫−鉛合金）などのロウ材から成る突起状端子４
が形成されている。この突起状端子４は、球状もしくは
柱状のロウ材を接続パッド３ａに並べるか、またはスク
リーン印刷法によりロウ材を接続パッド上に印刷するこ
とにより形成される。A plurality of metallized wiring layers 3 are formed on the insulating substrate 1 from the periphery to the lower surface of the concave portion 1a in which the semiconductor element 5 is mounted. Further, as shown in FIG. 2, a large number of concave portions 1b are provided on the lower surface of the insulating substrate 1, and connection pads 3a electrically connected to the metallized wiring layer 3 are formed on the bottom surface of the concave portion 1b. I have. On the surface of the connection pad 3a, as a connection terminal with a wiring conductor 8 formed on the surface of the external electric circuit board B,
Projecting terminal 4 made of brazing material such as solder (tin-lead alloy)
Is formed. The protruding terminals 4 are formed by arranging spherical or column-shaped brazing materials on the connection pads 3a or by printing brazing materials on the connection pads by a screen printing method.

【００２３】この接続パッド３ａに取着されている接続
端子４は絶縁基板１の下面に突出部４ａを有しており、
半導体素子５の各電極が接続されている接続パッド３ａ
を外部電気回路基板Ｂの配線導体８に接続させるととも
に半導体素子収納用パッケージＡを外部電気回路基板Ｂ
上に実装させる作用を為す。The connection terminal 4 attached to the connection pad 3a has a protrusion 4a on the lower surface of the insulating substrate 1,
Connection pad 3a to which each electrode of semiconductor element 5 is connected
Is connected to the wiring conductor 8 of the external electric circuit board B, and the semiconductor element housing package A is connected to the external electric circuit board B.
It works on top.

【００２４】なお、接続パッド３ａと電気的に接続され
たメタライズ配線層３は、半導体素子５の各電極とボン
ディングワイヤ７を介して電気的に接続されることによ
り、半導体素子の電極は、接続パッド３ａと電気的に接
続されることになる。The metallized wiring layer 3 electrically connected to the connection pad 3a is electrically connected to each electrode of the semiconductor element 5 via a bonding wire 7, so that the electrodes of the semiconductor element are connected. It is electrically connected to the pad 3a.

【００２５】一方、外部電気回路基板Ｂとしては、絶縁
体９と配線導体８により構成されており、絶縁体９は、
少なくとも有機樹脂を含む材料からなるプリント基板か
らなる。具体的にはガラス−エポキシ系複合材料等のよ
うに４０〜４００℃における熱膨張係数が１２〜１６ｐ
ｐｍ／℃の絶縁材料からなる。また、この回路基板Ｂの
表面に実装される配線導体８は、絶縁体との熱膨張係数
の整合性と、良電気伝導性の点で、通常、Ｃｕ、Ａｕ、
Ａｌ、Ｎｉ、Ｐｂ−Ｓｎ等の金属導体からなる。On the other hand, the external electric circuit board B includes an insulator 9 and a wiring conductor 8, and the insulator 9
It consists of a printed circuit board made of a material containing at least an organic resin. Specifically, the coefficient of thermal expansion at 40 to 400 ° C. is 12 to 16p such as a glass-epoxy composite material.
It is made of an insulating material of pm / ° C. The wiring conductor 8 mounted on the surface of the circuit board B is usually made of Cu, Au,
It is made of a metal conductor such as Al, Ni, and Pb-Sn.

【００２６】上記半導体素子収納用パッケージＡを上記
外部電気回路基板Ｂに実装するには、パッケージＡの絶
縁基板１下面の接続パッド３ａに取着されている半田か
ら成る突起状端子４を外部電気回路基板Ｂの配線導体８
上に載置当接させ、しかる後、約２５０〜４００℃の温
度で加熱することにより、半田などのロウ材からなる突
起状端子４自体が溶融し、端子４を配線導体８に接合さ
せることによって外部電気回路基板Ｂ上に実装される。
この時、配線導体８の表面には端子４とのロウ材による
接続を容易に行うためにロウ材が被着されていることが
望ましい。To mount the semiconductor element housing package A on the external electric circuit board B, the projecting terminals 4 made of solder attached to the connection pads 3a on the lower surface of the insulating substrate 1 of the package A are connected to the external electric circuit board B. Wiring conductor 8 of circuit board B
The protruding terminal 4 itself made of a brazing material such as solder is melted by placing the terminal 4 on the upper surface and then heating at a temperature of about 250 to 400 ° C. to join the terminal 4 to the wiring conductor 8. On the external electric circuit board B.
At this time, it is desirable that a brazing material is attached to the surface of the wiring conductor 8 in order to easily connect the terminal 4 with the brazing material.

【００２７】また、他の例として、図３に示すように前
記接続端子として、接続パッド３ａに対して高融点材料
からなる球状端子１０を低融点ロウ材１１によりロウ付
けしたものが適用できる。この高融点材料は、ロウ付け
に使用される低融点ロウ材よりも高融点であることが必
要で、ロウ付け用ロウ材が例えばＰｂ４０重量％−Ｓｎ
６０重量％の低融点の半田からなる場合、球状端子は例
えばＰｂ９０重量％−Ｓｎ１０重量％の高融点半田や、
Ｃｕ、Ａｇ、Ｎｉ、Ａｌ、Ａｕ、Ｐｔ、Ｆｅなどの金属
により構成される。かかる構成においてはパッケージＡ
の絶縁基板１下面の接続パッド３ａに取着されている球
状端子１０を外部電気回路基板Ｂの配線導体８上に載置
当接させ、しかる後、球状端子１０を半田などのロウ材
１２により配線導体８に接着させて外部電気回路基板Ｂ
上に実装することができる。また、低融点のロウ材とし
てＡｕ−Ｓｎ合金を用いて接続端子を外部電気回路基板
に接続してもよく、さらに上記球状端子に代わりに柱状
の端子を用いてもよい。As another example, as shown in FIG. 3, as the connection terminal, one obtained by brazing a spherical terminal 10 made of a high melting point material to a connection pad 3a with a low melting point brazing material 11 can be applied. This high melting point material needs to have a higher melting point than the low melting point brazing material used for brazing, and the brazing material is, for example, 40% by weight of Pb-Sn.
In the case of a solder having a low melting point of 60% by weight, the spherical terminal is, for example, a high melting point solder of 90% by weight of Pb-10% by weight of Sn,
It is made of a metal such as Cu, Ag, Ni, Al, Au, Pt, and Fe. In such a configuration, the package A
The spherical terminal 10 attached to the connection pad 3a on the lower surface of the insulating substrate 1 is placed and abutted on the wiring conductor 8 of the external electric circuit board B, and then the spherical terminal 10 is soldered with a brazing material 12 such as solder. The external electric circuit board B is bonded to the wiring conductor 8.
Can be implemented on top. The connection terminal may be connected to an external electric circuit board using an Au-Sn alloy as a low melting point brazing material, and a columnar terminal may be used instead of the spherical terminal.

【００２８】次に、図４をもとにリードレスチップキャ
リア（ＬＣＣ）型の半導体素子収納用パッケージＣの外
部電気回路基板Ｂへの実装構造について説明する。この
図４において、前記図１と同一部材には、同一の番号を
付与した。図４におけるパッケージＣでは、メタライズ
配線層３が絶縁基板１の側面に導出され、その側面に導
出されたメタライズ層が接続端子４を構成している。ま
た、このパッケージＣでは、例えば、電磁波障害を防止
するために、半導体素子５を収納する凹部１ａにエポキ
シ樹脂等が充填され、また、凹部は導電性樹脂からなる
蓋体１３により密閉されている。また、パッケージＣの
底面にはアースのための導電層１４が形成されている。Next, the mounting structure of the leadless chip carrier (LCC) type semiconductor element housing package C on the external electric circuit board B will be described with reference to FIG. 4, the same members as those in FIG. 1 are denoted by the same reference numerals. In the package C in FIG. 4, the metallized wiring layer 3 is led out to the side surface of the insulating substrate 1, and the metallized layer led out to the side surface constitutes the connection terminal 4. In this package C, for example, in order to prevent electromagnetic interference, the concave portion 1a for housing the semiconductor element 5 is filled with an epoxy resin or the like, and the concave portion is sealed with a lid 13 made of a conductive resin. . Further, a conductive layer 14 for grounding is formed on the bottom surface of the package C.

【００２９】このパッケージＣを外部電気回路基板Ｂに
実装するには、パッケージＣの絶縁基板１側面の接続端
子４を外部電気回路基板Ｂの配線導体８上に載置当接さ
せてロウ材等により電気的に接続する。この時、接続端
子４や配線導体８の表面にはロウ材による接続を容易に
行うために表面にロウ材が被着形成されていることが望
ましい。In order to mount the package C on the external electric circuit board B, the connection terminals 4 on the side of the insulating substrate 1 of the package C are placed on the wiring conductors 8 of the external electric circuit board B so as to be in contact with the brazing material. For electrical connection. At this time, it is desirable that the surface of the connection terminal 4 and the wiring conductor 8 is formed with a brazing material so as to be easily connected by the brazing material.

【００３０】本発明によれば、このような外部電気回路
基板Ｂの表面に実装される半導体素子収納用パッケージ
として、その絶縁基板１を構成するガラスセラミック焼
結体が４０〜４００℃の温度範囲における線熱膨張係数
が８〜１８ｐｐｍ／℃、特に９〜１４ｐｐｍ／℃の焼結
体からなることが重要である。これは、前述した外部電
気回路基板Ｂとの熱膨張差により熱応力の発生を緩和
し、外部電気回路基板ＢとパッケージＡとの電気的接続
状態を長期にわたり良好な状態に維持するために重要で
あり、この線熱膨張係数が８ｐｐｍ／℃より小さいか、
あるいは１８ｐｐｍ／℃より大きいと、いずれも熱膨張
差に起因する熱応力が大きくなり、外部電気回路基板Ｂ
とパッケージＡとの電気的接続状態が悪化することを防
止することができない。According to the present invention, as a package for housing a semiconductor element mounted on the surface of such an external electric circuit board B, the glass-ceramic sintered body constituting the insulating substrate 1 has a temperature range of 40 to 400 ° C. It is important that the sintered body has a linear thermal expansion coefficient of 8 to 18 ppm / ° C., particularly 9 to 14 ppm / ° C. This is important to alleviate the generation of thermal stress due to the difference in thermal expansion between the external electric circuit board B and the external electric circuit board B, and to maintain a good electrical connection between the external electric circuit board B and the package A for a long time. The coefficient of linear thermal expansion is less than 8 ppm / ° C.,
Alternatively, if it is higher than 18 ppm / ° C., the thermal stress caused by the difference in thermal expansion becomes large, and the external electric circuit board B
Deterioration of the electrical connection between the package and the package A cannot be prevented.

【００３１】なお、絶縁基板の熱膨張係数が８〜１８ｐ
ｐｍ／℃と大きくなるに伴い、Ｓｉを基板とする半導体
素子との熱膨張差が逆に大きくなってしまうため、絶縁
基板１に半導体素子５を接着するには、そのガラス、有
機系接着財などのから適宜選択することが必要である。
熱膨張係数差による応力を緩衝するには、可撓性の材料
により構成することが望ましく、例えば、エポキシ系、
ポリイミド系の有機系接着材や、この接着材にＡｇなど
の金属を添加したものが好適に使用される。The thermal expansion coefficient of the insulating substrate is 8-18p
With the increase in pm / ° C., the difference in thermal expansion between the semiconductor element and the semiconductor element having Si as the substrate increases. It is necessary to appropriately select from among them.
In order to buffer the stress due to the difference in the coefficient of thermal expansion, it is desirable that the material be made of a flexible material.
A polyimide organic adhesive or a material obtained by adding a metal such as Ag to this adhesive is preferably used.

【００３２】上記の配線基板の絶縁基板を構成する本発
明のガラスセラミック焼結体は、結晶相５０〜９９重量
％と、ガラス相１〜５０重量％から構成されるものであ
り、結晶相中に、フォルステライト及びエンスタタイト
を合計で全量中２０〜８５重量％の割合で含有すること
が重要である。フォルステライトは、それ自体で熱膨張
係数が１０ｐｐｍ／℃、エンステタイトが９ｐｐｍ／℃
といずれも高い熱膨張係数を有するものであり、これら
の結晶相を含有することにより、高熱膨張特性を安定に
得られる。The glass-ceramic sintered body of the present invention, which constitutes the insulating substrate of the above-mentioned wiring board, comprises 50 to 99% by weight of a crystal phase and 1 to 50% by weight of a glass phase. In addition, it is important that forsterite and enstatite are contained in a total amount of 20 to 85% by weight based on the total amount. Forsterite itself has a coefficient of thermal expansion of 10 ppm / ° C and enstatite at 9 ppm / ° C.
All have a high thermal expansion coefficient, and by including these crystal phases, high thermal expansion characteristics can be stably obtained.

【００３３】フォルステライト及びエンスタタイトの量
が２０重量％より少ないと熱膨張係数を８〜１８ｐｐｍ
／℃の範囲に制御することが難 くなるとともに、ガラ
スの含有量が増加し、製品単価が高くなる原因になる。
逆に、８５重量％より多いと、焼結不良となり、緻密な
焼結体が得られない。好ましくは、６０〜７５重量％が
良い。When the amount of forsterite and enstatite is less than 20% by weight, the thermal expansion coefficient is 8 to 18 ppm.
It is difficult to control the temperature in the range of / ° C, and at the same time, the content of glass increases, which causes an increase in product unit price.
Conversely, if the content is more than 85% by weight, sintering becomes poor, and a dense sintered body cannot be obtained. Preferably, the content is 60 to 75% by weight.

【００３４】また、本発明によれば、結晶相としてリチ
ウムシリケートをさらに含有することが望ましい。この
リチウムシリケートも１２ｐｐｍ／℃の熱膨張係数を有
することから高熱膨張化の安定化に寄与するとともに、
強度向上効果を有する。このリチウムシリケートは結晶
化ガラスから焼結過程で析出したものであることが望ま
しい。リチウムシリケート結晶を析出させるためには結
晶性ガラス中にＬｉ２Ｏ量が５〜３０重量％であること
が必要である。According to the present invention, it is desirable to further contain lithium silicate as a crystal phase. Since this lithium silicate also has a thermal expansion coefficient of 12 ppm / ° C., it contributes to stabilization of high thermal expansion,
Has an effect of improving strength. This lithium silicate is desirably precipitated from crystallized glass during the sintering process. In order to precipitate lithium silicate crystals, it is necessary that the amount of Li 2 O is 5 to 30% by weight in the crystalline glass.

【００３５】かかる観点から、結晶性ガラス組成は、Ｌ
ｉ２ Ｏ量を５〜３０重量％、ＳｉＯ2 を５０〜８５重
量％、Ａｌ2 Ｏ3 、ＭｇＯ、ＺｎＯ、Ｎａ2 Ｏ、ＴｉＯ
2 、Ｋ2 Ｏ、Ｐ2 Ｏ5 の群から選ばれる少なくとも１種
以上を５〜２０重量％の割合で含有する組成物が望まし
い。具体的な系としては、ＳｉＯ2 −Ｌｉ2 Ｏ−Ａｌ2
Ｏ3 、ＳｉＯ2 −Ｌｉ2 Ｏ−ＭｇＯ、ＳｉＯ2 −Ｌｉ2
Ｏ−ＺｎＯ、ＳｉＯ2 −Ｌｉ2 Ｏ−ＭｇＯ−Ａｌ2 Ｏ3
−Ｎａ2 Ｏ−Ｆ、ＳｉＯ2 −Ｌｉ2 Ｏ−ＭｇＯ−Ａｌ2
Ｏ3 −ＴｉＯ2 、ＳｉＯ2 −Ｌｉ2 Ｏ−Ａｌ2 Ｏ3 −Ｋ
2 Ｏ−Ｐ2 Ｏ5 、ＳｉＯ2 −Ｌｉ2 Ｏ−Ａｌ2 Ｏ3 −Ｋ
2 Ｏ−Ｎａ2 Ｏ−ＺｎＯ、ＳｉＯ2 −Ｌｉ2 Ｏ−Ａｌ2
Ｏ3 −Ｋ2 Ｏ−Ｎａ2 Ｏ−Ｐ2 Ｏ5 −ＺｎＯ、等が挙げ
られる。From this viewpoint, the crystalline glass composition is L
i 2 O content of 5 to 30 wt%, SiO 2 of 50 to 85 wt%, Al 2 O 3 , MgO, ZnO, Na 2 O, TiO
2, K 2 O, a composition containing at least one or more in a proportion of 5 to 20 wt% selected from the group consisting of P 2 O 5 is desirable. As a specific system, SiO 2 —Li 2 O—Al 2
O 3 , SiO 2 —Li 2 O—MgO, SiO 2 —Li 2
O-ZnO, SiO 2 -Li 2 O-MgO-Al 2 O 3
-Na 2 O-F, SiO 2 -Li 2 O-MgO-Al 2
O 3 -TiO 2, SiO 2 -Li 2 O-Al 2 O 3 -K
2 O—P 2 O 5 , SiO 2 —Li 2 O—Al 2 O 3 —K
2 O-Na 2 O-ZnO, SiO 2 -Li 2 O-Al 2
O 3 —K 2 O—Na 2 O—P 2 O 5 —ZnO; and the like.

【００３６】さらに、結晶相としては、熱膨張係数の制
御のために他の結晶成分を含有することもできる。他の
結晶成分としては、少なくとも４０〜４００℃における
熱膨張係数が６ｐｐｍ／℃以上の金属酸化物、例えば、
クリストバライト（ＳｉＯ2）、クォーツ（Ｓｉ
Ｏ2 ）、スピネル（ＭｇＯ・Ａｌ2 Ｏ3 ）、マグネシア
（ＭｇＯ）、アルミナ（Ａｌ2 Ｏ3 ）、ペタライト（Ｌ
ｉＡｌＳｉ4 Ｏ10）等を添加してもよい。Further, the crystal phase may contain other crystal components for controlling the coefficient of thermal expansion. As other crystal components, metal oxides having a thermal expansion coefficient of at least 6 ppm / ° C. at 40 to 400 ° C., for example,
Cristobalite (SiO 2 ), quartz (Si
O 2 ), spinel (MgO.Al 2 O 3 ), magnesia (MgO), alumina (Al 2 O 3 ), petalite (L
iAlSi 4 O 10 ) may be added.

【００３７】次に、上記のガラスセラミック焼結体を作
製するための具体的な方法について説明すると、出発原
料としてフォルステライト粉末とエンスタタイト粉末お
よび結晶化ガラス粉末を用いる方法と、フォルステライ
ト粉末と、結晶化ガラス粉末とを用いる方法がある。Next, a specific method for producing the above-mentioned glass ceramic sintered body will be described. For example, a method using forsterite powder, enstatite powder and crystallized glass powder as starting materials, a method using forsterite powder, And crystallized glass powder.

【００３８】前者の場合には、フォルステライト粉末と
エンスタタイト粉末とを２０〜８５重量％、残部を前述
した結晶化ガラスとなる組成で混合する。この混合物を
所望の成形手段、例えば、ドクターブレード法、金型プ
レス法、押出し成形法、圧延法等により任意の形状、例
えばシート状に成形後、酸化性雰囲気中で８００〜１０
００℃の温度で焼成することにより得られる。In the former case, the forsterite powder and the enstatite powder are mixed in an amount of 20 to 85% by weight, and the remainder is mixed with the above-mentioned composition to form the crystallized glass. The mixture is formed into a desired shape by a desired forming means, for example, a doctor blade method, a mold pressing method, an extrusion forming method, a rolling method, or the like, into a sheet shape, and then 800 to 10% in an oxidizing atmosphere.
It is obtained by firing at a temperature of 00 ° C.

【００３９】後者の場合には、エンスタタイト（ＭｇＯ
・ＳｉＯ2 ）は、フォルステライト（２ＭｇＯ・ＳｉＯ
2 ）よりもＳｉＯ2 が多量に含む成分であることから、
焼結過程においてフォルステライトの一部にＳｉＯ2 が
固溶反応してエンスタタイトに変換される反応を生じさ
せる。そのため、結晶化ガラス中に少なくともＳｉＯ2
が５０重量％以上含有される結晶化ガラスを用いて、フ
ォルステライトを２０〜８５重量％、残部が結晶化ガラ
スとなる組成で混合し、これを上述した方法により成形
後、酸化性雰囲気中で８００〜１０００℃の温度で焼成
することにより、エンスタタイトを生成させることがで
きる。In the latter case, enstatite (MgO
.SiO 2 ) is forsterite (2MgO.SiO)
Since 2 ) is a component containing a larger amount of SiO 2 than
In the sintering process, SiO 2 forms a solid solution reaction with a part of forsterite to cause a reaction to be converted into enstatite. Therefore, at least SiO 2 is contained in the crystallized glass.
Is mixed with 20 to 85% by weight of forsterite in a composition that makes the remaining part to be crystallized glass using a crystallized glass containing 50% by weight or more. By baking at a temperature of 800 to 1000 ° C., enstatite can be generated.

【００４０】本発明のガラスセラミック焼結体を用いて
配線基板を作製するには、絶縁基板を構成するための上
述した原料粉末に適当な有機バインダー、可塑剤、溶剤
を添加混合して泥漿物を作るとともに該泥漿物をドクタ
ーブレード法やカレンダーロール法を採用することによ
ってグリーンシート（生シート）と作製する。そして、
メタライズ配線層及び接続パッドを形成するため、Ｃ
ｕ、Ａｇ、Ｎｉ、Ｐｄ，Ａｕから選ばれる少なくとも１
種の金属粉末に有機バインダー、可塑剤、溶剤を添加混
合して得た金属ペーストを前記グリーンシートに周知の
スクリーン印刷法により所定パターンに印刷塗布する。
また、場合によっては、前記グリーンシートに適当な打
ち抜き加工してスルーホールを形成し、このホール内に
もメタライズペーストを充填する。そしてこれらのグリ
ーンシートを複数枚積層し、グリーンシートとメタライ
ズとを８００〜１０００℃で同時焼成することにより多
層構造の配線基板やパッケージを得ることができる。In order to manufacture a wiring board using the glass ceramic sintered body of the present invention, an appropriate organic binder, a plasticizer and a solvent are added to and mixed with the above-mentioned raw material powder for forming an insulating substrate. And a green sheet (raw sheet) is produced by employing the doctor blade method or the calendar roll method. And
To form a metallized wiring layer and connection pads, C
at least one selected from u, Ag, Ni, Pd, and Au
A metal paste obtained by adding an organic binder, a plasticizer, and a solvent to the seed metal powder is mixed and printed on the green sheet in a predetermined pattern by a known screen printing method.
In some cases, the green sheet is appropriately punched to form a through hole, and the hole is filled with a metallizing paste. By laminating a plurality of these green sheets and simultaneously firing the green sheets and metallization at 800 to 1000 ° C., a wiring board or package having a multilayer structure can be obtained.

【００４１】[0041]

【実施例】【Example】

実施例１ （焼結体作製）原料粉末として、純度９９％以上のフォ
ルステライト（２ＭｇＯ・ＳｉＯ2 ）粉末、純度９９％
以上のエンスタタイト（ＭｇＯ・ＳｉＯ2 ）粉末、およ
び以下の組成からなるガラスを準備した。なお、以下の
組成比は重量比率である。Example 1 (Preparation of sintered body) Forsterite (2MgO.SiO 2 ) powder having a purity of 99% or more as a raw material powder, purity of 99%
A glass having the above enstatite (MgO.SiO 2 ) powder and the following composition was prepared. The following composition ratios are weight ratios.

【００４２】 ７４％ＳｉＯ2 −１４％Ｌｉ2 Ｏ−４％Ａｌ2 Ｏ3 −２％Ｐ2 Ｏ5 −２％Ｋ2 Ｏ−２％ＺｎＯ−２％Ｎａ2 Ｏ （軟化点６００℃） ７８％ＳｉＯ2 −１０％Ｌｉ2 Ｏ−４％Ａｌ2 Ｏ3 −３％Ｋ2 Ｏ −３％Ｐ2 Ｏ5 −１％Ｎａ2 Ｏ−１％Ｂ2 Ｏ3 （軟化点８００℃） ５０％ＳｉＯ2 −９％Ｌｉ2 Ｏ−１３％Ａｌ2 Ｏ3 −２％Ｐ2 Ｏ3 −２％Ｋ2 Ｏ−２４％ＺｎＯ （軟化点１０００℃） これらを用いて表１，２に示す組成に秤量混合した後、
この混合物を粉砕後、有機バインダーを添加して十分に
混合した後、１軸プレス法により３．５×３．５×１５
ｍｍの形状の成形体を作製した。そして、この成形体を
７００℃のＮ2＋Ｈ2 Ｏ中で脱バインダ処理した後、大
気の雰囲気中で８５０〜１０００℃で焼成して焼結体を
作製した。74% SiO 2 -14% Li 2 O-4% Al 2 O 3 -2% P 2 O 5 -2% K 2 O-2% ZnO-2% Na 2 O (softening point 600 ° C.) 78 % SiO 2 -10% Li 2 O-4% Al 2 O 3 -3% K 2 O -3% P 2 O 5 -1% Na 2 O-1% B 2 O 3 (softening point 800 ° C) 50% SiO 2 -9% Li 2 O-13% Al 2 O 3 -2% P 2 O 3 -2% K 2 O-24% ZnO (softening point 1000 ° C.) After weighing and mixing,
After the mixture was pulverized, an organic binder was added and mixed well, and then 3.5 × 3.5 × 15 by a uniaxial pressing method.
A molded article having a shape of mm was produced. Then, the molded body was subjected to a binder removal treatment in N 2 + H 2 O at 700 ° C., and then fired at 850 to 1000 ° C. in an air atmosphere to produce a sintered body.

【００４３】（物性評価）次に、得られた焼結体に対し
て４０〜４００℃の線熱膨張係数を測定し表１，２に示
した。また、焼結体を直径６０ｍｍ、厚さ２ｍｍに加工
し、ＪＩＳＣ２１４１の手法で比誘電率と誘電損失を求
めた。測定はＬＣＲメータ（Ｙ．Ｈ．Ｐ４２８４Ａ）を
用いて行い、１ＭＨｚ，１．０Ｖｒｓｍの条件で２５℃
における静電容量を測定し、この静電容量から２５℃に
おける比誘電率を測定した。また、Ｘ線回折測定により
結晶相の同定と検量線法により結晶相の定量を行った。(Evaluation of Physical Properties) Next, linear thermal expansion coefficients of the obtained sintered bodies at 40 to 400 ° C. were measured and are shown in Tables 1 and 2. Further, the sintered body was processed into a diameter of 60 mm and a thickness of 2 mm, and the relative dielectric constant and the dielectric loss were determined by the method of JISC2141. The measurement was performed using an LCR meter (YHP4284A) at 25 ° C. under the conditions of 1 MHz and 1.0 Vrsm.
Was measured, and the relative dielectric constant at 25 ° C. was measured from the capacitance. The crystal phase was identified by X-ray diffraction measurement, and the crystal phase was quantified by the calibration curve method.

【００４４】次に、表１，２における各原料組成物を用
いて、溶媒としてトルエンとイソプロピルアルコール、
バインダーとしてアクリル樹脂、可塑剤としてＤＢＰ
（ジブチルフタレート）を用いてドクターブレード法に
より厚み５００μｍのグリーンシートを作製した。この
グリーンシートの表面にスクリーン印刷法によりＣｕメ
タライズペーストを塗布した。また、グリーンシートの
所定箇所に基板の下面まで通過するスルーホールを形成
しそのスルーホール内にもＣｕメタライズペーストを充
填した。そして、メタライズペーストが塗布されたグリ
ーンシートをスルーホールの位置合わせを行いながら６
枚積層し圧着した。Next, using each raw material composition in Tables 1 and 2, toluene and isopropyl alcohol were used as solvents.
Acrylic resin as binder, DBP as plasticizer
A green sheet having a thickness of 500 μm was prepared by a doctor blade method using (dibutyl phthalate). A Cu metallizing paste was applied to the surface of the green sheet by a screen printing method. Further, a through hole was formed at a predetermined portion of the green sheet to pass through to the lower surface of the substrate, and the through hole was filled with a Cu metallizing paste. Then, while aligning the through holes with the green sheet coated with the metallizing paste, 6
The sheets were laminated and pressed.

【００４５】この積層体を８００〜１０００℃の焼成温
度で脱バインダー工程：Ｎ2 ＋Ｈ2Ｏ、本焼成：Ｎ2 の
雰囲気中でメタライズ配線層と絶縁基板とを同時に焼成
しパッケージ用の配線基板を作製した。A binder is removed from the laminate at a firing temperature of 800 to 1000 ° C. in a debinding step: N 2 + H 2 O, and a final firing is performed by simultaneously firing the metallized wiring layer and the insulating substrate in an atmosphere of N 2. Was prepared.

【００４６】次に、配線基板の下面にスルーホールに接
続する箇所に凹部を形成しＣｕメタライズからなる接続
パッドを作製した。そして、その接続パッドに図１に示
すように半田（錫３０〜１０％−鉛７０〜９０％）から
なる接続端子を取着した。なお、接続端子は、１ｃｍ2
当たり３０端子の密度で配線基板の下面全体に形成し
た。Next, a concave portion was formed on the lower surface of the wiring substrate at a position connected to the through hole, and a connection pad made of Cu metallized was manufactured. Then, connection terminals made of solder (30 to 10% of tin-70 to 90% of lead) were attached to the connection pads as shown in FIG. The connection terminal is 1 cm 2
It was formed on the entire lower surface of the wiring board at a density of 30 terminals per contact.

【００４７】一方、ガラス−エポキシ複合材料からなる
４０〜８００℃における線熱膨張係数が１３ｐｐｍ／℃
の絶縁体の表面に銅箔からなる配線導体が形成されたプ
リント基板を準備した。On the other hand, the linear thermal expansion coefficient of the glass-epoxy composite material at 40 to 800 ° C. is 13 ppm / ° C.
A printed circuit board having a wiring conductor made of copper foil formed on the surface of the insulator was prepared.

【００４８】そして、上記のパッケージ用配線基板とプ
リント基板とを、配線基板の接続端子と配線導体とが接
続されるように位置合わせし、これをＮ2 の雰囲気中で
２６０℃で３分間熱処理しパッケージ用配線基板をプリ
ント基板表面に実装した。この熱処理によりパッケージ
用配線基板の半田からなる接続端子が溶けてプリント基
板の配線導体と電気的に接続されたことを確認した。Then, the package wiring board and the printed board are aligned with each other so that the connection terminals of the wiring board and the wiring conductors are connected, and this is heat-treated at 260 ° C. for 3 minutes in an N 2 atmosphere. The package wiring board was mounted on the surface of the printed circuit board. By this heat treatment, it was confirmed that the solder connection terminals of the package wiring board were melted and electrically connected to the wiring conductors of the printed circuit board.

【００４９】[0049]

【表１】 [Table 1]

【００５０】[0050]

【表２】 [Table 2]

【００５１】表１、２より明らかなように、結晶化ガラ
スのみを配合した試料Ｎo.１０では、８００℃で緻密化
するためＣｕ等のメタライズとの同時焼成ができなかっ
た。また、ガラスとしてＳｉＯ2 量の少ないのガラス
を用いた試料Ｎo.２１では、フォルステライトとの反応
によるエンスタタイトの生成がなく、焼結体もボイドを
多量に含むものであった。そこで、試料Ｎo.２２に示す
ように、ガラス量を増やしてエンスタタイトを生成させ
たが、その量はわずかでありしかもガラス自体の軟化点
が高いために焼結不良を生じた。また、フォルステライ
トとエンスタタイトの合計量を８５重量％を越えるに
は、試料Ｎo.２３のようにフィラーを多量に含める必要
があり、そのため１１００℃の温度でも焼結不良を生じ
た。As is clear from Tables 1 and 2, Sample No. 10 containing only crystallized glass could not be co-fired with metallization of Cu or the like because of densification at 800 ° C. In sample No. 21 using glass having a small amount of SiO 2 as the glass, no enstatite was generated by the reaction with forsterite, and the sintered body also contained a large amount of voids. Thus, as shown in Sample No. 22, enstatite was generated by increasing the amount of glass, but the amount was small and the softening point of the glass itself was high, resulting in poor sintering. Further, if the total amount of forsterite and enstatite exceeds 85% by weight, it is necessary to include a large amount of filler as in Sample No. 23, so that sintering failure occurred even at a temperature of 1100 ° C.

【００５２】これに対して、それ以外の本発明の試料
は、４０〜４００℃における熱膨張係数８〜１８ｐｐｍ
／℃であり、且つ８００〜１０００℃の温度で緻密化さ
れるためにＣｕなどの配線層との同時焼成が可能であっ
た。しかも、誘電率や誘電損失も良好な特性を示した。On the other hand, the other samples of the present invention have a thermal expansion coefficient of 8 to 18 ppm at 40 to 400 ° C.
/ ° C. and densification at a temperature of 800 to 1000 ° C., thus enabling simultaneous firing with a wiring layer such as Cu. In addition, the dielectric constant and the dielectric loss exhibited good characteristics.

【００５３】また、本発明による配線基板をプリント基
板表面に実装したものを大気中にて−４０℃と１２５℃
の各温度に制御した恒温槽に試験サンプルを１５分／１
５分の保持を１サイクルとして最高１０００サイクル繰
り返した結果、いずれも１０００サイクル経過後も配線
基板とプリント基板間には電気的抵抗の変化は全く認め
られず、極めて安定した良好な電気的接続状態を維持で
きた。因みに、市販の熱膨張係数が６ｐｐｍ／℃のガラ
スセラミック配線基板に対して、同様な試験を行った結
果、約２００サイクルで電気抵抗が大きくなる変化が見
られた。Further, the circuit board according to the present invention mounted on the surface of a printed circuit board is exposed to air at −40 ° C. and 125 ° C.
The test sample was placed in a thermostatic chamber controlled at each temperature for 15 minutes / 1.
As a result of repeating the holding for 5 minutes as one cycle and repeating a maximum of 1,000 cycles, no change in electrical resistance was observed between the wiring board and the printed board even after 1000 cycles, and an extremely stable and excellent electrical connection state Could be maintained. Incidentally, a similar test was performed on a commercially available glass-ceramic wiring board having a thermal expansion coefficient of 6 ppm / ° C., and as a result, a change was observed in which the electric resistance increased in about 200 cycles.

【００５４】[0054]

【発明の効果】以上詳述したように、本発明のガラスセ
ラミック焼結体は、４０〜４００℃において８〜１８ｐ
ｐｍ／℃の範囲で任意の熱膨張係数に制御できるととも
に、かかる焼結体を配線基板の絶縁基板として使用する
ことにより、プリント基板等の外部電気回路基板に対し
て実装した場合においても配線基板が大型形状であって
も何ら接続不良等を引き起こすことがなく信頼性の高い
配線基板を提供できる。また、Ｃｕなどの配線層と同時
に焼成することができるために、配線層の多層化も実現
することもできるため、配線基板の低コスト化を図るこ
ともできる。As described in detail above, the glass-ceramic sintered body of the present invention can be used at 8 to 18 p
In addition to being able to control the coefficient of thermal expansion to an arbitrary value within the range of pm / ° C. and using such a sintered body as an insulating substrate of a wiring board, the wiring board can be mounted on an external electric circuit board such as a printed board. Can provide a highly reliable wiring board which does not cause any connection failure even if it has a large shape. In addition, since it can be fired at the same time as the wiring layer of Cu or the like, a multilayer wiring layer can be realized, so that the cost of the wiring board can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明におけるボールグリッドアレイ（ＢＧ
Ａ）型半導体素子収納用パッケージの実装構造を説明す
るための断面図である。FIG. 1 shows a ball grid array (BG) according to the present invention.
FIG. 2 is a cross-sectional view for explaining a mounting structure of an A) type semiconductor element storage package.

【図２】図１の要部拡大断面図である。FIG. 2 is an enlarged sectional view of a main part of FIG.

【図３】接続端子の他の実施例における要部拡大断面図
である。FIG. 3 is an enlarged sectional view of a main part of another embodiment of the connection terminal.

【図４】本発明におけるリードレスチップキャリア（Ｌ
ＣＣ）型半導体素子収納用パッケージの実装構造を説明
するための断面図である。FIG. 4 shows a leadless chip carrier (L) according to the present invention.
It is sectional drawing for demonstrating the mounting structure of CC) type semiconductor element accommodation package.

【符号の説明】[Explanation of symbols]

１・・・・絶縁基板 １ａ，１ｂ・・凹部 ２・・・蓋体 ３・・・メタライズ配線層 ３ａ・・接続パッド ４・・・接続端子 ４ａ・・突出部 ５・・・半導体素子 ６・・・容器 ８・・・配線導体 ９・・・絶縁体 Ａ・・・ＢＧＡ型パッケージ Ｂ・・・外部電気回路基板 Ｃ・・・ＬＣＣ型パッケージ DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 1a, 1b ... Depression 2 ... Lid 3 ... Metallized wiring layer 3a ... Connection pad 4 ... Connection terminal 4a ... Protrusion 5 ... Semiconductor element 6 ...・ ・ Container 8 ・ ・ ・ Wiring conductor 9 ・ ・ ・ Insulator A ・ ・ ・ BGA type package B ・ ・ ・ External electric circuit board C ・ ・ ・ LCC type package

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−100454（ＪＰ，Ａ) 特開 平４−254439（ＪＰ，Ａ) 特開 平４−231334（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) C04B 35/00 - 35/22 C03C 1/00 - 14/00 H01L 23/15 H05K 1/03 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-62-100454 (JP, A) JP-A-4-254439 (JP, A) JP-A-4-231334 (JP, A) (58) Field (Int.Cl. 7 , DB name) C04B 35/00-35/22 C03C 1/00-14/00 H01L 23/15 H05K 1/03

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】結晶相５０〜９９重量％と、ガラス相１〜
５０重量％から構成され、前記結晶相として、フォルス
テライト及びエンスタタイトを合計で２０〜８５重量％
含有するとともに、４０〜４００℃における熱膨張係数
が８〜１８ｐｐｍ／℃であることを特徴とするガラス−
セラミック焼結体。(1) a crystal phase of 50 to 99% by weight and a glass phase of 1 to
50% by weight, and forsterite and enstatite in a total amount of 20 to 85% by weight as the crystal phase.
A glass characterized by containing and having a coefficient of thermal expansion at 40 to 400 ° C. of 8 to 18 ppm / ° C.
Ceramic sintered body. 【請求項２】前記結晶相中に、リチウムシリケートを含
む請求項１記載のガラス−セラミック焼結体。2. The glass-ceramic sintered body according to claim 1, wherein said crystal phase contains lithium silicate. 【請求項３】絶縁基板の表面あるいは内部にメタライズ
配線層が配設された配線基板において、前記絶縁基板
が、結晶相５０〜９９重量％と、ガラス相１〜５０重量
％から構成され、前記結晶相として、フォルステライト
及びエンスタタイトを合計で２０〜８５重量％含有する
とともに、４０〜４００℃における熱膨張係数が８〜１
８ｐｐｍ／℃のガラス−セラミック焼結体からなること
を特徴とする配線基板。3. A wiring board having a metallized wiring layer disposed on the surface or inside of an insulating substrate, wherein the insulating substrate is composed of 50 to 99% by weight of a crystal phase and 1 to 50% by weight of a glass phase. As a crystalline phase, forsterite and enstatite are contained in a total amount of 20 to 85% by weight, and have a thermal expansion coefficient of 8 to 1 at 40 to 400 ° C.
A wiring board comprising a glass-ceramic sintered body at 8 ppm / ° C. 【請求項４】前記結晶相中に、リチウムシリケートを含
む請求項３記載の配線基板。4. The wiring board according to claim 3, wherein said crystal phase contains lithium silicate.
JP30562295A 1995-03-31 1995-11-24 Glass-ceramic sintered body and wiring board using the same Expired - Fee Related JP3346693B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP30562295A JP3346693B2 (en) 1995-11-24 1995-11-24 Glass-ceramic sintered body and wiring board using the same
US08/623,979 US5763059A (en) 1995-03-31 1996-03-29 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30562295A JP3346693B2 (en) 1995-11-24 1995-11-24 Glass-ceramic sintered body and wiring board using the same

Publications (2)

Publication Number Publication Date
JPH09142880A JPH09142880A (en) 1997-06-03
JP3346693B2 true JP3346693B2 (en) 2002-11-18

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CN108585512A (en) * 2018-06-20 2018-09-28 内蒙古科技大学 A kind of tailing MAS series vitro-ceramic insulating materials and preparation method thereof

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US6572955B2 (en) * 2000-04-27 2003-06-03 Kyocera Corporation Ceramics having excellent high-frequency characteristics and method of producing the same
JP5454833B2 (en) * 2007-07-23 2014-03-26 Ｔｄｋ株式会社 Ceramic substrate and manufacturing method thereof
JP5354320B2 (en) * 2007-07-23 2013-11-27 Ｔｄｋ株式会社 Ceramic substrate and manufacturing method thereof
EP2177490B1 (en) * 2007-07-23 2018-03-14 TDK Corporation Ceramic substrate, process for producing the same, and dielectric-porcelain composition
EP3178787B1 (en) * 2014-08-07 2019-10-09 Nissan Chemical Corporation Silane-treated forsterite fine particles and production method therefor, and organic solvent dispersion of silane-treated forsterite fine particles and production method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108585512A (en) * 2018-06-20 2018-09-28 内蒙古科技大学 A kind of tailing MAS series vitro-ceramic insulating materials and preparation method thereof
CN108585512B (en) * 2018-06-20 2021-04-09 内蒙古科技大学 Tailing MAS series glass ceramic insulating material and preparation method thereof

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