JP3346475B2 - Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit - Google Patents

Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit

Info

Publication number
JP3346475B2
JP3346475B2 JP2000009221A JP2000009221A JP3346475B2 JP 3346475 B2 JP3346475 B2 JP 3346475B2 JP 2000009221 A JP2000009221 A JP 2000009221A JP 2000009221 A JP2000009221 A JP 2000009221A JP 3346475 B2 JP3346475 B2 JP 3346475B2
Authority
JP
Japan
Prior art keywords
film
via hole
interlayer film
upper interlayer
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000009221A
Other languages
Japanese (ja)
Other versions
JP2001203207A (en
Inventor
厚 西沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2000009221A priority Critical patent/JP3346475B2/en
Priority to TW089127535A priority patent/TW567530B/en
Priority to US09/751,979 priority patent/US6809037B2/en
Priority to KR10-2001-0001760A priority patent/KR100382089B1/en
Publication of JP2001203207A publication Critical patent/JP2001203207A/en
Application granted granted Critical
Publication of JP3346475B2 publication Critical patent/JP3346475B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、金属配線まで到達
するヴァイアホールと凹溝とを層間膜に同時に形成する
半導体集積回路の製造方法と、この製造方法により製造
された半導体集積回路と、に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a via hole and a groove reaching a metal wiring are simultaneously formed in an interlayer film, and a semiconductor integrated circuit manufactured by the manufacturing method. .

【０００２】[0002]

【従来の技術】現在、半導体集積回路の高性能化や微細
化が要求されており、各種の製造方法や使用材料が研究
されている。従来、半導体集積回路の配線にはポリシリ
コンやアルミニウムが多用されてきたが、半導体集積回
路の高性能化や微細化を実現するためには更に低抵抗の
材料が必要である。2. Description of the Related Art At present, high performance and miniaturization of semiconductor integrated circuits are required, and various manufacturing methods and materials to be used are being studied. Conventionally, polysilicon and aluminum have been frequently used for wiring of a semiconductor integrated circuit. However, in order to realize high performance and miniaturization of the semiconductor integrated circuit, a material having a lower resistance is required.

【０００３】そこで、半導体集積回路の微細な配線を銅
で形成することが創案されたが、銅は物性的にエッチン
グによるパターニングが困難であり、耐食性も良好でな
い。そこで、層間膜の内部と表面とに銅からなる金属配
線を形成し、これらの金属配線を銅からなるコンタクト
で接続した半導体集積回路を製造する製造方法としてデ
ュアルダマシン法が開発された。Therefore, it has been proposed to form fine wiring of a semiconductor integrated circuit with copper. However, copper is physically difficult to pattern by etching and has poor corrosion resistance. Therefore, a dual damascene method has been developed as a method for manufacturing a semiconductor integrated circuit in which metal wirings made of copper are formed inside and on the surface of an interlayer film and these metal wirings are connected by contacts made of copper.

【０００４】このデュアルダマシン法の製造方法の一従
来例を図２ないし図５を参照して以下に説明する。な
お、図２ないし図５は半導体集積回路の製造工程を順番
に示す縦断正面図である。A conventional example of the manufacturing method of the dual damascene method will be described below with reference to FIGS. 2 to 5 are longitudinal sectional front views sequentially showing the steps of manufacturing the semiconductor integrated circuit.

【０００５】まず、ここで製造する半導体集積回路１０
０では、図５(ｃ)に示すように、ＳiＯ2からなる下部層
間膜１０１と上部層間膜１０２とが積層されており、下
部層間膜１０１の上部に銅からなる下部金属配線１０３
が埋め込まれている。上部層間膜１０２の上部にも銅か
らなる上部金属配線１０４が埋め込まれており、この上
部金属配線１０４と一体に形成された接続配線１０５が
下部金属配線１０３に接続されている。First, the semiconductor integrated circuit 10 manufactured here is
In FIG. 5C, as shown in FIG. 5C, a lower interlayer film 101 made of SiO 2 and an upper interlayer film 102 are laminated, and a lower metal wiring 103 made of copper is formed on the lower interlayer film 101.
Is embedded. An upper metal wiring 104 made of copper is also buried above the upper interlayer film 102, and a connection wiring 105 formed integrally with the upper metal wiring 104 is connected to the lower metal wiring 103.

【０００６】なお、下部／上部金属配線１０３，１０４
は、例えば、図面を貫通する前後方向に連通するパター
ンに形成されているが、接続配線１０５は、例えば、前
後幅が左右幅と同一の形状に形成されており、この前後
方向に連通しない接続配線１０５により前後方向に連通
する下部／上部金属配線１０３，１０４が一点で接続さ
れている。The lower / upper metal wirings 103, 104
Is formed, for example, in a pattern communicating in the front-rear direction penetrating the drawing, but the connection wiring 105 is formed, for example, in the same shape as the left-right width in the front-rear width, and is not connected in the front-rear direction. The lower / upper metal wirings 103 and 104 communicating in the front-rear direction by the wiring 105 are connected at one point.

【０００７】上述のような構造の半導体集積回路１００
を製造する一般的な製造方法としては、図２(ａ)に示す
ように、シリコン基板１１０の表面にＳiＯ2からなる所
定膜厚の下部層間膜１０１を形成し、その表面にフォト
レジストを塗布してからパターニングしてレジストマス
ク(図示せず)を形成する。このレジストマスクの開口孔
から下部層間膜１０１をドライエッチングすることによ
り、同図(ｂ)に示すように、この下部層間膜１０１の表
面に所定深度まで凹部１１１を形成する。[0007] The semiconductor integrated circuit 100 having the structure described above.
2A, a lower interlayer film 101 of a predetermined thickness made of SiO 2 is formed on the surface of a silicon substrate 110, and a photoresist is applied to the surface thereof, as shown in FIG. Then, patterning is performed to form a resist mask (not shown). By dry-etching the lower interlayer film 101 from the opening of the resist mask, a recess 111 is formed to a predetermined depth on the surface of the lower interlayer film 101 as shown in FIG.

【０００８】この凹部１１１が完成したら、Ｏ2雰囲気
中でのプラズマ処理と有機剥離によりレジストマスクを
除去し、同図(ｃ)に示すように、これで露出した下部層
間膜１０１の表面に、タンタル膜１１２と銅膜１１３と
をスパッタリングで順番に成膜する。When the recess 111 is completed, the resist mask is removed by plasma treatment in an O 2 atmosphere and organic peeling, and the exposed surface of the lower interlayer film 101 is removed as shown in FIG. A tantalum film 112 and a copper film 113 are sequentially formed by sputtering.

【０００９】つぎに、同図(ｄ)に示すように、この銅膜
１１３の表面に銅からなるメッキ膜１１４を形成して凹
部１１１を充填してから、同図(ｅ)に示すように、この
メッキ膜１１４をＣＭＰ(Chemical Mechanical Polishi
ng)により下部層間膜１０１の表面まで平坦に研磨す
る。Next, as shown in FIG. 1D, a plating film 114 made of copper is formed on the surface of the copper film 113 to fill the recess 111, and then, as shown in FIG. The plating film 114 is formed by CMP (Chemical Mechanical Polishing).
(ng), the surface of the lower interlayer film 101 is polished flatly.

【００１０】つぎに、図３(ａ)に示すように、この平坦
に研磨された表面にプラズマＣＶＤ(Chemical Vapor De
position)法によりＳiＮからなるストッパ膜１１５を値
例えば、膜厚500(Å)まで成長させてから、やはりプラ
ズマＣＶＤ法によりＳiＯ2からなる上部層間膜１０２
を、例えば、膜厚12000(Å)まで成長させる。Next, as shown in FIG. 3 (a), the flat polished surface is subjected to plasma CVD (Chemical Vapor Deposition).
After the stopper film 115 made of SiN is grown to a thickness of, for example, 500 (500) by the (position) method, the upper interlayer film 102 made of SiO 2 is also formed by the plasma CVD method.
Is grown to a film thickness of 12000 (1), for example.

【００１１】つぎに、下部金属配線１０３の上方が開口
したレジストマスク１１６を上部層間膜１０２の表面に
形成し、このレジストマスク１１６の開口部から上部層
間膜１０２をエッチングすることにより、同図(ｂ)に示
すように、上部層間膜１０２の表面からストッパ膜１１
５の表面で下部金属配線１０３に対向する位置までヴァ
イアホール１１７を形成する。Next, a resist mask 116 having an opening above the lower metal wiring 103 is formed on the surface of the upper interlayer film 102, and the upper interlayer film 102 is etched from the opening of the resist mask 116, thereby forming a resist mask 116 as shown in FIG. As shown in b), the stopper film 11 is removed from the surface of the upper interlayer film 102.
Via holes 117 are formed to a position facing the lower metal wiring 103 on the surface of No. 5.

【００１２】このヴァイアホール１１７が形成できたら
レジストマスク１１６を除去し、同図(ｃ)に示すよう
に、有機膜としてＡＲＣ(Anti Reflective Coating)膜
１１８を上部層間膜１０２の表面に膜厚2000(Å)まで成
膜するとともにヴァイアホール１１７の内部に充填す
る。When the via hole 117 is formed, the resist mask 116 is removed, and an ARC (Anti Reflective Coating) film 118 is formed as an organic film on the surface of the upper interlayer film 102 as shown in FIG. The film is formed up to (Å) and the inside of the via hole 117 is filled.

【００１３】このＡＲＣ膜１１８の表面にヴァイアホー
ル１１７より幅広に開口したレジストマスク１１９を、
例えば、膜厚8000(Å)に形成し、同図(ｄ)に示すよう
に、“Ｃ4Ｆ8”と“Ｏ2”とを混合したエッチングガス
と“Ａr”の不活性ガスとの“30(mToll)”程度の圧力の
雰囲気中で、レジストマスク１１９の開口からＡＲＣ膜
１１８をプラズマエッチングする。なお、“Ｃ4Ｆ8”と
“Ｏ2”と“Ａr”との混合比は、例えば、“20／10／20
0”などとされる。On the surface of the ARC film 118, a resist mask 119 having an opening wider than the via hole 117 is formed.
For example, the film is formed to a film thickness of 8000 (Å), and as shown in FIG. 4D, an etching gas obtained by mixing “C 4 F 8 ” and “O 2 ” and an inert gas of “Ar” are used. The ARC film 118 is plasma-etched from the opening of the resist mask 119 in an atmosphere having a pressure of about 30 (mToll) ". The mixing ratio of “C 4 F 8 ”, “O 2 ”, and “Ar” is, for example, “20/10/20
0 "and so on.

【００１４】このＡＲＣ膜１１８のプラズマエッチング
が完了したらエッチングガスを“Ｃ 4Ｆ8”に変更し、図
４(ａ)に示すように、レジストマスク１１９の開口から
上部層間膜１０２とＡＲＣ膜１１８とを同時にプラズマ
エッチングし、ストッパ膜１１５まで到達しない深度40
00(Å)の幅広の凹溝１２０を形成する。Plasma etching of the ARC film 118
Is completed, change the etching gas to "C FourF8Change to “
As shown in FIG. 4A, through the opening of the resist mask 119,
Simultaneously plasma the upper interlayer film 102 and the ARC film 118
Etching, depth 40 not reaching stopper film 115
A wide concave groove 120 of (00) is formed.

【００１５】このとき、“Ｃ4Ｆ8”のエッチングガスに
よる上部層間膜１０２とＡＲＣ膜１１８とのプラズマエ
ッチングのエッチングレートは約“4000(Å)／min”な
ので、エッチング時間を一分に規制することにより凹溝
１２０の深度を4000(Å)に調節する。At this time, since the etching rate of the plasma etching of the upper interlayer film 102 and the ARC film 118 by the etching gas of “C 4 F 8 ” is about “4000 (Å) / min”, the etching time is restricted to one minute. By doing so, the depth of the groove 120 is adjusted to 4000 (Å).

【００１６】つぎに、“Ｏ2”でのプラズマ処理とアミ
ン系の有機剥離液による剥離処理により、同図(ｂ)に示
すように、レジストマスク１１９とＡＲＣ膜１１８とを
除去することにより、ヴァイアホール１１７の底部にス
トッパ膜１１５を露出させる。なお、銅からなる下部金
属配線１０３は耐食性が低いが、上述のようにレジスト
マスク１１９とＡＲＣ膜１１８とを除去する時点ではス
トッパ膜１１５で雰囲気から遮断されているので腐食す
ることはない。Next, as shown in FIG. 1B, the resist mask 119 and the ARC film 118 are removed by a plasma treatment with "O 2 " and a peeling treatment with an amine-based organic peeling liquid. The stopper film 115 is exposed at the bottom of the via hole 117. Although the lower metal wiring 103 made of copper has low corrosion resistance, it is not corroded at the time of removing the resist mask 119 and the ARC film 118 because it is cut off from the atmosphere by the stopper film 115 as described above.

【００１７】同図(ｃ)に示すように、“ＣＨＦ3”と
“Ｏ2”とを混合したエッチングガスと“Ａr”の不活性
ガスとの雰囲気中で上部層間膜１０２をマスクとしてヴ
ァイアホール１１７の底部に位置するストッパ膜１１５
をプラズマエッチングし、ヴァイアホール１１７の底部
に下部金属配線１０３を露出させる。なお、“ＣＨ
Ｆ3”と“Ｏ2”と“Ａr”との混合比も、例えば、“20
／10／200”などとされる。As shown in FIG. 1C, a via hole is formed by using the upper interlayer film 102 as a mask in an atmosphere of an etching gas in which "CHF 3 " and "O 2 " are mixed and an inert gas of "Ar". Stopper film 115 located at the bottom of 117
Is subjected to plasma etching to expose the lower metal wiring 103 at the bottom of the via hole 117. Note that "CH
The mixing ratio of “F 3 ”, “O 2 ”, and “Ar” is also, for example, “20
/ 10/200 ".

【００１８】この状態で上部層間膜１０２と下部金属配
線１０３との露出している表面をアミン系の有機剥離液
により清浄化してから、図５(ａ)に示すように、この清
浄化された表面に窒化タンタル膜１２１と銅膜１２２と
をスパッタリングにより順番に成膜する。In this state, the exposed surfaces of the upper interlayer film 102 and the lower metal wiring 103 are cleaned with an amine-based organic stripping solution, and then, as shown in FIG. A tantalum nitride film 121 and a copper film 122 are sequentially formed on the surface by sputtering.

【００１９】これで上部層間膜１０２の表面から凹溝１
２０とヴァイアホール１１７との内面まで窒化タンタル
膜１２１と銅膜１２２とが成膜されるので、同図(ｂ)に
示すように、この銅膜１２２の表面に銅からなるメッキ
膜１２３を形成して凹溝１２０とヴァイアホール１１７
とを充填する。Thus, the groove 1 is removed from the surface of the upper interlayer film 102.
Since the tantalum nitride film 121 and the copper film 122 are formed up to the inner surface of the via hole 117 and the inner surface of the via hole 117, a plating film 123 made of copper is formed on the surface of the copper film 122 as shown in FIG. Groove 120 and via hole 117
And filling.

【００２０】そして、このメッキ膜１２３をＣＭＰによ
り上部層間膜１０２の表面まで平坦に研磨することによ
り、同図(ｃ)に示すように、凹溝１２０の内部に位置す
る上部金属配線１０４とヴァイアホール１１７の内部に
位置する接続配線１０５とが形成されるので、これで半
導体集積回路１００が完成することになる。Then, the plating film 123 is polished flat to the surface of the upper interlayer film 102 by CMP, so that the upper metal wiring 104 located inside the concave groove 120 and the via are polished as shown in FIG. Since the connection wiring 105 located inside the hole 117 is formed, the semiconductor integrated circuit 100 is completed with this.

【００２１】なお、上述のように幅狭のヴァイアホール
１１７と幅広の凹溝１２０とを同時に形成する手法は、
一般的にデュアルダマシン法と呼称されている。また、
上述の層間膜１０１，１０２としては、ＳiＯ2の他に低
誘電率膜も利用することができ、この低誘電率膜として
は、水素含有シリコン酸化膜や有機含有シリコン酸化膜
などを利用することができる。As described above, the method of simultaneously forming the narrow via hole 117 and the wide concave groove 120 is as follows.
It is generally called the dual damascene method. Also,
As the above-mentioned interlayer films 101 and 102, a low dielectric constant film can be used in addition to SiO 2. As the low dielectric constant film, a hydrogen-containing silicon oxide film, an organic-containing silicon oxide film, or the like is used. Can be.

【００２２】また、ＡＲＣ膜１１８としては、ポリイミ
ドやノボラックからなるベース樹脂にポリビニルフェノ
ールやポリメチルメタクリレートを添加したものなどを
利用することができ、レジストとしては、ノボラック樹
脂やポリイミド樹脂などを利用することができる。Further, as the ARC layer 118, can be utilized such as those added to the base resin to polyvinyl phenol or polymethyl methacrylate made of polyimide and novolac, as the resist, novolac resin, polyimide resins, etc. The Can be used.

【００２３】[0023]

【発明が解決しようとする課題】上述のような方法で半
導体集積回路１００を製造することにより、幅狭のヴァ
イアホール１１７上に幅広の凹溝１２０を形成できるの
で、下部層間膜１０１に埋め込まれた銅からなる下部金
属配線１０３と上部層間膜１０２に埋め込まれた銅から
なる上部金属配線１０４とがヴァイアホール１１７内の
接続配線１０５で接続された構造を形成することができ
る。By manufacturing the semiconductor integrated circuit 100 by the above-described method, a wide concave groove 120 can be formed on the narrow via hole 117. A structure in which the lower metal wiring 103 made of copper and the upper metal wiring 104 made of copper embedded in the upper interlayer film 102 are connected by the connection wiring 105 in the via hole 117 can be formed.

【００２４】しかし、図４(ａ)に示すように、“Ｃ
4Ｆ8”のエッチングガスで上部層間膜１０２とＡＲＣ膜
１１８とを同時にプラズマエッチングするとき、実際に
はＡＲＣ膜１１８のエッチングレートが上部層間膜１０
２より低いため、プラズマエッチングは上部層間膜１０
２からＡＲＣ膜１１８が突出した状態で進行することに
なる。However, as shown in FIG.
When the upper interlayer film 102 and the ARC film 118 are simultaneously plasma-etched with 4F 8 ″ etching gas, the etching rate of the ARC film 118 is actually lower than the upper interlayer film 10.
2, the plasma etching is performed on the upper interlayer film 10.
2 and the ARC film 118 protrudes.

【００２５】また、“Ｃ4Ｆ8”のエッチングガスは、プ
ラズマ中で分解されたものや反応生成物からフロロカー
ボン系のデポジションを発生しやすいので、上部層間膜
１０２からＡＲＣ膜１１８が突出した状態でプラズマエ
ッチングが進行すると、図６に示すように、上部層間膜
１０２から突出したＡＲＣ膜１１８の側面にデポジショ
ン１２４が堆積しやすい。The ARC film 118 protrudes from the upper interlayer film 102 because the etching gas of “C 4 F 8 ” is liable to generate fluorocarbon-based deposition from plasma decomposition and reaction products. When plasma etching proceeds in this state, as shown in FIG. 6, deposition 124 is likely to be deposited on the side surface of ARC film 118 protruding from upper interlayer film 102.

【００２６】このようにデポジション１２４が堆積する
と、これがマスクとなって下方のプラズマエッチングが
阻害される。このため、上部層間膜１０２とＡＲＣ膜１
１８との同時エッチングが完了してから、ヴァイアホー
ル１１７の内部のＡＲＣ膜１１８を除去すると、図７に
示すように、ヴァイアホール１１７の開口の周囲にデポ
ジション１２４が残存した不良が発生する。When the deposition 124 is deposited as described above, the deposition 124 serves as a mask, thereby inhibiting the lower plasma etching. Therefore, the upper interlayer film 102 and the ARC film 1
If the ARC film 118 inside the via hole 117 is removed after the completion of the simultaneous etching with the hole 18, a defect occurs in which the deposition 124 remains around the opening of the via hole 117 as shown in FIG.

【００２７】このようにヴァイアホール１１７の開口の
周囲にデポジション１２４が残存すると、上部金属配線
１０４を良好な形状に形成できないので断線などの不良
の原因となる。If the deposition 124 remains around the opening of the via hole 117 in this manner, the upper metal wiring 104 cannot be formed in a good shape, which causes a failure such as disconnection.

【００２８】本発明は上述のような課題に鑑みてなされ
たものであり、ヴァイアホール上に凹溝を形成するため
にデュアルダマシン法により上部層間膜と有機膜とを同
時にプラズマエッチングしても、ヴァイアホールの開口
の周囲にデポジションが残存しない半導体集積回路の製
造方法を提供することを目的とする。The present invention has been made in view of the above-mentioned problems. Even if the upper interlayer film and the organic film are simultaneously plasma-etched by the dual damascene method to form a concave groove on the via hole, An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit in which no deposition remains around an opening of a via hole.

【００２９】[0029]

【課題を解決するための手段】本発明の半導体集積回路
の製造方法は、下部金属配線が埋め込まれた下部層間膜
上に上部層間膜を堆積する工程と、その後前記上部層間
膜の前記下部金属配線の位置に対向する位置にヴァイア
ホールを形成する工程と、その後前記ヴァイアホールを
充填するように全面に有機膜を成膜する工程と、その後
前記ヴァイアホールの位置に対応して前記ヴィアホール
より幅広に開口したレジストマスクを形成する工程と、
その後前記上部層間膜の表面が露出するまで前記有機膜
をエッチングする第１のエッチング工程と、その後前記
有機膜の方が前記上部層間膜よりエッチングレートが高
い雰囲気中で前記有機膜と前記上部層間膜とを途中まで
エッチングする第２のエッチング工程と、その後前記ヴ
ィアホールに残存している前記有機膜を除去する第３の
エッチング工程と、その後全面に金属膜を成膜する工程
と、を備えている。 Method of manufacturing a semi-conductor integrated circuit SUMMARY OF THE INVENTION The present invention includes a lower interlayer film lower metal wires are embedded
Depositing an upper interlayer film thereon, and thereafter,
A via is provided at a position opposite to the position of the lower metal wiring of the film.
Forming a hole, and then forming the via hole
A step of forming an organic film over the entire surface so as to fill, and thereafter
The via hole corresponds to the position of the via hole
Forming a resist mask with a wider opening;
Thereafter, the organic film is exposed until the surface of the upper interlayer film is exposed.
A first etching step of etching
The etching rate of the organic film is higher than that of the upper interlayer film.
Between the organic film and the upper interlayer film
A second etching step for etching, and
A third step of removing the organic film remaining in the via hole.
Etching process and then metal film deposition over the entire surface
And

【００３０】[0030]

【００３１】[0031]

【００３２】[0032]

【００３３】[0033]

【００３４】[0034]

【発明の実施の形態】本発明の実施の一形態を図１を参
照して以下に説明する。ただし、本実施の形態に関して
前述した一従来例と同一の部分は、同一の名称および符
号を使用して詳細な説明は省略する。なお、同図は本実
施の形態の半導体集積回路の製造方法の要部の工程を示
す縦断正面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. However, the same portions as those of the conventional example described above with respect to the present embodiment are denoted by the same names and reference numerals, and detailed description thereof is omitted. FIG. 4 is a vertical sectional front view showing main steps of a method of manufacturing a semiconductor integrated circuit according to the present embodiment.

【００３５】本実施の形態の半導体集積回路１００も、
完成した構造は一従来例の場合と同一である。この半導
体集積回路１００を製造する本実施の形態の方法でも、
一従来例の製造方法と同様に、下部金属配線１０３が埋
め込まれた下部層間膜１０１の表面にストッパ膜１１５
を介して上部層間膜１０２を積層し、この上部層間膜１
０２の表面からストッパ膜１１５の表面で下部金属配線
１０３に対向する位置までヴァイアホール１１７を形成
する。The semiconductor integrated circuit 100 of the present embodiment also
The completed structure is the same as that of the conventional example. In the method of the present embodiment for manufacturing the semiconductor integrated circuit 100,
As in the conventional manufacturing method, the stopper film 115 is formed on the surface of the lower interlayer film 101 in which the lower metal wiring 103 is embedded.
The upper interlayer film 102 is laminated through the
A via hole 117 is formed from the surface of the substrate 02 to a position facing the lower metal wiring 103 on the surface of the stopper film 115.

【００３６】このヴァイアホール１１７と上部層間膜１
０２の表面とにＡＲＣ膜１１８を埋め込み、このＡＲＣ
膜１１８の表面にヴァイアホール１１７より幅広に開口
したレジストマスク１１９を形成し、同図(ａ)に示すよ
うに、このレジストマスク１１９の開口からＡＲＣ膜１
１８をプラズマエッチングする。The via hole 117 and the upper interlayer film 1
The ARC film 118 is embedded in the surface of the ARC
A resist mask 119 having an opening wider than the via hole 117 is formed on the surface of the film 118, and the ARC film 1 is opened from the opening of the resist mask 119 as shown in FIG.
18 is plasma-etched.

【００３７】このＡＲＣ膜１１８のプラズマエッチング
が完了したらエッチングガスを変更し、同図(ｂ)に示す
ように、レジストマスク１１９の開口からストッパ膜１
１５まで到達しない所定深度まで上部層間膜１０２とＡ
ＲＣ膜１１８とを同時にプラズマエッチングして幅広の
凹溝１２０を形成する。When the plasma etching of the ARC film 118 is completed, the etching gas is changed and the stopper film 1 is opened through the opening of the resist mask 119 as shown in FIG.
And the upper interlayer film 102 and A
The RC film 118 is simultaneously plasma-etched to form a wide groove 120.

【００３８】このプラズマエッチングされた幅広の凹溝
１２０の底部に位置する幅狭のヴァイアホール１１７に
残存しているＡＲＣ膜１１８を除去し、同図(ｃ)に示す
ように、このＡＲＣ膜１１８を除去したヴァイアホール
１１７の底部に位置するストッパ膜１１５をエッチング
して下部金属配線１０３を露出させる。The ARC film 118 remaining in the narrow via hole 117 located at the bottom of the plasma-etched wide concave groove 120 is removed, and as shown in FIG. The stopper film 115 located at the bottom of the via hole 117 from which the metal wiring 103 has been removed is etched to expose the lower metal wiring 103.

【００３９】ただし、本実施の形態の製造方法では、一
従来例の製造方法とは相違して、上述のようにデュアル
ダマシン法により上部層間膜１０２とＡＲＣ膜１１８と
を同時にプラズマエッチングするとき、エッチングガス
として“ＣＦ4”を使用する。However, in the manufacturing method according to the present embodiment, unlike the conventional manufacturing method, when the upper interlayer film 102 and the ARC film 118 are simultaneously plasma-etched by the dual damascene method as described above, “CF 4 ” is used as an etching gas.

【００４０】より詳細には、同図(ａ)に示すように、
“ＣＦ4”と“Ｏ2”とを混合したエッチングガスと“Ａ
r”の不活性ガスとの圧力“300〜400(mToll)”の雰囲気
中で、レジストマスク１１９の開口からＡＲＣ膜１１８
をプラズマエッチングし、このプラズマエッチングが完
了したらエッチングガスを“ＣＦ4”に変更し、同図
(ｂ)に示すように、レジストマスク１１９の開口から上
部層間膜１０２とＡＲＣ膜１１８とを同時にプラズマエ
ッチングする。More specifically, as shown in FIG.
An etching gas containing a mixture of “CF 4 ” and “O 2 ” and “A
r ”through an opening of the resist mask 119 in an atmosphere of an inert gas at a pressure of“ 300 to 400 (mToll) ”.
Is plasma-etched, and when the plasma-etching is completed, the etching gas is changed to “CF 4 ”.
As shown in (b), the upper interlayer film 102 and the ARC film 118 are simultaneously plasma-etched from the opening of the resist mask 119.

【００４１】なお、ＡＲＣ膜１１８をプラズマエッチン
グするときの“ＣＦ4”と“Ｏ2”と“Ａr”との混合比
は、例えば、“100／10／500”などとされ、上部層間膜
１０２とＡＲＣ膜１１８とを同時にプラズマエッチング
するときの“ＣＦ4”と“Ａr”との混合比は、例えば、
“100／500”などとされる。When the ARC film 118 is subjected to plasma etching, the mixing ratio of “CF 4 ”, “O 2 ”, and “Ar” is set to, for example, “100/10/500”. The mixing ratio of “CF 4 ” and “Ar” when plasma etching is simultaneously performed on the ARC film 118 and the ARC film 118 is, for example, as follows:
"100/500" etc.

【００４２】本実施の形態の製造方法では、上述のよう
にデュアルダマシン法によりレジストマスク１１９の開
口からＡＲＣ膜１１８と上部層間膜１０２とを同時にプ
ラズマエッチングするとき、従来とは相違してエッチン
グガスとして“ＣＦ4”を使用する。In the manufacturing method of the present embodiment, when the ARC film 118 and the upper interlayer film 102 are simultaneously plasma-etched from the opening of the resist mask 119 by the dual damascene method as described above, the etching gas differs from the conventional one. Is used as “CF 4 ”.

【００４３】この“ＣＦ4”のエッチングガスによるプ
ラズマエッチングでは、物性的にＡＲＣ膜１１８のエッ
チングレートが上部層間膜１０２のエッチングレートよ
り高いので、同図(ｂ)に示すように、上部層間膜１０２
からＡＲＣ膜１１８が突出した状態でプラズマエッチン
グが進行することがなく、物性的にデポジションが堆積
しやすいＡＲＣ膜１１８の側面が形成されない。In the plasma etching using the etching gas of “CF 4 ”, since the etching rate of the ARC film 118 is physically higher than the etching rate of the upper interlayer film 102, as shown in FIG. 102
The plasma etching does not proceed in a state where the ARC film 118 protrudes from the ARC film 118, and the side surface of the ARC film 118 on which deposition is likely to be physically deposited is not formed.

【００４４】しかも、“ＣＦ4”からなるエッチングガ
スは、分子構造の弗素の原子数が炭素の原子数の三倍以
上であり、炭素が少数で弗素が多数なので、物性的にフ
ロロカーボン系のデポジションを発生しにくい。さら
に、本実施の形態の製造方法では、エッチングガスの圧
力を“300〜400(mToll)”もの高圧とするので分子のブ
ラウン運動が活発となってプラズマエッチングの方向性
が等方的となり、上方に順次堆積されるデポジションが
各種方向から逐次除去されることになる。Further, the etching gas composed of “CF 4 ” has fluorine in the molecular structure of three times or more the number of carbon atoms, and has a small amount of carbon and a large amount of fluorine. Less likely to generate positions. Further, in the manufacturing method of the present embodiment, since the pressure of the etching gas is set to a high pressure of “300 to 400 (mToll)”, the Brownian motion of the molecule becomes active and the direction of the plasma etching becomes isotropic, and deposition sequentially deposited is to be sequentially removed from a variety of directions.

【００４５】このため、本実施の形態の製造方法では、
デュアルダマシン法によりレジストマスク１１９の開口
からＡＲＣ膜１１８と上部層間膜１０２とを同時にプラ
ズマエッチングするとき、同図(ｃ)に示すように、ヴァ
イアホール１１７の開口の周囲にフロロカーボン系のデ
ポジションが堆積する不良が発生しない。Therefore, in the manufacturing method of the present embodiment,
When the ARC film 118 and the upper interlayer film 102 are simultaneously plasma-etched from the opening of the resist mask 119 by the dual damascene method, a fluorocarbon-based deposition is formed around the opening of the via hole 117 as shown in FIG. No deposit failure occurs.

【００４６】なお、本発明は上記形態に限定されるもの
ではなく、その要旨を逸脱しない範囲で各種の変形を許
容する。例えば、上記形態ではエッチングガスが“ＣＦ
4”からなることを例示したが、このエッチングガスが
“Ｃ2Ｆ6”からなることも可能である。また、エッチン
グガスの圧力が“300〜400(mToll)”であることを例示
したが、これは“100(mToll)”以上であれば良い。The present invention is not limited to the above-described embodiment, but allows various modifications without departing from the scope of the invention. For example, in the above embodiment, the etching gas is “CF
"It has been exemplified that consists, the etching gas is" 4 C 2 F 6 "can be made of. The pressure of the etching gas" has been exemplified that the 300~400 (mToll) " It is sufficient that this is "100 (mToll)" or more.

【００４７】また、上記形態では幅広の凹溝１２０の底
部に幅狭のヴァイアホール１１７が位置する構造で、こ
のヴァイアホール１１７の開口の周囲に発生するデポジ
ションを防止することを例示したが、前述のように凹溝
１２０は前後方向に連通する形状であり、ヴァイアホー
ル１１７は前後方向には連通しない形状である。In the above embodiment, the structure in which the narrow via hole 117 is located at the bottom of the wide concave groove 120 is described as an example of preventing the deposition occurring around the opening of the via hole 117. As described above, the concave groove 120 has a shape communicating with the front-rear direction, and the via hole 117 has a shape not communicating with the front-rear direction.

【００４８】このため、凹溝１２０とヴァイアホール１
１７とが同幅の場合や凹溝１２０よりヴァイアホール１
１７が幅広の場合でも、ヴァイアホール１１７の開口の
前後にはデポジションが発生する段差が存在するので、
本発明を適用することが可能である。For this reason, the concave groove 120 and the via hole 1
17 is the same width or via hole 1
Even when 17 is wide, there is a step where deposition occurs before and after the opening of the via hole 117.
The present invention can be applied.

【００４９】[0049]

【発明の効果】本発明の一の半導体集積回路の製造方法
では、レジストマスクの開口から有機膜と上部層間膜と
を同時にプラズマエッチングするとき、エッチングガス
による有機膜のエッチングレートが上部層間膜のエッチ
ングレートより高いことにより、上部層間膜から有機膜
が突出した状態でプラズマエッチングが進行することが
ないので、デポジションが発生して有機膜の側面に堆積
することがなく、ヴァイアホールの開口の周囲にデポジ
ションが残存する不良の発生を防止することができる。According to the method of manufacturing a semiconductor integrated circuit of the present invention, when the organic film and the upper interlayer film are simultaneously plasma-etched from the opening of the resist mask, the etching rate of the organic film by the etching gas is reduced. by higher than the etching rate, since no plasma etching in a state where the organic film from the upper interlayer film is projected proceeds, without deposition is deposited <br/> the side surface of the organic film occurs, vias It is possible to prevent occurrence of a defect in which deposition remains around the opening of the hole.

【００５０】[0050]

【００５１】[0051]

【００５２】[0052]

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の一形態の半導体集積回路の製造
方法の要部の工程を示す縦断正面図である。FIG. 1 is a vertical sectional front view showing main steps of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

【図２】一従来例の製造方法の第一から第五の工程を示
す縦断正面図である。FIG. 2 is a longitudinal sectional front view showing first to fifth steps of a manufacturing method of a conventional example.

【図３】第六から第九の工程を示す縦断正面図である。FIG. 3 is a vertical sectional front view showing sixth to ninth steps.

【図４】第十から第十一の工程を示す縦断正面図であ
る。FIG. 4 is a longitudinal sectional front view showing tenth to eleventh steps.

【図５】第十二から第十四の工程を示す縦断正面図であ
る。FIG. 5 is a longitudinal sectional front view showing twelfth to fourteenth steps.

【図６】デポジションが発生した状態を示す縦断正面図
である。FIG. 6 is a vertical sectional front view showing a state in which deposition has occurred.

【図７】デポジションが残存した状態を示す縦断正面図
である。FIG. 7 is a longitudinal sectional front view showing a state in which deposition remains.

【符号の説明】[Explanation of symbols]

１００ 半導体集積回路 １１１ 凹部 １０３ 下部金属配線 １０１ 下部層間膜 １１５ ストッパ膜 １０２ 上部層間膜 １１７ ヴァイアホール １１８ 有機膜であるＡＲＣ膜 １１９ レジストマスク １２０ 凹溝 REFERENCE SIGNS LIST 100 semiconductor integrated circuit 111 concave portion 103 lower metal wiring 101 lower interlayer film 115 stopper film 102 upper interlayer film 117 via hole 118 ARC film as organic film 119 resist mask 120 concave groove

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. 7 , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 下部金属配線が埋め込まれた下部層間膜
上に上部層間膜を堆積する工程と、 その後前記上部層間膜の前記下部金属配線の位置に対向
する位置にヴァイアホールを形成する工程と、 その後前記ヴァイアホールを充填するように全面に有機
膜を成膜する工程と、 その後前記ヴァイアホールの位置に対応して前記ヴィア
ホールにり幅広に開口したレジストマスクを形成する工
程と、 その後前記上部層間膜の表面が露出するまで前記有機膜
をエッチングする第１のエッチング工程と、 その後前記有機膜の方が前記上部層間膜よりエッチング
レートが高い雰囲気中で前記有機膜と前記上部層間膜と
を途中までエッチングする第２のエッチング工程と、 その後前記ヴィアホールに残存している前記有機膜を除
去する第３のエッチング工程と、 その後全面に金属膜を成膜する工程と、 を備えており、 前記有機膜はＡＲＣ膜であり、 前記上部層間膜はシリコン酸化膜であり、 前記第１のエッチング工程は“ＣＦ 4 ”と“Ｏ 2 ”と不活
性ガスとの混合雰囲気で行い、 前記第２のエッチング工程は“ＣＦ 4 ”と不活性ガスと
の混合雰囲気で行う ことを特徴とする半導体集積回路の
製造方法。A step of depositing an upper interlayer film on the lower interlayer film in which the lower metal wiring is embedded; and a step of forming a via hole at a position of the upper interlayer film opposite to the position of the lower metal wiring. A step of forming an organic film over the entire surface so as to fill the via hole, and a step of forming a resist mask having a wide opening in the via hole corresponding to the position of the via hole. A first etching step of etching the organic film until the surface of the upper interlayer film is exposed, and thereafter, the organic film and the upper interlayer film in an atmosphere in which the organic film has a higher etching rate than the upper interlayer film. A second etching step of partially etching the substrate, and a third etching step of subsequently removing the organic film remaining in the via hole And a step of subsequently forming a metal film on the entire surface , wherein the organic film is an ARC film, the upper interlayer film is a silicon oxide film, and the first etching step is “CF 4 ”. And “O 2 ” and inactive
Performed in a mixed atmosphere with an inert gas, and the second etching step is performed using “CF 4 ” and an inert gas.
A method for manufacturing a semiconductor integrated circuit, wherein the method is performed in a mixed atmosphere . 【請求項２】 下部金属配線が埋め込まれた下部層間膜
上に上部層間膜を堆積する工程と、 その後前記上部層間膜の前記下部金属配線の位置に対向
する位置にヴァイアホールを形成する工程と、 その後前記ヴァイアホールを充填するように全面に有機
膜を成膜する工程と、 その後前記ヴァイアホールの位置に対応して前記ヴィア
ホールにり幅広に開口したレジストマスクを形成する工
程と、 その後前記上部層間膜の表面が露出するまで前記有機膜
をエッチングする第１のエッチング工程と、 その後前記有機膜の方が前記上部層間膜よりエッチング
レートが高い雰囲気中で前記有機膜と前記上部層間膜と
を途中までエッチングする第２のエッチング工程と、 その後前記ヴィアホールに残存している前記有機膜を除
去する第３のエッチング工程と、 その後全面に金属膜を成膜する工程と、 を備えており、 前記有機膜はＡＲＣ膜であり、 前記上部層間膜はシリコン酸化膜であり、 前記第１のエッチング工程は“Ｃ 2 Ｆ 6 ”と“Ｏ 2 ”と不
活性ガスとの混合雰囲気で行い、 前記第２のエッチング工程は“Ｃ 2 Ｆ 6 ”と不活性ガスと
の混合雰囲気で行う ことを特徴とする半導体集積回路の
製造方法。A step of depositing an upper interlayer film on the lower interlayer film in which the lower metal wiring is embedded; and a step of forming a via hole at a position of the upper interlayer film opposite to the position of the lower metal wiring. A step of forming an organic film over the entire surface so as to fill the via hole, and a step of forming a resist mask having a wide opening in the via hole corresponding to the position of the via hole. A first etching step of etching the organic film until the surface of the upper interlayer film is exposed, and thereafter, the organic film and the upper interlayer film in an atmosphere in which the organic film has a higher etching rate than the upper interlayer film. A second etching step of partially etching the substrate, and a third etching step of subsequently removing the organic film remaining in the via hole And a step of subsequently forming a metal film on the entire surface , wherein the organic film is an ARC film, the upper interlayer film is a silicon oxide film, and the first etching step is “C 2 F 6 "and" the O 2 "not
Carried out in a mixed atmosphere of active gas, the second etching step and "C 2 F 6" and an inert gas
A method for manufacturing a semiconductor integrated circuit, wherein the method is performed in a mixed atmosphere . 【請求項３】 前記下部層間膜上にストッパ膜を介して
前記上部層間膜を堆積させ、 前記上部層間膜に前記ヴィアホールを前記ストッパ膜の
表面まで形成し、 前記第３のエッチング工程で前記ヴィアホールに残存し
ている前記有機膜を除去して前記ストッパ膜を露出さ
せ、 前記ヴァイアホールの底部に位置する前記ストッパ膜を
エッチングしてから金属膜を成膜することを特徴とする
請求項１または２に記載の半導体集積回路の製造方法。3. An upper interlayer film is deposited on the lower interlayer film via a stopper film, the via hole is formed in the upper interlayer film up to the surface of the stopper film, and the via hole is formed in the third etching step. The organic film remaining in the via hole is removed to expose the stopper film, and the stopper film located at the bottom of the via hole is etched to form a metal film.
A method for manufacturing a semiconductor integrated circuit according to claim 1 . 【請求項４】 前記雰囲気の圧力が“100(mToll)”以上
である請求項１ないし３の何れか一項に記載の半導体集
積回路の製造方法。4. A manufacturing method of a semiconductor integrated circuit according to any one of 3 claims 1 pressure is "100 (mToll)" or the atmosphere. 【請求項５】 下部金属配線が埋め込まれている層間膜
の表面から所定深度まで凹溝が形成されており、この凹
溝の底部にヴァイアホールが形成されており、このヴァ
イアホールの底部に前記下部金属配線が露出している半
導体集積回路であって、請求項１ないし４ の何れか一項に記載の製造方法により
製造されている半導体集積回路。5. A groove is formed to a predetermined depth from the surface of the interlayer film in which the lower metal wiring is embedded, a via hole is formed at the bottom of the groove, and the via hole is formed at the bottom of the via hole. A semiconductor integrated circuit having a lower metal wiring exposed, the semiconductor integrated circuit being manufactured by the manufacturing method according to claim 1 .
JP2000009221A 2000-01-18 2000-01-18 Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit Expired - Lifetime JP3346475B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000009221A JP3346475B2 (en) 2000-01-18 2000-01-18 Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit
TW089127535A TW567530B (en) 2000-01-18 2000-12-21 Manufacturing method semiconductor integrated circuit including simultaneous formation of via hole reaching metal wiring and concave groove in interlayer film and semiconductor integrated circuit manufactured with the manufacturing method
US09/751,979 US6809037B2 (en) 2000-01-18 2000-12-29 Manufacturing method of semiconductor integrated circuit including simultaneous formation of via-hole reaching metal wiring and concave groove in interlayer film and semiconductor integrated circuit manufactured with the manufacturing method
KR10-2001-0001760A KR100382089B1 (en) 2000-01-18 2001-01-12 Manufacturing method of semiconductor integrated circuit including simultaneous formation of via hole reaching metal wiring and concave groove in interlayer film and semiconductor integrated circuit manufactured with the manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000009221A JP3346475B2 (en) 2000-01-18 2000-01-18 Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JP2001203207A JP2001203207A (en) 2001-07-27
JP3346475B2 true JP3346475B2 (en) 2002-11-18

Family

ID=18537393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000009221A Expired - Lifetime JP3346475B2 (en) 2000-01-18 2000-01-18 Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit

Country Status (4)

Country Link
US (1) US6809037B2 (en)
JP (1) JP3346475B2 (en)
KR (1) KR100382089B1 (en)
TW (1) TW567530B (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180525B1 (en) * 1998-08-19 2001-01-30 Micron Technology, Inc. Method of minimizing repetitive chemical-mechanical polishing scratch marks and of processing a semiconductor wafer outer surface
US6391757B1 (en) * 2001-06-06 2002-05-21 United Microelectronics Corp. Dual damascene process
KR100434511B1 (en) * 2002-08-12 2004-06-05 삼성전자주식회사 Method for fabricating semiconductor devices by forming damascene interconnections
KR100462884B1 (en) * 2002-08-21 2004-12-17 삼성전자주식회사 Dual Damascene Interconnection Formation Method in Semiconductor Device using Sacrificial Filling Material
KR100441685B1 (en) * 2002-09-19 2004-07-27 삼성전자주식회사 Dual damascene process
JP4487489B2 (en) 2002-09-20 2010-06-23 三菱電機株式会社 Embedding material and manufacturing method of semiconductor integrated circuit using the embedding material
KR100583957B1 (en) * 2003-12-03 2006-05-26 삼성전자주식회사 Method of forming a dual damascene metal interconnection employing a sacrificial metal oxide layer
KR101016340B1 (en) 2003-12-15 2011-02-22 매그나칩 반도체 유한회사 Method of manufacturing inductor in RF semiconductor device
WO2005086962A2 (en) * 2004-03-11 2005-09-22 The University Of Vermont And State Agricultural College System and method for fabricating a crystalline thin structure
US20080138927A1 (en) * 2004-03-11 2008-06-12 The University Of Vermont And State Agricultural College Systems and Methods for Fabricating Crystalline Thin Structures Using Meniscal Growth Techniques
KR100704471B1 (en) * 2004-10-30 2007-04-10 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US20080020584A1 (en) * 2006-03-24 2008-01-24 Shin Hirotsu Method of manufacturing semiconductor device and plasma processing apparatus
JP2008085005A (en) * 2006-09-27 2008-04-10 Elpida Memory Inc Method of manufacturing semiconductor device
JP5293145B2 (en) * 2008-12-17 2013-09-18 大日本印刷株式会社 Semiconductor device
JP5218214B2 (en) * 2009-03-31 2013-06-26 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP6869875B2 (en) * 2017-11-24 2021-05-12 ルネサスエレクトロニクス株式会社 Semiconductor devices and methods for manufacturing semiconductor devices

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
JP3281260B2 (en) 1996-05-21 2002-05-13 株式会社東芝 Method for manufacturing semiconductor device
JPH10209273A (en) * 1997-01-16 1998-08-07 Fujitsu Ltd Manufacture of semiconductor device
US5883006A (en) 1997-12-12 1999-03-16 Kabushiki Kaisha Toshiba Method for making a semiconductor device using a flowable oxide film
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
TW410455B (en) * 1998-02-16 2000-11-01 United Microelectronics Corp Forming method for dual damascene structure
JP3403058B2 (en) 1998-03-26 2003-05-06 株式会社東芝 Wiring formation method
US6042999A (en) * 1998-05-07 2000-03-28 Taiwan Semiconductor Manufacturing Company Robust dual damascene process
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
JP3214475B2 (en) * 1998-12-21 2001-10-02 日本電気株式会社 Method of forming dual damascene wiring
US6262484B1 (en) * 1999-04-20 2001-07-17 Advanced Micro Devices, Inc. Dual damascene method for backened metallization using poly stop layers
US6362093B1 (en) * 1999-08-20 2002-03-26 Taiwan Semiconductor Manufacturing Company Dual damascene method employing sacrificial via fill layer
US6323123B1 (en) * 2000-09-06 2001-11-27 United Microelectronics Corp. Low-K dual damascene integration process

Also Published As

Publication number Publication date
KR20010086322A (en) 2001-09-10
TW567530B (en) 2003-12-21
KR100382089B1 (en) 2003-05-09
JP2001203207A (en) 2001-07-27
US20010008802A1 (en) 2001-07-19
US6809037B2 (en) 2004-10-26

Similar Documents

Publication Publication Date Title
US6514852B2 (en) Semiconductor device and method of manufacturing the same
US6337519B1 (en) Semiconductor device having a multilayered interconnection structure
JP3346475B2 (en) Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit
US5990015A (en) Dual damascence process
US6323118B1 (en) Borderless dual damascene contact
US5899738A (en) Method for making metal plugs in stacked vias for multilevel interconnections and contact openings while retaining the alignment marks without requiring extra masking steps
EP1282165A2 (en) Semiconductor device and manufacturing method thereof
US7378340B2 (en) Method of manufacturing semiconductor device and semiconductor device
JP3700460B2 (en) Semiconductor device and manufacturing method thereof
KR20010098774A (en) Semiconductor Device and Manufacturing Method of the Device
JP3312604B2 (en) Method for manufacturing semiconductor device
JP3448025B2 (en) Method for manufacturing semiconductor device
JP3183238B2 (en) Method for manufacturing semiconductor device
US6399424B1 (en) Method of manufacturing contact structure
US6204096B1 (en) Method for reducing critical dimension of dual damascene process using spin-on-glass process
US20080174019A1 (en) Semiconductor device and method for manufacturing the same
US20040048203A1 (en) Method of manufacturing a semiconductor device for high speed operation and low power consumption
US6764957B2 (en) Method for forming contact or via plug
JP2003086679A (en) Integrated circuit device and its manufacturing method
JP3317279B2 (en) Method for manufacturing semiconductor device
KR100737701B1 (en) Method of manufacturing wire in a semiconductor device
US6642139B1 (en) Method for forming interconnection structure in an integration circuit
US6284645B1 (en) Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process
JP3432216B2 (en) Method for manufacturing semiconductor device
JP2000183166A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
R150 Certificate of patent or registration of utility model

Ref document number: 3346475

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080906

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080906

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090906

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090906

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100906

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100906

Year of fee payment: 8

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100906

Year of fee payment: 8

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110906

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120906

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120906

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130906

Year of fee payment: 11

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term