JP3314590B2 - High frequency inverter - Google Patents
High frequency inverterInfo
- Publication number
- JP3314590B2 JP3314590B2 JP22327395A JP22327395A JP3314590B2 JP 3314590 B2 JP3314590 B2 JP 3314590B2 JP 22327395 A JP22327395 A JP 22327395A JP 22327395 A JP22327395 A JP 22327395A JP 3314590 B2 JP3314590 B2 JP 3314590B2
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- current
- load
- diode
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Inverter Devices (AREA)
- Power Conversion In General (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、誘導加熱用高周波
電源装置の電圧形高周波インバータに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage type high frequency inverter of a high frequency power supply for induction heating.
【０００２】[0002]
【従来の技術】電圧形インバータは図３に示すように直
流電源Ｐ，Ｎ間に半導体スイッチング素子（自己消弧素
子）Ｓｕ〜Ｓｙを接続した構成となっていて、出力電流
Ｉ0が正弦波で出力電圧Ｖ0は方形波となる。このため出
力電流Ｉ0を出力電圧Ｖ0より若干の遅れ位相となるよう
にインバータを動作させると、スナバ回路を使用しなく
ても電圧サージが発生せず素子の電圧責務が低減して装
置を安定に運転することができる。BACKGROUND OF THE INVENTION Voltage source inverters have been direct-current power supply P, as shown in FIG. 3, a structure of connecting the semiconductor switching elements (self-turn-off devices) Su～Sy between N, the output current I 0 is a sine wave , The output voltage V 0 becomes a square wave. Therefore, if the inverter is operated so that the output current I 0 has a slightly delayed phase from the output voltage V 0, voltage surge does not occur even if a snubber circuit is not used, and the voltage responsibilities of the elements are reduced. It can drive stably.
【０００３】その理由を図４，図５を用いて説明する。
スイッチング素子Ｓｕ及びＳｘに図４のようにゲートＯ
Ｎ期間Ａ及びＣにゲート信号Ｕ及びＸを加える。期間Ａ
では素子ＳｕがＯＮ、デッドタイム期間Ｂでは素子Ｓｕ
がＯＮ→ＯＦＦ、素子ＳｘがＯＦＦする。素子ＳｕがＯ
ＦＦしたことにより出力電流Ｉ0は素子Ｓｘ側の浮遊キ
ャパシタＣ0（図８）から供給される。これにより素子
Ｓｘの浮遊キャパシタの電圧は低下（−△Ｖ）して、素
子Ｓｕ側の浮遊キャパシタの電圧は上昇（＋△Ｖ）す
る。その後素子Ｓｘの浮遊キャパシタが完全に放電する
と、素子Ｓｕ側の浮遊キャパシタ電圧は電源電圧Ｅｄま
で上昇する。The reason will be described with reference to FIGS.
The switching elements Su and Sx are connected to the gate O as shown in FIG.
Gate signals U and X are applied to N periods A and C. Period A
In the element Su, the element Su is ON, and in the dead time period B, the element Su
Turns ON → OFF, and the element Sx turns OFF. Element Su is O
The output current I 0 is supplied from the floating capacitor C 0 (FIG. 8) on the element Sx side by the FF. As a result, the voltage of the floating capacitor of the element Sx decreases (−ΔV), and the voltage of the floating capacitor on the element Su side increases (+ ΔV). Thereafter, when the floating capacitor of the element Sx is completely discharged, the floating capacitor voltage on the element Su side rises to the power supply voltage Ed.
【０００４】期間Ｃでは素子ＳｕがＯＦＦ，素子Ｓｘが
ＯＦＦ→ＯＮし、素子内ダイオードＤ0（図８）を通し
て流れる電流が正から負に反転した時点で素子Ｓｘを通
して電流がスムーズに移行するため、スイッチングによ
る異常なサージ電圧は発生しない。[0004] Period C the element Su is OFF, the element Sx is OFF → ON, and because the current is a smooth transition through the element Sx when the current flowing through the element in the diode D 0 (FIG. 8) is inverted from positive to negative No abnormal surge voltage due to switching is generated.
【０００５】特に、数百ＫＨｚの高周波インバータを動
作させる場合は、スイッチング素子に並列にスナバ回路
を使用すると、スイッチングによる電圧は低減できるが
スナバ損失が大きくなるため、負荷同期をとり常にイン
バータを遅れ電流で制御する方式としてスナバ回路を小
形化している。In particular, when a high-frequency inverter of several hundred KHz is operated, if a snubber circuit is used in parallel with the switching element, the voltage due to switching can be reduced, but the snubber loss increases. The snubber circuit has been downsized as a method of controlling by current.
【０００６】[0006]
【発明が解決しようとする課題】前記遅れ電流制御の場
合は電流がスイッチング素子のＯＮ，ＯＦＦ動作でスム
ーズに転流するが、急激な負荷変動（周波数急変）が発
生する場合は制御遅れ等により進み電流モードでインバ
ータが動作する場合が発生する。進み電流モードでイン
バータが動作すると、スイッチング時に急峻な電圧サー
ジが発生する。In the case of the delay current control, the current commutates smoothly due to the ON / OFF operation of the switching element. However, when a sudden load change (rapid change in frequency) occurs, the current is reduced due to a control delay or the like. In some cases, the inverter operates in the leading current mode. When the inverter operates in the leading current mode, a steep voltage surge occurs during switching.
【０００７】その理由を図６，図７を用いて説明する。
期間Ａの後半では素子ＳｕはＯＮしているが電流は進み
のため素子内ダイオードＤ0に流れている。期間Ｂでは
素子ＳｕがＯＮ→ＯＦＦ，素子ＳｘがＯＦＦとなるが、
素子内ダイオードＤ0に電流が流れているため素子Ｓｕ
がＯＦＦしてもモードは変化しない。期間Ｃでは素子Ｓ
ｕがＯＦＦ，素子ＳｘがＯＦＦ→ＯＮとなるが、この状
態で素子ＳｘがＯＮすると素子Ｓｘ側の浮遊キャパシタ
は急峻に放電すると同時に、素子Ｓｕ側の素子内ダイオ
ードＤ0の逆回復が発生し、直流短絡現象が発生すると
同時に素子Ｓｕ側の浮遊キャパシタＣ0の急峻な充電現
象が起り電圧サージが発生する。The reason will be described with reference to FIGS.
Element Su in the second half of the period A is in the ON state current is flowing in the element in the diode D 0 for the advance. In the period B, the element Su turns from ON to OFF and the element Sx turns OFF.
Since a current flows through the diode D 0 in the element, the element Su
Does not change even if is turned off. In the period C, the element S
u turns off and the element Sx changes from OFF to ON. If the element Sx turns on in this state, the floating capacitor on the element Sx side discharges sharply, and at the same time, the diode D 0 in the element on the element Su side. At the same time, a DC short-circuit phenomenon occurs, and at the same time, a steep charging phenomenon of the floating capacitor C 0 on the element Su side occurs, and a voltage surge occurs.
【０００８】この急峻な電圧サージが発生すると素子の
電圧耐量以上の責務が発生したり、制御回路がノイズで
誤動作する場合がある。この対策として損失を犠牲にし
てスイッチング素子に並列にスナバ回路を入れるか又は
急峻な負荷変動（周波数急変）が発生するシステムには
適用できない欠点があった。[0008] When the steep voltage surge occurs, a duty higher than the withstand voltage of the element may occur, or the control circuit may malfunction due to noise. As a countermeasure against this, there is a drawback that it cannot be applied to a system in which a snubber circuit is inserted in parallel with the switching element at the expense of loss or a steep load change (sudden frequency change) occurs.
【０００９】本発明は、従来のこのような問題点に鑑み
てなされたものであり、その目的とするところは、スイ
ッチング素子内ダイオードの逆回復期間中に発生する直
流短絡現象をなくして素子破損を防止することができる
高周波インバータを提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to eliminate a DC short-circuit phenomenon that occurs during a reverse recovery period of a diode in a switching element and to damage the element. It is an object of the present invention to provide a high-frequency inverter capable of preventing the problem.
【００１０】[0010]
【課題を解決するための手段】自己消弧素子を使用した
電圧形インバータにおいて、インバータの出力端子と直
列共振負荷の端子との間に逆並列ダイオードと高周波リ
アクトルの直列回路を接続し、負荷の端子と直流電源と
の間に外付帰還ダイオードを接続し、インバータの出力
端子間に直流抑制用抵抗又はコンデンサと遅れ電流供給
用リアクトルとの直列回路からなるダミー遅れ負荷を接
続してなるものである。SUMMARY OF THE INVENTION In a voltage source inverter using a self-extinguishing element, the output terminal of the inverter is directly
A series circuit of anti-parallel diodes and high frequency reactor between the terminals of the column resonant load, connect the external feedback diode between the load terminal and the DC power source, the resistor for DC suppression between the inverter output terminal Alternatively, a dummy delay load consisting of a series circuit of a capacitor and a reactor for supplying a delay current is connected.
【００１１】[0011]
【発明の実施の形態】実施の形態１ 図１はインバータの主回路を示すもので、Ｓｕ〜Ｓｙは
インバータの各アームを構成するスイッチング素子（自
己消弧素子）、１１はインバータの直列共振負荷、Ｄｕ
〜Ｄｙは負荷１１の端子Ｃ，Ｄとインバータの直流電源
Ｐ，Ｎとの間に接続された外付帰還ダイオード、１２は
インバータの出力端子Ａ，Ｂ間に接続された直流分抑制
抵抗Ｒ1と遅れ電流供給用リアクトルＬ1からなるダミー
遅れ負荷、１３はインバータの出力端子Ａと負荷の端子
Ｃとの間に直列に接続された逆並列ダイオードＤ1，Ｄ2
とフエライトコア入りの高周波リアクトルＬ2からなる
電流抑制回路、１４はインバータの出力端子Ｂと負荷の
端子Ｄとの間に直列に接続された逆並列ダイオード
Ｄ3，Ｄ4をフエライトコア入りの高周波リアクトルＬ4
からなる電流抑制回路である。なお、Ｃ0及びＤ0はスイ
ッチング素子内浮遊コンデンサ及び素子内ダイオード
（図８）を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows a main circuit of an inverter, where Su to Sy are switching elements (self-extinguishing elements) constituting each arm of the inverter, and 11 is a series resonant load of the inverter. , Du
Dy is an external feedback diode connected between the terminals C and D of the load 11 and the DC power supplies P and N of the inverter, and 12 is a DC component suppressing resistor R 1 connected between the output terminals A and B of the inverter. And a dummy delay load 13 consisting of a delay current supply reactor L 1 and anti-parallel diodes D 1 and D 2 connected in series between the output terminal A of the inverter and the terminal C of the load.
A high frequency reactor L 2 consisting of current control circuit of the ferrite core containing 14 high frequency antiparallel diodes D 3, D 4 connected in series between the terminal D of the load and the output terminal B of the inverter of the ferrite core containing Reactor L 4
Is a current suppressing circuit. C 0 and D 0 indicate a floating capacitor in the switching element and a diode in the element (FIG. 8).
【００１２】以上のように、インバータが構成されてい
るので、定常運転時は遅れダミー負荷１２の遅れ電流を
取り込むリアクトルＬ１及び出力電流と出力電圧の関係
を、出力電流遅れモードで同期制御して運転することに
より、スイッチング素子Ｓｕ〜Ｓｙの浮遊キャパシタＣ
0の電荷を放電させるための電流を確保することができ
ると共に、方形波出力電圧に含まれる直流分はダミー遅
れ負荷の抵抗Ｒ１により抑制される。As described above, since the inverter is configured, during the steady operation, the reactor L1 that takes in the delay current of the delay dummy load 12 and the relationship between the output current and the output voltage are synchronously controlled in the output current delay mode. By driving, the floating capacitors C of the switching elements Su to Sy
A current for discharging the zero charge can be secured, and the DC component included in the square wave output voltage is suppressed by the resistance R1 of the dummy delay load.
【００１３】負荷の急峻な変動（周波数急変）が生じ電
流が進みモードとなった時は、外付帰還ダイオードＤｕ
〜Ｄｙを通して進み電流が環流する。この電流は、逆並
列ダイオードＤ１，Ｄ２、Ｄ３，Ｄ４と素子内ダイオー
ドＤ0が直列となっているので、外付ダイオードＤｕ〜
Ｄｙのみに流れ、素子内ダイオードＤ0へは進み電流は
流れない。When a sudden change in the load (sudden frequency change) occurs and the current is in the advanced mode, the external feedback diode Du is used.
Through Dy, the current flows back. This current, since the anti-parallel diodes D1, D2, D3, D4 and elements within da Io <br/> de D 0 is in the series, external diode Du~
Flows only to Dy, the leading current does not flow into the element in the diode D 0.
【００１４】デッドタイム期間を通して他素子へ転流の
際の外付ダイオードの逆回復による直流短絡電流は、逆
並列ダイオードＤ１，Ｄ２，Ｄ３，Ｄ４に直列に接続し
たフエライトコアを有する高周波リアクトルＬ２，Ｌ４
によりその変化分（ｄｉ／ｄｔ）が抑制されるので、ス
イッチング素子がＯＦＦするとき異常なサージを発生す
ることがない。The DC short-circuit current due to the reverse recovery of the external diode during commutation to another element throughout the dead time period is caused by the high-frequency reactor L2 having a ferrite core connected in series to the antiparallel diodes D1, D2, D3, and D4. L4
Therefore, the amount of change (di / dt) is suppressed, so that an abnormal surge does not occur when the switching element is turned off.
【００１５】上記ではダミー遅れ負荷として遅れ電流供
給用リアクトルＬ１と直列に方形波出力電圧に含まれる
直流分を抑制する抵抗Ｒ１を接続しているが、抵抗Ｒ１
に代わりにコンデンサＣ１を用いても方形波出力電圧に
含まれる直流分を除去することができる。このコンデン
サ直列接続方式は抵抗直列接続方式に比べて直流分に対
するインピーダンスがコンデンサ容量にかかわらず無限
大となるため回路電流と周波数条件さえ注意すればよ
く、選定が容易となる。In the above, the resistor R1 for suppressing the DC component included in the square wave output voltage is connected in series with the delay current supply reactor L1 as a dummy delay load.
Alternatively, the DC component included in the square wave output voltage can be removed by using the capacitor C1 instead. In this capacitor series connection method, the impedance for the DC component becomes infinite irrespective of the capacitance of the capacitor as compared with the resistance series connection method.
【００１６】実施の形態２ 図２はハーフブリッジ回路で高周波インバータを構成し
た例を示す。この回路は図１のインバータのスイッチン
グ素子Ｓｕ，帰還ダイオードＤｕ等で構成されるアーム
とスイッチング素子Ｓｘ，帰還ダイオードＤｘ等で構成
されるアームに代えてコンデンサＣｕとＣｘを使用した
もので作用及び動作は上記実施の形態１と変わりがない
ので、説明を省略する。Embodiment 2 FIG. 2 shows an example in which a half-bridge circuit constitutes a high-frequency inverter. This circuit operates and operates by using capacitors Cu and Cx instead of the arm composed of the switching element Su and the feedback diode Du of the inverter of FIG. 1 and the arm composed of the switching element Sx and the feedback diode Dx. Is the same as in the first embodiment, and the description is omitted.
【００１７】[0017]
【発明の効果】本発明は、上述のとおり構成されている
ので、次に記載する効果を奏する。Since the present invention is configured as described above, the following effects can be obtained.
【００１８】（１）スイッチング素子内ダイオードに進
み電流が流れなくなり、素子内ダイオードの逆回復期間
中直流短絡現象が発生しないので、素子破損を防止でき
る。(1) Current does not flow through the diode in the switching element, and no DC short circuit occurs during the reverse recovery period of the diode in the element, so that damage to the element can be prevented.
【００１９】（２）スイッチング素子の遅れ電流をＬ−
Ｒ又はＬ−Ｃの直列回路からなるダミー遅れ負荷に取込
むことができるので、素子の浮遊キャパシタに充電され
た電荷を放電する電流が確保され、電流がスムーズに移
動するので、異常サージ電圧が発生せず、素子の破損を
防止できる。(2) The delay current of the switching element is represented by L-
Since it is possible to take in the dummy delay load composed of the R or LC series circuit, a current for discharging the electric charge charged in the floating capacitor of the element is secured, and the current moves smoothly. This does not occur, and damage to the element can be prevented.
【００２０】（３）外付けダイオードの逆回復期間中の
直流短絡は逆並列ダイオードと直列のリアクトルにより
その電流の変化が抑制され、スイッチング素子の破損を
防止できる。(3) The DC short circuit during the reverse recovery period of the external diode is prevented from changing its current by the reactor connected in series with the anti-parallel diode, thereby preventing the switching element from being damaged.
【００２１】（４）主回路のみの対策であるため誤動作
することがない。(4) There is no malfunction because the measure is taken only for the main circuit.
【００２２】（５）スナバ回路が不要となるので、損失
が少なくてすむ。(5) Since a snubber circuit is not required, the loss can be reduced.
【図１】実施の態様１を示すインバータ主回路図。FIG. 1 is an inverter main circuit diagram showing a first embodiment.
【図２】実施の態様２を示すインバータ主回路図。FIG. 2 is an inverter main circuit diagram showing a second embodiment.
【図３】インバータの基本回路図。FIG. 3 is a basic circuit diagram of an inverter.
【図４】遅れモード時の動作を説明する波形図。FIG. 4 is a waveform diagram illustrating an operation in a delay mode.
【図５】遅れモード時の動作説明図。FIG. 5 is an explanatory diagram of an operation in a delay mode.
【図６】進みモード時の動作を説明する波形図。FIG. 6 is a waveform chart for explaining the operation in the advance mode.
【図７】進みモード時の動作説明図。FIG. 7 is an explanatory diagram of an operation in an advance mode.
【図８】スイッチング素子の等価回路図。FIG. 8 is an equivalent circuit diagram of a switching element.
Ｓｕ〜Ｓｙ…スイッチング素子（自己消弧素子） Ｄｕ〜Ｄｙ…外付（帰還）ダイオード １１…直列共振負荷 １２…ダミー遅れ負荷 １３，１４…電流抑制回路 Ｌ１…遅れ電流供給用リアクトル Ｌ３，Ｌ４…フエライトコアを有する電流変化抑制用リ
アクトル Ｄ１〜Ｄ４…素子内ダイオード通電阻止用ダイオード Ｄ0…素子内（寄生）ダイオード Ｒ１…直流分抑制用抵抗 Ｃ１…直流分抑制用コンデンサ ＣD…平滑用コンデンサ Ｃ0…素子内（浮遊）コンデンサSu to Sy: switching element (self-extinguishing element) Du to Dy: external (feedback) diode 11: series resonance load 12, dummy delay load 13, 14, current suppression circuit L1: delay current supply reactor L3, L4 reactor current change suppressing having ferrite core D1 to D4 ... elements in the diode current-blocking diode D 0 ... the element (parasitic) diodes R1 ... capacitor DC component suppression resistors C1 ... DC component suppression C D ... smoothing capacitor C 0 … in-element (floating) capacitor
フロントページの続き (56)参考文献 特開 平７−79574（ＪＰ，Ａ) 特開 昭55−83472（ＪＰ，Ａ) 特公 昭55−47560（ＪＰ，Ｂ１) 特表 平５−502365（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H02M 7/48 H02M 1/06 H02M 7/5387 Continuation of the front page (56) References JP-A-7-79574 (JP, A) JP-A-55-83472 (JP, A) JP-B-55-47560 (JP, B1) JP-A-5-502365 (JP) , A) (58) Field surveyed (Int. Cl. 7 , DB name) H02M 7/48 H02M 1/06 H02M 7/5387
Claims (1)
タにおいて、 インバータの出力端子と直列共振負荷の端子との間に逆
並列ダイオードと高周波リアクトルの直列回路を接続
し、負荷の端子と直流電源との間に外付帰還ダイオード
を接続し、 インバータの出力端子間に直流抑制用抵抗又はコンデン
サと遅れ電流供給用リアクトルとの直列回路からなるダ
ミー遅れ負荷を接続し、 てなることを特徴とした高周波インバータ。1. A voltage source inverter using a self-extinguishing element, wherein a series circuit of an anti-parallel diode and a high-frequency reactor is connected between an output terminal of the inverter and a terminal of a series resonance load, and a terminal of the load and a DC power supply are connected. connect the external feedback diode between, connecting the dummy delay load comprising a series circuit of the DC suppression resistors or capacitors and delays current supply reactor between the inverter output terminal, it was characterized by comprising Te High frequency inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22327395A JP3314590B2 (en) | 1995-08-31 | 1995-08-31 | High frequency inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22327395A JP3314590B2 (en) | 1995-08-31 | 1995-08-31 | High frequency inverter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0970174A JPH0970174A (en) | 1997-03-11 |
| JP3314590B2 true JP3314590B2 (en) | 2002-08-12 |
Family
ID=16795546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22327395A Expired - Fee Related JP3314590B2 (en) | 1995-08-31 | 1995-08-31 | High frequency inverter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3314590B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4783905B2 (en) * | 2004-08-16 | 2011-09-28 | 国立大学法人東京海洋大学 | Zero voltage switching high frequency inverter |
| JP5552972B2 (en) * | 2010-09-02 | 2014-07-16 | 三菱電機株式会社 | Semiconductor switching device |
-
1995
- 1995-08-31 JP JP22327395A patent/JP3314590B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0970174A (en) | 1997-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2373762C (en) | Method and apparatus for converting a dc voltage to an ac voltage | |
| US6937483B2 (en) | Device and method of commutation control for an isolated boost converter | |
| JP2674341B2 (en) | Snubber circuit of power converter | |
| US5027263A (en) | Switching power source means | |
| JP2807760B2 (en) | Switching power supply | |
| JPH03230764A (en) | Power supply device using pwm control | |
| JPH0760998B2 (en) | All bridge / power conversion circuit | |
| EP0783203B1 (en) | Bridge power converter | |
| US5063488A (en) | Switching power source means | |
| JP3221185B2 (en) | Switching power supply | |
| JP3314590B2 (en) | High frequency inverter | |
| JP2801621B2 (en) | Power supply device by PWM control | |
| KR19980065882A (en) | Lossless snubber circuit and input power factor improvement circuit for soft switching of DC / DC converter | |
| JPH11150952A (en) | Switching dc power supply equipment | |
| JP3303573B2 (en) | Pulse power supply | |
| KR102616556B1 (en) | direct current pulse power supply | |
| JPH10309078A (en) | Switching dc power unit | |
| JP3468261B2 (en) | Bridge type inverter device | |
| JP2003052166A (en) | Switching power circuit | |
| JP3327754B2 (en) | Gate drive device for semiconductor switching element | |
| JP3291031B2 (en) | Inverter device | |
| JP2962388B2 (en) | Two-stone insulated switching power supply | |
| JPH0928087A (en) | Pulse power supply apparatus | |
| CA2017639C (en) | Switching power source means | |
| JPH1023742A (en) | Semiconductor power converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090607 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090607 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100607 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110607 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110607 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120607 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130607 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |