JP3308713B2 - Electronics - Google Patents

Electronics

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Publication number
JP3308713B2
JP3308713B2 JP14845994A JP14845994A JP3308713B2 JP 3308713 B2 JP3308713 B2 JP 3308713B2 JP 14845994 A JP14845994 A JP 14845994A JP 14845994 A JP14845994 A JP 14845994A JP 3308713 B2 JP3308713 B2 JP 3308713B2
Authority
JP
Japan
Prior art keywords
electrode
good heat
semiconductor element
substrate
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14845994A
Other languages
Japanese (ja)
Other versions
JPH07335823A (en
Inventor
泰男 長谷川
裕二 秋山
忠夫 菊地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
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Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP14845994A priority Critical patent/JP3308713B2/en
Publication of JPH07335823A publication Critical patent/JPH07335823A/en
Application granted granted Critical
Publication of JP3308713B2 publication Critical patent/JP3308713B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、セラミクス基板のよう
な電気絶縁基板に固着された半導体素子又は電力制御用
半導体素子などを樹脂封止してなる小型、軽量、薄型で
表面実装に適した半導体装置、電子回路装置を金属基板
に搭載してなる電子機器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compact, lightweight, thin, and suitable for surface mounting in which a semiconductor element fixed to an electrically insulating substrate such as a ceramic substrate or a power control semiconductor element is sealed with a resin. The present invention relates to an electronic device in which a semiconductor device and an electronic circuit device are mounted on a metal substrate.

【０００２】[0002]

【従来の技術】一般にコンバ−タ電源機器などの電子機
器は、ますます小形化が要求され、表面実装法によるオ
ンボ−ド電源（ＯＢＰ）などの開発が進められている。
しかし、大容量のコンバ−タを小形のＯＢＰとするに
は、これらに使用される一部の半導体部品は大き過ぎる
ために全体を小形化できない問題が生じている。特に、
比較的容量の大きいショットキ−バリアダイオ−ド、バ
イポーラトランジスタ、ＭＯＳＦＥＴなどの半導体部品
は、半導体素子からの発熱が大きいので、金属製ヒ−ト
シンクと外部リ−ドを同時にトランスファ−モ−ルドし
て放熱効果を大ならしめているので、大型化せざるを得
ないという実情がある。2. Description of the Related Art In general, electronic devices such as converter power supply devices are required to be further miniaturized, and on-board power supply (OBP) by a surface mounting method is being developed.
However, in order to convert a large-capacity converter into a small-sized OBP, there is a problem that some of the semiconductor components used therein are too large and cannot be reduced in size as a whole. In particular,
Semiconductor components such as a Schottky barrier diode, a bipolar transistor, and a MOSFET having a relatively large capacity generate a large amount of heat from a semiconductor element, so that a metal heat sink and an external lead are simultaneously transfer-molded and dissipated. There is a fact that it is necessary to increase the size because the effect is exaggerated.

【０００３】これらのショットキ−バリアダイオ−ド、
バイポーラトランジスタ、ＭＯＳＦＥＴなどの半導体部
品のベアチップである半導体素子をそのまま基板に搭載
し、ボンディングしてモ−ルドすることができれば小形
化には最適であるが、大容量の半導体素子の場合には熱
衝撃性、耐湿性などの信頼性が未だ不十分で検討の余地
がある。また、多くの回路部品が樹脂封止された表面実
装部品で、一部分がベアチップである場合には工程を分
けて搭載し、異なる工程で処理する必要があり、高価な
専用装置が必要で製造工数が増大し、したがってコスト
アップになるという欠点がある。[0003] These Schottky barrier diodes,
It is most suitable for miniaturization if the semiconductor element, which is a bare chip of semiconductor parts such as bipolar transistors and MOSFETs, can be mounted on the substrate as it is and bonded and molded. The reliability, such as impact resistance and moisture resistance, is still insufficient and there is room for study. In addition, if many circuit components are surface-mounted components sealed with resin and some are bare chips, they must be mounted separately and processed in different processes. Has the disadvantage of increasing the cost and therefore the cost.

【０００４】このように表面実装に使用する電子部品
は、品質面の向上はもとより、小型、薄型、軽量、低コ
ストなどが要求されている。一般にコンデンサ、抵抗、
コイル、トランス、ＩＣ、ダイオ−ド、トランジスタな
どの回路部品は基板に搭載され易い形状に設計されてお
り、回路部品を高速表面実装する製造方法へと移行して
いる。この方法は基板の導電パターンの所定位置にクリ
−ムハンダを塗布し、そこへ回路部品を搭載して仮接着
し、リフロ−加熱処理などによりハンダ付けを行うもの
である。表面実装法においては、回路部品を減圧で吸引
し搭載するので必然的に形状は軽量で、かつ封止樹脂上
面がフラットであることが好ましく、外装は品質保持の
ため、電気絶縁性の優れたエポキシ樹脂などを用い、ト
ランスファ−モ−ルド法などで量産される。As described above, electronic components used for surface mounting are required to be small, thin, light, and low in cost, in addition to improving quality. Generally, capacitors, resistors,
Circuit components such as coils, transformers, ICs, diodes, transistors and the like are designed in a shape that can be easily mounted on a substrate, and a transition has been made to a manufacturing method for high-speed surface mounting of circuit components. According to this method, cream solder is applied to a predetermined position of a conductive pattern on a substrate, circuit components are mounted thereon and temporarily bonded, and soldering is performed by reflow heat treatment or the like. In the surface mounting method, since the circuit components are suctioned and mounted under reduced pressure, the shape is inevitably lightweight, and the sealing resin upper surface is preferably flat, and the exterior is excellent in electrical insulation for quality maintenance. It is mass-produced by a transfer mold method using an epoxy resin or the like.

【０００５】図７により従来の小型、薄型、軽量の表面
実装タイプの半導体装置について説明すると、１は比較
的熱伝導性が良好で電気絶縁性にも優れるセラミクス基
板のような電気絶縁基板、２Ａ及び２Ｂは電気絶縁基板
１の一方の主面に形成された内部電極、３はダイオー
ド、トランジスタ、ＩＧＢＴ、サイリスタなどの半導体
部品のベアチップである半導体素子であり、内部電極２
Ａに一方の主電極側がろう付けされ、他方の主電極が金
属ワイヤ４により内部電極２Ｂにワイヤボンディングさ
れる。５Ａ及び５Ｂは電気絶縁基板１の他方の主面に形
成された外部電極であり、外部電極５Ａは後述するとお
り放熱を良好なものにするため、流れる電流容量をはる
かに超える大きな面積を有している。６は電気絶縁基板
１内に複数形成されて内部電極２Ａと外部電極５Ａ、内
部電極２Ｂと外部電極５Ｂをそれぞれ接続するバイアホ
ール、７はエポキシ樹脂のような封止樹脂である。Referring to FIG. 7, a conventional small, thin, and lightweight surface-mount type semiconductor device will be described. Reference numeral 1 denotes an electrical insulating substrate such as a ceramic substrate having relatively good thermal conductivity and excellent electrical insulation. And 2B are internal electrodes formed on one main surface of the electrically insulating substrate 1, and 3 is a semiconductor element which is a bare chip of a semiconductor component such as a diode, a transistor, an IGBT, and a thyristor.
One main electrode side is brazed to A, and the other main electrode is wire-bonded to the internal electrode 2B by the metal wire 4. Reference numerals 5A and 5B denote external electrodes formed on the other main surface of the electrically insulating substrate 1. The external electrode 5A has a large area far exceeding the flowing current capacity in order to improve heat radiation as described later. ing. Reference numeral 6 denotes a via hole formed in the electrically insulating substrate 1 to connect the internal electrode 2A to the external electrode 5A and the internal electrode 2B to the external electrode 5B, respectively. Reference numeral 7 denotes a sealing resin such as an epoxy resin.

【０００６】次に図８によりこのような構造の半導体装
置をオンボード電源のような電子機器の基板１０に搭載
し、接続してなる従来例を説明する。一般に大面積の基
板１０はアルミニウムのような導電性の良好な金属基板
１０Ａとその上面に形成された電気絶縁被膜１０Ｂとか
らなり、その一部分に半導体装置の外部電極５Ａと５Ｂ
それぞれに対応する接続電極１１Ａと１１Ｂを備える。
半導体装置の外部電極５Ａと５Ｂが基板１０の接続電極
１１Ａと１１Ｂに位置するように搭載され、クリームハ
ンダなどでろう付けされる。したがって、半導体素子３
が発する熱のほとんどは内部電極２Ａ、電気絶縁基板
１、外部電極５Ａ及び接続電極１１Ａを通して基板１０
に放熱される。放熱の観点から考えれば、外部電極５Ａ
及び接続電極１Ａが当接する面域が大きい方が放熱が良
好であるので、従来の場合には半導体素子３が位置する
部分に相当する面域よりはるかに大きな外部電極５Ａを
有していた。Next, a conventional example in which a semiconductor device having such a structure is mounted and connected to a substrate 10 of an electronic device such as an on-board power supply will be described with reference to FIG. In general, the large-area substrate 10 includes a metal substrate 10A having good conductivity such as aluminum and an electric insulating film 10B formed on the upper surface thereof, and external electrodes 5A and 5B of the semiconductor device are partially formed on the substrate.
It has connection electrodes 11A and 11B corresponding to each.
The external electrodes 5A and 5B of the semiconductor device are mounted so as to be located on the connection electrodes 11A and 11B of the substrate 10, and are brazed with cream solder or the like. Therefore, the semiconductor element 3
Most of the heat generated by the substrate 10 passes through the internal electrode 2A, the electrically insulating substrate 1, the external electrode 5A and the connection electrode 11A.
The heat is dissipated. From the viewpoint of heat radiation, the external electrode 5A
In addition, since the heat radiation is better when the surface area where the connection electrode 1A contacts is large, the external electrode 5A is much larger than the surface area corresponding to the portion where the semiconductor element 3 is located in the conventional case.

【０００７】[0007]

【発明が解決しようとする課題】しかし、金属基板１０
Ａと接続電極１１Ａとの間には電気絶縁被膜１０Ｂを誘
電体とするキャパシタが形成され、このキャパシタの容
量は電気絶縁被膜１０Ｂを一定とすると、接続電極部分
１１Ａの面積が大きいほど大きくなる。したがって、従
来の半導体装置では放熱をできる限り良好にするため、
接続電極部分１１Ａを半導体素子３の面積よりもかなり
大きな面積としていたため、そのまま表面実装すると、
金属基板１０Ａと接続電極１１Ａを電極板とするキャパ
シタの容量Ｃが大きくならざるを得なかった。そのた
め、半導体装置を高周波で動作させると、１／２・ＣＶ
2 ｆで表される損失が発生し、周波数ｆが高い程、また
電圧Ｖの２乗に比例してその損失が大きくなるため、で
きるだけ小さな容量であることが望まれる。また、損失
を表す前記式からキャパシタンスを形成する部分を固定
電位に維持すれば、数百ｋＨｚ以上の高周波で駆動した
としても、実質的にその部分の周波数ｆは非常に小さく
なるので、損失を大幅に小さくできる。However, the metal substrate 10
A capacitor having the electric insulating film 10B as a dielectric is formed between A and the connecting electrode 11A. The capacitance of this capacitor increases as the area of the connecting electrode portion 11A increases, assuming that the electric insulating film 10B is constant. Therefore, in order to make heat dissipation as good as possible in a conventional semiconductor device,
Since the connection electrode portion 11A had a considerably larger area than the area of the semiconductor element 3, if the surface mounting was performed as it was,
The capacitance C of the capacitor using the metal substrate 10A and the connection electrode 11A as an electrode plate had to be large. Therefore, when the semiconductor device is operated at a high frequency, 1/2 CV
Since a loss represented by 2f occurs and the loss increases as the frequency f increases and in proportion to the square of the voltage V, it is desirable that the capacitance be as small as possible. Further, if the portion forming the capacitance is maintained at a fixed potential according to the above equation representing the loss, even if the portion is driven at a high frequency of several hundred kHz or more, the frequency f of that portion becomes substantially very small. Can be significantly reduced.

【０００８】本発明は、放熱を低下させることなく、こ
のような従来の電子機器の問題点を解決することを主目
的とする。An object of the present invention is to solve such problems of conventional electronic devices without reducing heat radiation.

【０００９】[0009]

【課題を解決するための手段】このような問題点を解決
するため、この発明では、電気絶縁基板の一方の主面上
に互いに離れて形成された複数の内部電極と、その内部
電極に主電極が接続された半導体素子と、その半導体素
子と前記内部電極と前記電気絶縁基板の一方の主面とを
覆う封止樹脂と、前記電気絶縁基板の他方の主面上に互
いに離れて形成された複数の外部電極と、対応する前記
内部電極と外部電極との間を接続するため前記電気絶縁
基板の両主面間に形成された電気接続体とを備えた表面
実装型の半導体装置又は電子回路装置を、表面が電気絶
縁被膜で覆われた金属基板の上に搭載してなる電子機器
において、前記表面実装型の半導体装置又は電子回路装
置は、前記電気絶縁基板の他方の主面上に前記外部電極
から分離されて形成された良導熱体を備え、前記金属基
板は、前記電気絶縁被膜の上に回路パターンの一分とし
て形成された接続電極と、該接続電極に接続されていな
い良導熱部分とを備え、前記外部電極を前記接続電極に
接続すると共に、前記良導熱体を前記良導熱部分に結合
した電子機器を提供するものである。SUMMARY OF THE INVENTION In order to solve such a problem, according to the present invention, a plurality of internal electrodes formed apart from each other on one main surface of an electrically insulating substrate, and the internal electrodes are mainly A semiconductor element to which an electrode is connected, a sealing resin covering the semiconductor element, the internal electrode, and one main surface of the electrical insulating substrate, and formed separately from each other on the other main surface of the electrical insulating substrate; Surface-mounted semiconductor device or electronic device, comprising: a plurality of external electrodes; and an electrical connector formed between both main surfaces of the electrical insulating substrate to connect between the corresponding internal electrode and external electrode. In an electronic apparatus in which a circuit device is mounted on a metal substrate whose surface is covered with an electric insulating film, the surface-mounted semiconductor device or the electronic circuit device is provided on the other main surface of the electric insulating substrate. Separated from the external electrode The metal substrate includes a connection electrode formed as a part of a circuit pattern on the electric insulating film, and a good heat conduction portion not connected to the connection electrode, An electronic device in which an electrode is connected to the connection electrode and the good heat conducting body is coupled to the good heat conducting portion.

【００１０】このような問題点を解決するため、請求項
２では、前記外部電極が前記良導熱体の面積よりも小さ
な面積を有する請求項１に記載の電子機器を提供するも
のである。In order to solve such a problem, the second aspect provides the electronic device according to the first aspect, wherein the external electrode has an area smaller than an area of the good heat conductor.

【００１１】このような問題点を解決するため、請求項
３では、前記良導熱体が前記外部電極の厚みとほぼ等し
い金属板又は金属膜である請求項１又は請求項２に記載
の電子機器を提供するものである。According to a third aspect of the present invention, there is provided an electronic apparatus according to the first or second aspect, wherein the good heat conductor is a metal plate or a metal film substantially equal in thickness to the external electrode. Is provided.

【００１２】このような問題点を解決するため、請求項
４では、前記良導熱体が前記半導体素子又は電力制御用
半導体素子に対応する部分を含む面域に形成される請求
項１乃至請求項３のいずれかに記載の電子機器を提供す
るものである。In order to solve such a problem, according to claim 4, the good heat conductor is formed in a surface area including a portion corresponding to the semiconductor element or the power control semiconductor element. 3. An electronic device according to any one of 3.

【００１３】このような問題点を解決するため、請求項
５では、前記良導熱部分が接地端子に接続される請求項
１乃至請求項４のいずれかに記載の電子機器を提供する
ものである。According to a fifth aspect of the present invention, there is provided an electronic apparatus according to any one of the first to fourth aspects, wherein the good heat conducting portion is connected to a ground terminal. .

【００１４】[0014]

【実施例】図１により本発明にかかる電子機器に用いら
れる半導体装置の一例について説明する。図１は表面実
装型のダイオードの一例を示すもので、図７及び図８で
示した記号と同一の記号については相当する部材を示す
ものとする。セラミクス基板のような比較的導熱性の良
好な電気絶縁基板１の一方の面に固着された内部電極２
Ａには半導体素子３としてダイオードのベアチップが搭
載され、そのアノードがハンダ付けされている。そのカ
ソードは金属ワイヤ４により内部電極２Ｂに接続され
る。したがって、一方の内部電極２Ａが内部アノード端
子、他方の内部電極２Ｂが内部カソード端子となる。内
部電極２Ａは電気絶縁基板１内に形成されたバイアホー
ル６Ａを通して、電気絶縁基板１の他方の面に形成され
た一方の外部電極５Ａに接続される。同様に他方の内部
電極２Ｂもバイアホール６Ｂを通して、電気絶縁基板１
の他方の面に形成された一方の外部電極５Ｂに接続され
る。電気絶縁基板１の他方の面における外部電極５Ａと
外部電極５Ｂとの間に良導熱体８が形成される。ここで
バイアホール６Ａ、６Ｂは良く知られているように、基
板の表面と裏面それぞれに形成された電極間を接続する
電気接続体として働く通常のものである。FIG. 1 shows an example of a semiconductor device used in an electronic apparatus according to the present invention. FIG. 1 shows an example of a surface-mounted diode, and the same symbols as those shown in FIGS. 7 and 8 indicate corresponding members. Internal electrode 2 fixed to one surface of an electrically insulating substrate 1 having relatively good heat conductivity such as a ceramic substrate
A has a bare chip of a diode mounted thereon as the semiconductor element 3, and the anode thereof is soldered. The cathode is connected to the internal electrode 2B by the metal wire 4. Therefore, one internal electrode 2A serves as an internal anode terminal and the other internal electrode 2B serves as an internal cathode terminal. The internal electrode 2A is connected to one external electrode 5A formed on the other surface of the electric insulating substrate 1 through a via hole 6A formed in the electric insulating substrate 1. Similarly, the other internal electrode 2B is also connected to the electrically insulating substrate 1 through the via hole 6B.
Is connected to one of the external electrodes 5B formed on the other surface. Good heat conductor 8 is formed between external electrode 5A and external electrode 5B on the other surface of electrically insulating substrate 1. Here, as is well known, the via holes 6A and 6B are ordinary ones that function as electrical connectors for connecting between electrodes formed on the front surface and the back surface of the substrate.

【００１５】ここで製造工程を簡単にするため、良導熱
体８が外部電極５Ａ、５Ｂと同様な金属材料からなる場
合には、良導熱体８は外部電極５Ａ、５Ｂと接触しない
ように形成され、またバイアホールを介して内部電極２
Ａなどいかなる電極にも接続されることはない。良導熱
体８が電気絶縁基板１の他方の面に形成される位置は、
半導体素子３の搭載位置を含む面域で、しかも許容され
得る限り大きいことが放熱上好ましい。一方、外部電極
５Ａは、好ましくは半導体素子３の搭載位置から外れた
位置でバイアホール６Ａを通して内部電極２Ａに接続さ
れる。また、外部電極５Ａは、電流容量を満足させると
いう点では金属ワイヤ４の断面積程度の大きさの面積を
持てば良く、良導熱体８の面積よりも小さな面積でハン
ダ付けに支障がない程度に小さくすることにより、良導
熱体８の面積を大きくすることが可能である。Here, in order to simplify the manufacturing process, when the good heat conducting body 8 is made of the same metal material as the external electrodes 5A and 5B, the good heat conducting body 8 is formed so as not to contact the external electrodes 5A and 5B. And internal electrodes 2 through via holes.
It is not connected to any electrode such as A. The position where the good heat conductor 8 is formed on the other surface of the electrical insulating substrate 1 is as follows.
It is preferable in terms of heat radiation that the surface area including the mounting position of the semiconductor element 3 be as large as allowable. On the other hand, the external electrode 5A is preferably connected to the internal electrode 2A through the via hole 6A at a position deviated from the mounting position of the semiconductor element 3. In addition, the external electrode 5A may have an area approximately equal to the cross-sectional area of the metal wire 4 in terms of satisfying the current capacity. The external electrode 5A has an area smaller than the area of the good heat conductor 8 and does not hinder soldering. It is possible to increase the area of the good heat conducting body 8 by making the heat sink smaller.

【００１６】図２をも用いてこの半導体装置を電子機器
の基板１０に搭載する例を説明すると、アルミニウム板
のような金属基板１０Ａとその上に形成された電気絶縁
膜１０Ｂとからなる大面積の基板１０の電気絶縁被膜１
０Ｂ上には、図示していない多数の各種ＩＣ、個別の回
路部品が搭載され、その他に、この半導体装置の外部電
極５Ａ、５Ｂに対応する位置に接続電極１１Ａ、１１Ｂ
が形成されると共に、良導熱体８に対応する位置に良導
熱部分９が形成されている。ここで電気絶縁被膜１０Ｂ
上の接続電極１１Ａ、１１Ｂは、後述するようにキャパ
シタンスを小さくするために、外部電極５Ａ、５Ｂの面
積と同程度以下であることが好ましいが、良導熱部分９
は良導熱体８の面積と同程度以上であることが好まし
い。良導熱体８と良導熱部分９が金属材料からなる場合
には、外部電極５Ａと接続電極１１Ａ、外部電極５Ｂと
接続電極１１Ｂ、及び良導熱体８と良導熱部分９は通常
の方法でハンダ付けされる。An example in which this semiconductor device is mounted on a substrate 10 of an electronic device will be described with reference to FIG. 2 as well. A large area composed of a metal substrate 10A such as an aluminum plate and an electric insulating film 10B formed thereon is described. Electrical insulation coating 1 on substrate 10
A large number of various ICs (not shown) and individual circuit components are mounted on the semiconductor device 0B, and the connection electrodes 11A and 11B are provided at positions corresponding to the external electrodes 5A and 5B of the semiconductor device.
Are formed, and a good heat conducting portion 9 is formed at a position corresponding to the good heat conducting body 8. Here, the electric insulating film 10B
The upper connection electrodes 11A and 11B are preferably equal to or less than the area of the external electrodes 5A and 5B in order to reduce the capacitance as described later.
Is preferably equal to or greater than the area of the good heat conductor 8. When the good heat conducting body 8 and the good heat conducting part 9 are made of a metal material, the external electrode 5A and the connecting electrode 11A, the external electrode 5B and the connecting electrode 11B, and the good heat conducting body 8 and the good heat conducting part 9 are soldered in a usual manner. Attached.

【００１７】従来例でも説明したように、電気絶縁被膜
１０Ｂを挟む金属基板１０Ａと接続電極１１Ａ間にはキ
ャパシタンスＣ１が形成され、同様に電気絶縁被膜１０
Ｂを挟む金属基板１０Ａと接続電極１１Ｂ間にもキャパ
シタンスＣ２が形成される。一般にキャパシタの容量は
電極間隔を一定とすると、電極の面積に比例するから、
キャパシタンスＣ１、Ｃ２は接続電極１１Ａ、１１Ｂの
面積に比例する。したがって、例えば外部電極５Ａと接
続電極１１Ａが方形の形状として、それぞれ従来の電極
の一辺の寸法に比べてほぼ１／３に小さくなったとする
と、それらの面積はほぼ１／９となり、容量もほぼ１／
９と小さくなる。このことから電流容量及び確実なハン
ダ付けの面から許される限り、接続電極１１Ａ、１１Ｂ
の幅と長さ、つまり面積をできる限り小さくする方が好
ましい。As described in the conventional example, the capacitance C1 is formed between the metal substrate 10A and the connection electrode 11A with the electric insulating film 10B interposed therebetween.
A capacitance C2 is also formed between the metal substrate 10A and the connection electrode 11B sandwiching B. In general, the capacitance of a capacitor is proportional to the area of an electrode when the electrode spacing is constant,
The capacitances C1 and C2 are proportional to the areas of the connection electrodes 11A and 11B. Therefore, for example, assuming that the external electrode 5A and the connection electrode 11A have a rectangular shape and are each reduced to approximately one third of the dimension of one side of the conventional electrode, their area is reduced to approximately 1/9 and the capacitance is also substantially reduced. 1 /
9 and smaller. For this reason, the connection electrodes 11A and 11B are limited as far as the current capacity and reliable soldering allow.
It is preferable to make the width and length, that is, the area, as small as possible.

【００１８】ここで、良導熱体８と良導熱部分９は製造
上手頃な金属材料を用いても、他の電極、回路パターン
には接続されていないので、良導熱体８と良導熱部分９
と金属基板１０Ａ間のキャパシタンスと、良導熱体８と
半導体素子３間のキャパシタンスとが直列接続になり、
したがって、半導体素子３と金属基板１０Ａ間のキャパ
シタンスは小さくなる。また、図示していないが、良導
熱部分９を金属材料で構成し、良導熱部分９を直流電源
電圧に比例する一定電圧、又は接地電圧に接続した場合
には、良導熱部分９の電圧レベルはほぼ一定であるの
で、前述のように１／２・ＣＶ2 ｆで表される損失は、
半導体装置の駆動周波数が数百ｋＨｚを超える高周波で
あっても、十分に小さい値に抑制できる。通常、良導熱
部分９も金属板１０も使用時には接地電位に保持される
ので、それらの間のキャパシタンスは実質的にゼロであ
り、この場合には良導熱体８は導電性を有しても有さな
くとも良い。Here, the good heat conducting body 8 and the good heat conducting part 9 are not connected to other electrodes and circuit patterns even if a good metal material is used for the manufacture, so that the good heat conducting body 8 and the good heat conducting part 9 are used.
And the capacitance between the metal substrate 10A and the capacitance between the good heat conductor 8 and the semiconductor element 3 are connected in series,
Therefore, the capacitance between the semiconductor element 3 and the metal substrate 10A decreases. Although not shown, when the good heat conducting portion 9 is made of a metal material and the good heat conducting portion 9 is connected to a constant voltage proportional to the DC power supply voltage or to a ground voltage, the voltage level of the good heat conducting portion 9 is increased. Is almost constant, the loss expressed by 1/2 · CV2 f is as described above.
Even when the driving frequency of the semiconductor device is a high frequency exceeding several hundred kHz, it can be suppressed to a sufficiently small value. Normally, since both the good heat conducting portion 9 and the metal plate 10 are kept at the ground potential when used, the capacitance between them is substantially zero. In this case, even if the good heat conducting body 8 has conductivity, It is not necessary to have.

【００１９】次に樹脂封止について簡単に述べておく。
この封止樹脂７としてはエポキシ樹脂、フェノ−ル樹
脂、ポリエステル樹脂、などの電気絶縁性樹脂が適して
いる。加熱により徐々に硬化する組成の熱硬化性樹脂も
用いることができ、硬化剤、触媒としては酸無水物、フ
ェノ−ル樹脂、芳香族アミン、イミダゾ−ルなどが使用
できる。また顔料、充填剤、添加剤も特性保持のために
使用できる。充填剤は石英粉、アルミナなどが使用で
き、一般に６０% 程度以上含有するものが良い。電気絶
縁基板１との密着性、離型性、流れ性、低温硬化性、脱
泡性、低チクソ性などの作業性を良くすること、低膨
脹、含有不純物イオンの低いこと、またエッチング液に
侵されないことなども要求される。熱可塑性樹脂として
はＰＰＯや液晶ポリマ−が使用できるが、溶融させて注
入することが必要である。このような封止樹脂を用い
て、フラットな上面に格子状に切れ目の入った封止樹脂
の成型物は、特開平６ー６１４１７号公報に記載された
方法などで作成できる。そのような方法で作成された封
止樹脂成型物を分割することによりこの半導体装置が得
られる。Next, the resin sealing will be briefly described.
As the sealing resin 7, an electrically insulating resin such as an epoxy resin, a phenol resin, and a polyester resin is suitable. A thermosetting resin having a composition which is gradually cured by heating can also be used, and as a curing agent and a catalyst, an acid anhydride, a phenol resin, an aromatic amine, imidazole and the like can be used. Pigments, fillers, and additives can also be used to maintain properties. As the filler, quartz powder, alumina or the like can be used, and it is generally preferable that the filler contains about 60% or more. To improve the workability such as adhesion to the electrical insulating substrate 1, release property, flowability, low-temperature curing property, defoaming property, low thixotropy, low expansion, low content of impurity ions, and It is also required not to be invaded. As the thermoplastic resin, PPO or liquid crystal polymer can be used, but it is necessary to melt and inject. Using such a sealing resin, a molded product of the sealing resin having a flat upper surface with cuts in a lattice shape can be prepared by a method described in JP-A-6-61417. This semiconductor device is obtained by dividing the sealing resin molded product created by such a method.

【００２０】次に、図３により４個のダイオードを全波
整流構成に結合してなる半導体装置の一例について説明
を行う。電気絶縁基板１の一方の主面には、内部電極２
Ａ、２ａ、２Ｂ、２ｂが形成され、内部電極２Ａには半
導体素子としてのダイオードのベアチップ３Ａ、３Ｂの
アノード側がハンダ付けされ、内部電極２Ｂにはダイオ
ードのベアチップ３ａ、３ｂのカソード側がハンダ付け
される。ベアチップ３Ａのカソードとベアチップ３ａの
アノードが金属ワイヤ４Ａによりワイヤボンディングさ
れると共に、金属ワイヤ４ａにより内部電極２ｂにボン
ディングされる。また同様に、ベアチップ３Ｂのカソー
ドとベアチップ３ｂのアノードが金属ワイヤ４Ｂにより
ワイヤボンディングされると共に、金属ワイヤ４ｂによ
り内部電極２Ｂにボンディングされる。そして内部電極
２ａは図３の右端側で、バイアホール６ｂにより外部電
極５ｂに接続される。外部電極５ｂはカソード端子とな
る。内部電極２ｂはバイアホール６ａにより、交流入力
端子の役割を行う外部電極５ａに接続される。また図示
していないが、内部電極２Ａは図３の左側でバイアホー
ルによりアノード端子として作用する外部電極に接続さ
れ、内部電極２Ｂはバイアホールにより、他方の交流入
力端子の役割を行う外部電極に接続される。ベアチップ
である半導体素子３Ａ、３Ｂ、３ａ、３ｂを含む面域に
対応する面域に良熱導体８が形成されており、従来の構
造に比べて放熱効果を低下させることなくキャパシタン
スを大幅に低減できる。Next, an example of a semiconductor device in which four diodes are combined in a full-wave rectification configuration will be described with reference to FIG. An internal electrode 2 is provided on one main surface of the electrically insulating substrate 1.
A, 2a, 2B, and 2b are formed, the anode side of the diode bare chip 3A, 3B as a semiconductor element is soldered to the internal electrode 2A, and the cathode side of the diode bare chip 3a, 3b is soldered to the internal electrode 2B. You. The cathode of the bare chip 3A and the anode of the bare chip 3a are wire-bonded by the metal wire 4A and also bonded to the internal electrode 2b by the metal wire 4a. Similarly, the cathode of the bare chip 3B and the anode of the bare chip 3b are wire-bonded by the metal wire 4B, and are also bonded to the internal electrode 2B by the metal wire 4b. The internal electrode 2a is connected to the external electrode 5b by a via hole 6b on the right end side in FIG. The external electrode 5b serves as a cathode terminal. The internal electrode 2b is connected via a via hole 6a to an external electrode 5a serving as an AC input terminal. Although not shown, the internal electrode 2A is connected to an external electrode acting as an anode terminal via a via hole on the left side of FIG. 3, and the internal electrode 2B is connected to an external electrode serving as the other AC input terminal via the via hole. Connected. The good heat conductor 8 is formed in a surface area corresponding to the surface area including the semiconductor elements 3A, 3B, 3a, 3b which are bare chips, and the capacitance is greatly reduced without lowering the heat radiation effect as compared with the conventional structure. it can.

【００２１】次に、図４によりＭＯＳＦＥＴのベアチッ
プを樹脂封止してなる半導体装置の一例について説明を
行う。電気絶縁基板１の一方の主面には、内部電極２Ａ
〜２Ｃが形成される。内部電極２Ａには半導体素子とし
てのＭＯＳＦＥＴのベアチップ３Ａのドレイン電極がハ
ンダ付けされる。ベアチップ３Ａのソース電極は複数の
金属ワイヤ４Ａにより内部電極２Ｂにワイヤボンディン
グされる。また、ＭＯＳＦＥＴのベアチップ３Ａのゲー
ト電極は金属ワイヤ４Ｂにより内部電極２Ｃにボンディ
ングされる。そして内部電極２Ａは図４の右端側で、バ
イアホール６Ａにより外部電極５Ａに接続される。外部
電極５Ａはドレイン端子の役割を果たす。内部電極２Ｃ
はバイアホール６Ｂにより、ゲート端子の役割を行う外
部電極５Ｂに接続される。また図示していないが、内部
電極２Ｂは図４の左側でバイアホールによりソース端子
として作用する外部電極に接続される。電気絶縁基板１
の他方の主面には、ベアチップ３Ａを含む面域に対応す
る面域に良熱導体８が形成されており、この例でも従来
の構造に比べて放熱効果を向上させながら、前述のよう
な大面積の搭載用の基板によるキャパシタンスを大幅に
低減できる。この実施例はバイポーラトランジスタ、Ｉ
ＧＢＴ及びサイリスタなど他の制御型の半導体装置にも
全く同様に適用可能である。Next, an example of a semiconductor device in which a bare MOSFET chip is sealed with a resin will be described with reference to FIG. On one main surface of the electrically insulating substrate 1, an internal electrode 2A
~ 2C are formed. The drain electrode of the bare chip 3A of the MOSFET as a semiconductor element is soldered to the internal electrode 2A. The source electrode of the bare chip 3A is wire-bonded to the internal electrode 2B by a plurality of metal wires 4A. The gate electrode of the bare chip 3A of the MOSFET is bonded to the internal electrode 2C by the metal wire 4B. The internal electrode 2A is connected to the external electrode 5A by a via hole 6A on the right end side in FIG. The external electrode 5A functions as a drain terminal. Internal electrode 2C
Is connected to an external electrode 5B serving as a gate terminal through a via hole 6B. Although not shown, the internal electrode 2B is connected to an external electrode acting as a source terminal by a via hole on the left side of FIG. Electrically insulating substrate 1
On the other main surface, a good heat conductor 8 is formed in a surface area corresponding to the surface area including the bare chip 3A. In this example as well, while improving the heat radiation effect as compared with the conventional structure, Capacitance due to a large-area mounting substrate can be significantly reduced. This embodiment is a bipolar transistor, I
The present invention can be applied to other control-type semiconductor devices such as a GBT and a thyristor.

【００２２】次に図５（Ａ）〜（Ｃ）により、４個のト
ランジスタＴ１〜Ｔ４のベアチップである半導体素子３
Ａ〜３Ｄをブリッジ構成にすると共に、各トランジスタ
のベアチップに逆並列にダイオードＤ１〜Ｄ４のベアチ
ップである半導体素子３ａ〜３ｄを配置してなるトラン
ジスタインバータ構成の半導体装置の一例について説明
を行う。図５（Ｃ）に示されるトランジスタＴ１、Ｔ２
に相当する半導体素子３Ａ、３Ｂのコレクタ側が共通の
内部電極２Ａに固着される。トランジスタＴ３に相当す
る半導体素子３Ｃのコレクタ側が内部電極２Ｂに固着さ
れ、トランジスタＴ４に相当する半導体素子３Ｄのコレ
クタ側が内部電極２Ｃに固着される。トランジスタＴ
１、Ｔ２の近傍において、ダイオードＤ１、Ｄ２に相当
する半導体素子３ａ、３ｂのカソード側が共通の内部電
極２Ａに固着される。同様に、ダイオードＤ３、Ｄ４に
相当する半導体素子３ｃ、３ｄのカソード側がそれぞれ
内部電極２Ｂ、２Ｃに固着される。Next, referring to FIGS. 5A to 5C, the semiconductor element 3 which is a bare chip of the four transistors T1 to T4
An example of a semiconductor device having a transistor inverter configuration in which A to 3D have a bridge configuration and semiconductor elements 3a to 3d that are bare chips of diodes D1 to D4 are arranged in anti-parallel with the bare chip of each transistor will be described. The transistors T1 and T2 shown in FIG.
Are fixed to the common internal electrode 2A. The collector side of the semiconductor element 3C corresponding to the transistor T3 is fixed to the internal electrode 2B, and the collector side of the semiconductor element 3D corresponding to the transistor T4 is fixed to the internal electrode 2C. Transistor T
1, near the T2, the cathode sides of the semiconductor elements 3a, 3b corresponding to the diodes D1, D2 are fixed to the common internal electrode 2A. Similarly, the cathode sides of the semiconductor elements 3c and 3d corresponding to the diodes D3 and D4 are fixed to the internal electrodes 2B and 2C, respectively.

【００２３】半導体素子３Ａのエミッタは、複数の金属
ワイヤ４Ａにより内部電極２Ｂにボンディングされ、そ
のベースは金属ワイヤ４ａにより内部電極２ａにボンデ
ィングされる。また、ダイオードＤ１に相当する半導体
素子３ａのアノードは金属ワイヤ４Ａ’により半導体素
子３Ａのエミッタにボンディングされる。半導体素子３
Ｂのエミッタは、複数の金属ワイヤ４Ｂにより内部電極
２Ｃにボンディングされ、そのベースは金属ワイヤ４ｂ
により内部電極２ｂにボンディングされる。また、ダイ
オードＤ２に相当する半導体素子３ｂのアノードは金属
ワイヤ４Ｂ’により半導体素子３Ｂのエミッタにボンデ
ィングされる。また、半導体素子３Ｃのエミッタは、複
数の金属ワイヤ４Ｃにより内部電極２Ｂ’にボンディン
グされ、そのベースは金属ワイヤ４ｃにより内部電極２
ｃにボンディングされる。また、ダイオードＤ３に相当
する半導体素子３ｃのアノードは金属ワイヤ４Ｃ’によ
り半導体素子３Ｃのエミッタにボンディングされる。同
様に、半導体素子３Ｄのエミッタは、複数の金属ワイヤ
４Ｄにより内部電極２Ｃ’にボンディングされ、そのベ
ースは金属ワイヤ４ｄにより内部電極２ｄにボンディン
グされる。また、ダイオードＤ４に相当する半導体素子
３ｄのアノードは金属ワイヤ４Ｄ’により半導体素子３
Ｄのエミッタにボンディングされる。The emitter of the semiconductor element 3A is bonded to the internal electrode 2B by a plurality of metal wires 4A, and its base is bonded to the internal electrode 2a by a metal wire 4a. Further, the anode of the semiconductor element 3a corresponding to the diode D1 is bonded to the emitter of the semiconductor element 3A by the metal wire 4A '. Semiconductor element 3
The B emitter is bonded to the internal electrode 2C by a plurality of metal wires 4B, and its base is connected to the metal wires 4b.
Is bonded to the internal electrode 2b. Further, the anode of the semiconductor element 3b corresponding to the diode D2 is bonded to the emitter of the semiconductor element 3B by the metal wire 4B '. The emitter of the semiconductor element 3C is bonded to the internal electrode 2B 'by a plurality of metal wires 4C, and the base thereof is connected to the internal electrode 2B by the metal wire 4c.
c. Further, the anode of the semiconductor element 3c corresponding to the diode D3 is bonded to the emitter of the semiconductor element 3C by the metal wire 4C '. Similarly, the emitter of the semiconductor element 3D is bonded to the internal electrode 2C ′ by a plurality of metal wires 4D, and its base is bonded to the internal electrode 2d by a metal wire 4d. The anode of the semiconductor element 3d corresponding to the diode D4 is connected to the semiconductor element 3d by a metal wire 4D '.
Bonded to D emitter.

【００２４】内部電極２ｂはバイアホール６ｂを通して
外部電極５ｂに結合され、内部電極２Ｃ’はバイアホー
ル６Ｃ’を通して外部電極５Ｃ’に結合される。図示し
ていないが、他の内部電極２Ａ、２ａ、２Ｂ、２Ｃ、２
ｃ、２Ｂ’、２ｄについても同様に、それぞれのバイア
ホールを通して対応する外部電極に結合される。ここで
図５（Ｃ）に示される正の直流端子ｔ１は、図示されて
いないが、内部電極２Ａの突出部分２Ａ１にバイアホー
ルを通して結合される外部電極に相当し、同様に端子ｔ
２は内部電極２ａに結合される外部電極、端子ｔ３は内
部電極２ｂに結合される外部電極５ｂ、交流端子ｔ４、
ｔ５はそれぞれ内部電極２Ｂ、２Ｃの突出部分２Ｂ１、
２Ｃ１に結合される外部電極、端子ｔ６は内部電極２ｃ
に結合される外部電極、端子ｔ７は内部電極２ｄに結合
される外部電極、及び負の直流端子ｔ８はそれぞれ内部
電極２Ｂ’、２Ｃ’に結合される外部電極に相当する。
したがって、この実施例においても、内部電極２Ａ〜２
Ｃの突出部分を除いたそれらの外郭線に対応する面域に
良導熱体８を備えることができ、それほど放熱を低下さ
せずにキャパシタンスを低減することができる。The internal electrode 2b is connected to the external electrode 5b through the via hole 6b, and the internal electrode 2C 'is connected to the external electrode 5C' through the via hole 6C '. Although not shown, other internal electrodes 2A, 2a, 2B, 2C, 2
Similarly, c, 2B 'and 2d are coupled to the corresponding external electrodes through the respective via holes. Although not shown, the positive DC terminal t1 shown in FIG. 5C corresponds to an external electrode coupled to the protruding portion 2A1 of the internal electrode 2A through a via hole.
2 is an external electrode coupled to the internal electrode 2a, terminal t3 is an external electrode 5b coupled to the internal electrode 2b, an AC terminal t4,
t5 is a protruding portion 2B1 of each of the internal electrodes 2B and 2C,
The external electrode coupled to 2C1 and the terminal t6 are connected to the internal electrode 2c.
The terminal t7 corresponds to an external electrode coupled to the internal electrode 2d, and the negative DC terminal t8 corresponds to an external electrode coupled to the internal electrodes 2B 'and 2C', respectively.
Therefore, also in this embodiment, the internal electrodes 2A to 2A
The good heat conductor 8 can be provided in a surface area corresponding to those outlines excluding the protruding portion of C, and the capacitance can be reduced without significantly reducing heat radiation.

【００２５】次に図６によりハイブリッドＩＣのような
電子回路装置を金属基板１０に搭載した一実施例につい
て説明する。電気絶縁基板１はアルミニウムのような金
属板１Ａを電気絶縁被膜１Ｂで覆ったものからなり、そ
の一方の面には複数の内部電極２Ａと２Ｂ、電力制御用
半導体素子３Ａと比較的発熱の大きい他の回路部品３Ｂ
がそれぞれ搭載される搭載部分２Ｘ、２Ｙ及びこれらの
所定のものを接続する配線（図示せず）とからなる回路
パターンが形成されている。内部電極２Ａ、２Ｂは、例
えば、それぞれ入力電極と出力電極であり、また図示し
ていないが、内部電極２Ａ、２Ｂと同様に、電気絶縁基
板１の周りには制御信号の印加される制御電極、検出信
号が現出する検出電極など他の内部電極が備えられる。
そして内部電極２Ａ、２Ｂを含むこれら内部電極はそれ
ぞれバイアホール６Ａ、６Ｂなどを通して外部電極５
Ａ、５Ｂなど対応する外部電極に接続される。なお、回
路部品の搭載部分２Ｘ、２Ｙなど搭載部分は電気絶縁被
膜１Ｂ上に形成された配線、あるいは金属ワイヤ（図示
せず）により内部電極又は他の回路素子などに接続され
ている。Next, an embodiment in which an electronic circuit device such as a hybrid IC is mounted on a metal substrate 10 will be described with reference to FIG. The electric insulating substrate 1 is formed by covering a metal plate 1A such as aluminum with an electric insulating film 1B, and has a plurality of internal electrodes 2A and 2B, a power control semiconductor element 3A and relatively large heat generation on one surface. Other circuit components 3B
Are formed, and a circuit pattern is formed of mounting portions 2X and 2Y on which are mounted, respectively, and wiring (not shown) connecting these predetermined portions. The internal electrodes 2A and 2B are, for example, an input electrode and an output electrode, respectively. Although not shown, similar to the internal electrodes 2A and 2B, control electrodes to which a control signal is applied around the electrically insulating substrate 1 are provided. And other internal electrodes such as a detection electrode on which a detection signal appears.
These internal electrodes including the internal electrodes 2A and 2B are connected to the external electrodes 5 through via holes 6A and 6B, respectively.
A, 5B, etc. are connected to corresponding external electrodes. The mounting parts such as the mounting parts 2X and 2Y of the circuit components are connected to the internal electrodes or other circuit elements by wiring formed on the electric insulating film 1B or metal wires (not shown).

【００２６】また、搭載された電力制御用半導体素子３
Ａ、回路部品３Ｂなどのそれぞれのベアチップの他の電
極は通常、ワイヤボンディングにより回路構成上の他の
所定箇所に接続される。しかし、ベアチップの一面にす
べての電極が位置する構造の回路素子を用いれば、ワイ
ヤボンディング用の金属ワイヤを省略できる。そして良
導熱体８は、電力制御用半導体素子３Ａ、比較的発熱の
大きい他の回路部品３Ｂの搭載部分２Ｘ、２Ｙを含む面
域に対応する面域に形成される。そしてこの電子回路装
置は図２で述べたようにして、ＩＣのような他の回路部
品と共に電子機器の大面積の基板１０に搭載される。そ
の大面積の基板１０には前にも述べた通り、良導熱体８
に対応する面域にその面積とほぼ同一、あるいはこれよ
りも大きい面積を持つ良導熱部分９、及び電子回路装置
の外部電極５Ａ、５Ｂに対応する位置にその面積とほぼ
等しい面積の接続電極１１Ａ、１１Ｂが回路パターンの
一部分として形成されている。図示していないが、この
他にも電子回路装置の他の外部電極に対応する接続電極
が形成されている。The mounted power control semiconductor element 3
A, and other electrodes of each bare chip such as the circuit component 3B are usually connected to other predetermined locations on the circuit configuration by wire bonding. However, if a circuit element having a structure in which all electrodes are located on one surface of a bare chip is used, metal wires for wire bonding can be omitted. The good heat conductor 8 is formed in a surface area corresponding to a surface area including the mounting portions 2X and 2Y of the power control semiconductor element 3A and the other circuit components 3B that generate relatively large heat. This electronic circuit device is mounted on a large-area substrate 10 of an electronic device together with other circuit components such as an IC as described in FIG. As described above, the large-area substrate 10 has a good heat conducting body 8.
, A good heat conducting portion 9 having an area substantially equal to or larger than the area thereof, and a connection electrode 11A having an area substantially equal to the area at a position corresponding to the external electrodes 5A, 5B of the electronic circuit device. , 11B are formed as part of the circuit pattern. Although not shown, other connection electrodes corresponding to other external electrodes of the electronic circuit device are formed.

【００２７】なお、以上の例では半導体素子が単体、あ
るいは同様な半導体素子を複数用いた複合的な半導体装
置について述べたが、トランジスタやサイリスタのよう
な制御型の半導体素子とダイオード、又は抵抗、セラミ
ックコンデンサなどを組み合わせた半導体装置も同様に
して製作できる。例えば、ダーリントン接続タイプのト
ランジスタの場合、主トラジスタと増幅用トランジスタ
のコレクタ電極が第１の内部電極に搭載されてろう付け
され、主トラジスタのエミッタ電極を第２の内部電極に
ワイヤボンディングし、増幅用トランジスタのベース電
極が第３の内部電極にワイヤボンディングされ、そして
主トラジスタのベース電極と増幅用トランジスタのエミ
ッタ電極がワイヤボンデングされるか、又はこれらが第
４の内部電極にそれぞれワイヤボンデングされれば、ダ
ーリントン接続タイプの面実装型トランジスタを得るこ
とができる。また、制御型の半導体素子とこの両端に接
続されたスナバ回路、制御型の半導体素子とこの制御端
子と一方の主電極間に接続された駆動回路又はその一部
分の回路素子など、種々のバリエーションも前述と同様
にして得られる。また、以上のいずれの実施例でも説明
を省略したが、樹脂封止前に半導体素子をインナーコー
トが行われるのは当然である。また、以上の実施例では
バイアホールによって内部電極と外部電極を接続した
が、一般的に知られている方法で内部電極又は外部電極
を電気絶縁基板の側面まで延ばした形で形成された金属
膜により、内部電極と外部電極とを接続しても勿論良
い。In the above example, a single semiconductor element or a composite semiconductor device using a plurality of similar semiconductor elements has been described. However, a control type semiconductor element such as a transistor or a thyristor and a diode, or a resistor, A semiconductor device combining a ceramic capacitor and the like can be manufactured in a similar manner. For example, in the case of a Darlington connection type transistor, the main transistor and the collector electrode of the amplifying transistor are mounted on the first internal electrode and brazed, and the emitter electrode of the main transistor is wire-bonded to the second internal electrode to amplify the transistor. The base electrode of the amplifying transistor is wire-bonded to the third internal electrode, and the base electrode of the main transistor and the emitter electrode of the amplifying transistor are wire-bonded, or they are wire-bonded to the fourth internal electrode, respectively. Then, a Darlington connection type surface mount transistor can be obtained. There are also various variations such as a control type semiconductor element and a snubber circuit connected to both ends thereof, a control type semiconductor element and a drive circuit connected between the control terminal and one main electrode or a part of the circuit element. Obtained in the same manner as described above. Although the description has been omitted in any of the above embodiments, it is natural that the semiconductor element is subjected to the inner coating before the resin sealing. In the above embodiment, the internal electrode and the external electrode are connected by the via hole. However, a metal film formed by extending the internal electrode or the external electrode to the side surface of the electrically insulating substrate by a generally known method. Accordingly, the internal electrode and the external electrode may be connected.

【０００２８】[00028]

【発明の効果】以上述べたように、この発明によれば、
前記表面実装型の半導体装置又は電子回路装置が前記
電気絶縁基板の他方の主面上に前記外部電極から分離さ
れて形成された良導熱体を備えると共に、前記金属基板
が前記電気絶縁被膜の上に回路パターンの一分として形
成された接続電極の他に該接続電極に接続されていない
良導熱部分を備え、前記外部電極を前記接続電極に接続
し、かつ前記良導熱体を前記良導熱部に結合しているの
で、放熱を低下させることなく、前記金属基板と前記外
部電極間に形成されるキャパシタンスを小さくすること
ができ、また、良導熱体を金属材料で形成し、固定電位
に接続することにより、更に一層前記キャパシタンスに
よる損失を低減することができる。ている。As described above, according to the present invention,
The surface-mount type semiconductor device or the electronic circuit device includes a good heat conductor formed separately from the external electrode on the other main surface of the electrical insulating substrate, and the metal substrate is provided on the electrical insulating coating. A good heat conducting portion not connected to the connection electrode in addition to the connection electrode formed as a part of the circuit pattern, connecting the external electrode to the connection electrode, and connecting the good heat conducting body to the good heat conducting portion. , The capacitance formed between the metal substrate and the external electrode can be reduced without lowering the heat radiation, and a good heat conductor is formed of a metal material and connected to a fixed potential. By doing so, the loss due to the capacitance can be further reduced. ing.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 この発明にかかる電子機器に用いるのに適し
た半導体装置の一例を示す図である。FIG. 1 is a diagram illustrating an example of a semiconductor device suitable for use in an electronic device according to the present invention.

【図２】 この発明にかかる電子機器の一実施例を示す
図である。FIG. 2 is a diagram showing one embodiment of an electronic device according to the present invention.

【図３】 この発明にかかる電子機器に用いるのに適し
た他の半導体装置の一例を示す図である。FIG. 3 is a diagram showing an example of another semiconductor device suitable for use in an electronic device according to the present invention.

【図４】 この発明にかかる電子機器に用いるのに適し
た他の半導体装置の一例を示す図である。FIG. 4 is a diagram showing an example of another semiconductor device suitable for use in an electronic device according to the present invention.

【図５】 この発明にかかる電子機器に用いるのに適し
た他の半導体装置の一例を示す図である。FIG. 5 is a diagram showing an example of another semiconductor device suitable for use in an electronic device according to the present invention.

【図６】 この発明にかかる電子機器の他の一実施例を
示す図である。示す図である。FIG. 6 is a diagram showing another embodiment of the electronic apparatus according to the present invention. FIG.

【図７】 従来の表面実装型の半導体装置の１例を示す
図である。FIG. 7 is a diagram showing an example of a conventional surface-mount type semiconductor device.

【図８】 従来の表面実装型の半導体装置を電子機器の
金属基板に搭載した１例を示す図である。FIG. 8 is a diagram showing an example in which a conventional surface mount semiconductor device is mounted on a metal substrate of an electronic device.

【符号の説明】[Explanation of symbols]

１・・・電気絶縁基板 ２・・・内部電極 ３・・・半導体素子 ４・・・金属ワイ
ヤ ５・・・外部電極 ６・・・バイアホ
ール ７・・・封止樹脂 ８・・・良導熱体 ９・・・良導熱部分 １０・・・大面積の
基板 １０Ａ・・金属基板 １０Ｂ・・電気絶
縁被膜 １１・・・接続電極 Ｃ１、Ｃ２・・・
キャパシタンスDESCRIPTION OF SYMBOLS 1 ... Electrical insulating substrate 2 ... Internal electrode 3 ... Semiconductor element 4 ... Metal wire 5 ... External electrode 6 ... Via hole 7 ... Sealing resin 8 ... Good heat conduction Body 9: good heat conducting portion 10: large-area substrate 10A: metal substrate 10B: electric insulating film 11: connecting electrodes C1, C2 ...
capacitance

フロントページの続き (56)参考文献 特開 平１−204454（ＪＰ，Ａ) 特開 昭60−95944（ＪＰ，Ａ) 特開 昭61−34989（ＪＰ，Ａ) 特開 平５−152507（ＪＰ，Ａ) 特開 平４−109690（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 25/00 - 25/18 Continuation of front page (56) References JP-A-1-204454 (JP, A) JP-A-60-95944 (JP, A) JP-A-61-34989 (JP, A) JP-A-5-152507 (JP) , A) JP-A-4-109690 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 25/00-25/18

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 電気絶縁基板の一方の主面上に互いに離
れて形成された複数の内部電極と、該内部電極に主電極
が接続された半導体素子と、該半導体素子と前記内部電
極と前記電気絶縁基板の一方の主面とを覆う封止樹脂
と、前記電気絶縁基板の他方の主面上に互いに離れて形
成された複数の外部電極と、対応する前記内部電極と外
部電極との間を接続するため前記電気絶縁基板の両主面
間に形成された電気接続体とを備えた表面実装型の半導
体装置又は電子回路装置を、表面が電気絶縁被膜で覆わ
れた金属基板の上に搭載してなる電子機器において、 前記表面実装型の半導体装置又は電子回路装置は、前記
電気絶縁基板の他方の主面上に前記外部電極から分離さ
れて形成された良導熱体を備え、 前記金属基板は、前記電気絶縁被膜の上に回路パターン
の一分として形成された接続電極と、該接続電極に接続
されていない良導熱部分とを備え、 前記外部電極を前記接続電極に接続すると共に、前記良
導熱体を前記良導熱部分に結合したことを特徴とする電
子機器。A plurality of internal electrodes formed apart from each other on one main surface of an electrically insulating substrate; a semiconductor element having a main electrode connected to the internal electrodes; A sealing resin covering one main surface of the electric insulating substrate, a plurality of external electrodes formed apart from each other on the other main surface of the electric insulating substrate, and a corresponding one of the internal electrodes and the external electrodes. A surface-mounted semiconductor device or an electronic circuit device having an electrical connector formed between both main surfaces of the electrical insulating substrate, on a metal substrate whose surface is covered with an electrical insulating film. In the electronic device to be mounted, the surface-mount type semiconductor device or the electronic circuit device includes a good heat conductor formed separately from the external electrode on the other main surface of the electrical insulating substrate; The substrate is wrapped over the electrical insulation coating. A connection electrode formed as a part of the pattern, and a good heat conducting portion not connected to the connection electrode, wherein the external electrode is connected to the connection electrode, and the good heat conducting body is coupled to the good heat conducting portion. Electronic equipment characterized by the following. 【請求項２】 前記外部電極が前記良導熱体の面積より
も小さな面積を有することを特徴とする請求項１に記載
の電子機器。2. The electronic device according to claim 1, wherein the external electrode has an area smaller than an area of the good heat conductor. 【請求項３】 前記良導熱体が前記外部電極の厚みとほ
ぼ等しい金属板又は金属膜であることを特徴とする請求
項１又は請求項２に記載の電子機器。3. The electronic device according to claim 1, wherein the good heat conductor is a metal plate or a metal film substantially equal in thickness to the external electrode. 【請求項４】 前記良導熱体が前記半導体素子又は電力
制御用半導体素子に対応する部分を含む面域に形成され
ることを特徴とする請求項１乃至請求項３のいずれかに
記載の電子機器。4. The electron according to claim 1, wherein the good heat conductor is formed in a surface area including a portion corresponding to the semiconductor element or the power control semiconductor element. machine. 【請求項５】 前記良導熱部分が接地端子に接続される
ことを特徴とする請求項１乃至請求項４のいずれかに記
載の電子機器。5. The electronic device according to claim 1, wherein the good heat conducting portion is connected to a ground terminal.
JP14845994A 1994-06-07 1994-06-07 Electronics Expired - Lifetime JP3308713B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14845994A JP3308713B2 (en) 1994-06-07 1994-06-07 Electronics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14845994A JP3308713B2 (en) 1994-06-07 1994-06-07 Electronics

Publications (2)

Publication Number Publication Date
JPH07335823A JPH07335823A (en) 1995-12-22
JP3308713B2 true JP3308713B2 (en) 2002-07-29

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004087882A (en) * 2002-08-28 2004-03-18 Sanyo Electric Co Ltd Semiconductor device
JP4613077B2 (en) 2005-02-28 2011-01-12 株式会社オクテック Semiconductor device, electrode member, and method for manufacturing electrode member
JP5004837B2 (en) * 2007-03-20 2012-08-22 京セラ株式会社 Structure and electronic device
KR100955076B1 (en) * 2008-07-07 2010-04-28 한국기계연구원 A thin film electro Luminance lighting element and manufacturing method thereof
DE112010002822T5 (en) 2009-07-03 2012-06-14 Seoul Semiconductor Co., Ltd. HOUSING FOR LIGHT EMITTING DIODES
KR101645009B1 (en) * 2010-01-06 2016-08-03 서울반도체 주식회사 Led package with heat radiation substrate

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