JP3263476B2 - Solid-state imaging device - Google Patents
Solid-state imaging deviceInfo
- Publication number
- JP3263476B2 JP3263476B2 JP10104493A JP10104493A JP3263476B2 JP 3263476 B2 JP3263476 B2 JP 3263476B2 JP 10104493 A JP10104493 A JP 10104493A JP 10104493 A JP10104493 A JP 10104493A JP 3263476 B2 JP3263476 B2 JP 3263476B2
- Authority
- JP
- Japan
- Prior art keywords
- transfer
- region
- semiconductor layer
- semiconductor substrate
- transfer electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、撮像部に発生する情報
電荷を撮像部に隣接する蓄積部に一旦転送して蓄積する
固体撮像素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for temporarily transferring information charges generated in an image pickup section to a storage section adjacent to the image pickup section for storage.
【０００２】[0002]
【従来の技術】フレームトランスファ型の固体撮像素子
において、被写体からの光を受ける撮像部は、照射され
た光に応答して発生する情報電荷を蓄積すると同時に、
所定の期間蓄積した情報電荷を蓄積部へ転送出力する構
成となっている。このため、撮像部にも蓄積部と同様に
情報電荷を転送駆動するための転送電極が設けられる。2. Description of the Related Art In a frame transfer type solid-state image pickup device, an image pickup section which receives light from a subject accumulates information charges generated in response to irradiated light,
The information charges accumulated for a predetermined period are transferred and output to an accumulation unit. For this reason, a transfer electrode for transferring and driving information charges is provided in the image pickup unit as in the storage unit.
【０００３】図４は、フレームトランスファ型の固体撮
像素子の概略を示す平面図である。撮像部１は、垂直方
向に連続する複数のＣＣＤシフトレジスタからなり、入
射する光の量に応じて発生する情報電荷を受光期間に各
受光画素に蓄積し、その情報電荷を転送期間に垂直転送
クロックφVに従って転送出力する。蓄積部２は、撮像
部１のシフトレジスタに連続するＣＣＤシフトレジスタ
からなり、蓄積転送クロックφSを受けて転送期間に撮
像部１から出力される情報電荷を取り込んで蓄積する。
水平転送部３は、水平方向に連続する１列のＣＣＤシフ
トレジスタ（場合によっては２列以上となる）で構成さ
れ、各ビットに蓄積部２のシフトレジスタの出力を受
け、水平転送クロックφHに従って情報電荷を水平ライ
ン単位で出力する。出力部４は、電荷量を電圧値に変換
するフローティングディフュージョン（電気的に独立し
た拡散領域）及びそのフローティングディフュージョン
の電位変動を取り出すアンプを備え、水平転送部４から
１ビット単位で出力される情報電荷を逐次電圧値に変換
し、映像信号として出力する。FIG. 4 is a plan view schematically showing a frame transfer type solid-state imaging device. The imaging section 1 is composed of a plurality of CCD shift registers that are continuous in the vertical direction, accumulates information charges generated according to the amount of incident light in each light receiving pixel during a light receiving period, and vertically transfers the information charges during a transfer period. Transfer and output according to clock φV. The accumulation unit 2 is composed of a CCD shift register that is continuous with the shift register of the imaging unit 1, receives the accumulation transfer clock φS, takes in information charges output from the imaging unit 1 during a transfer period, and accumulates the information charges.
The horizontal transfer unit 3 is composed of one row of CCD shift registers (in some cases, two or more rows) that are continuous in the horizontal direction, receives the output of the shift register of the storage unit 2 for each bit, and according to the horizontal transfer clock φH. Information charges are output in units of horizontal lines. The output unit 4 includes a floating diffusion (electrically independent diffusion region) for converting a charge amount into a voltage value and an amplifier for extracting a potential variation of the floating diffusion, and information output from the horizontal transfer unit 4 in 1-bit units. The charges are sequentially converted to voltage values and output as video signals.
【０００４】図５は、固体撮像素子の撮像部１と蓄積部
２との接続部分の構造を示す平面図で、図６は、そのＸ
−Ｘ線の断面図である。この図面では、過剰な電荷を基
板側に吸収させる縦型オーバーフロードレイン構造のも
のを示している。Ｎ型のシリコン基板１０の一面には、
撮像部１では過剰な情報電荷をシリコン基板１０に吸収
させると共に、蓄積部２ではシリコン基板１０への情報
電荷の流出を防止するように、蓄積部２で撮像部１より
も高濃度となるＰ型の拡散層１１が形成される。この拡
散層１１内には、高濃度のＰ型領域や厚い酸化膜（ＬＯ
ＣＯＳ）等からなる複数の分離領域１２を隔てて複数の
チャネル領域１３が互いに平行となるように形成され
る。これらのチャネル領域１３には、基板表面部分にＮ
型の埋め込み層１４が形成され、埋め込みチャネル構造
が構成される。そして、絶縁膜１５を介して１層目の転
送電極１６がチャネル領域１３と交差するようにして互
いに平行に配列され、さらに２層目の転送電極１７が１
層目の転送電極１６の間隙を覆うようにして配列され
る。これらの転送電極１６、１７には、撮像部１で垂直
転送クロックφV1〜φV4、蓄積部で蓄積転送クロックφ
S1〜φS4がそれぞれ印加され、シリコン基板１０内の情
報電荷がチャネル領域１３に沿って撮像部１から蓄積部
２側へ転送される。垂直転送クロックφV1〜φV4と蓄積
転送クロックφS1〜φS4とは、情報電荷の転送期間に同
一クロックとなり、撮像部１から転送出力される情報電
荷を順次蓄積部２へ取り込むようにしている。FIG. 5 is a plan view showing a structure of a connection portion between an image pickup section 1 and a storage section 2 of the solid-state image pickup device. FIG.
It is sectional drawing of the -X line. This drawing shows a vertical overflow drain structure in which excess charge is absorbed by the substrate. On one surface of the N-type silicon substrate 10,
In the imaging unit 1, the excess concentration of the information charges is absorbed by the silicon substrate 10, and the accumulation unit 2 has a P concentration higher than that of the imaging unit 1 in the accumulation unit 2 so as to prevent the outflow of the information charges to the silicon substrate 10. A mold diffusion layer 11 is formed. In the diffusion layer 11, a high-concentration P-type region or a thick oxide film (LO
A plurality of channel regions 13 are formed so as to be parallel to each other with a plurality of separation regions 12 made of COS) or the like interposed therebetween. These channel regions 13 have N
A buried layer 14 is formed to form a buried channel structure. The transfer electrodes 16 of the first layer are arranged in parallel with each other so as to intersect with the channel region 13 with the insulating film 15 interposed therebetween.
They are arranged so as to cover the gap between the transfer electrodes 16 of the layer. The transfer electrodes 16 and 17 have vertical transfer clocks φ V1 to φ V4 in the imaging unit 1 and a storage transfer clock φ in the storage unit.
S1 to [phi] S4 are applied respectively, information charges in the silicon substrate 10 is transferred from the imaging section 1 along the channel region 13 to the storage section 2 side. The vertical transfer clocks φ V1 to φ V4 and the storage transfer clocks φ S1 to φ S4 become the same clock during the transfer period of the information charges, and the information charges transferred from the imaging unit 1 are sequentially taken into the storage unit 2. I have.
【０００５】[0005]
【発明が解決しようとする課題】ところで、チャネル領
域１３のポテンシャルは、Ｐ型の拡散層１１の不純物濃
度が高くなるほど深く形成されにくくなるため、蓄積部
２では、図７に示すように、撮像部１と比較して浅く形
成されることになる。この場合、撮像部１と蓄積部２と
の境界部分で撮像部１側のポテンシャルが、蓄積部２側
のポテンシャルの影響で浅くなり、撮像部１の出力端部
で転送能力が低下することになる。このため、撮像部１
と蓄積部２とで転送電極１６、１７に異なる電位を印加
する、具体的には、蓄積転送クロックφS1〜φS4の電位
を垂直転送クロックφV1〜φV4の電位より高く設定して
それぞれの転送能力を同等にする等の対策が必要とな
る。この場合には、各転送電極１６、１７に与えられる
転送クロックが複雑になり、駆動回路の回路構成の増大
によるコストアップが問題となる。Since the potential of the channel region 13 is less likely to be formed deeper as the impurity concentration of the P-type diffusion layer 11 becomes higher, the potential of the channel region 13 is reduced as shown in FIG. It is formed shallower than the part 1. In this case, the potential of the imaging unit 1 at the boundary between the imaging unit 1 and the storage unit 2 becomes shallow due to the influence of the potential of the storage unit 2, and the transfer capability at the output end of the imaging unit 1 decreases. Become. For this reason, the imaging unit 1
A different potential is applied to the transfer electrodes 16 and 17 in the storage unit 2 and, more specifically, the potentials of the storage transfer clocks φS1 to φS4 are set higher than the potentials of the vertical transfer clocks φV1 to φV4 to increase their transfer capabilities. It is necessary to take measures such as making them equal. In this case, the transfer clock applied to each of the transfer electrodes 16 and 17 becomes complicated, and there is a problem of an increase in cost due to an increase in the circuit configuration of the drive circuit.
【０００６】また、微細化によって転送電極１６、１７
が細くなると、拡散層１１と転送電極１６、１７との間
で僅かな位置ずれが生じても、撮像部１から蓄積部２へ
の情報電荷の受け渡しに大きな影響を及ぼすことにな
り、不純物濃度の差による影響と併せて、転送効率の劣
化の原因となっている。そこで本発明は、濃度の異なる
拡散層に連続して設けられるチャネル領域内を円滑に情
報電荷を転送できるようにすることを目的とする。Further, the transfer electrodes 16 and 17 are reduced by miniaturization.
When the thickness becomes smaller, even if a slight displacement occurs between the diffusion layer 11 and the transfer electrodes 16 and 17, the transfer of information charges from the imaging unit 1 to the storage unit 2 is greatly affected, and the impurity concentration is reduced. In addition to the effect of the difference, the transfer efficiency is degraded. Therefore, an object of the present invention is to enable information charges to be smoothly transferred in a channel region provided continuously to diffusion layers having different concentrations.
【０００７】[0007]
【課題を解決するための手段】本発明は、上述の課題を
解決するために成されたもので、一導電型の半導体基板
と、この半導体基板の表面領域に設けられる逆導電型の
第１の半導体層と、上記半導体基板の表面領域で上記第
１の半導体層に接して設けられ、上記第１の半導体層と
は不純物濃度の異なる逆導電型の第２の半導体層と、上
記第１の半導体層から上記第２の半導体層まで連続し、
分離領域を隔てて互いに平行に配列される複数のチャネ
ル領域と、このチャネル領域と交差して上記第１及び第
２の半導体層上に互いに平行に配列される複数の転送電
極と、を備えた固体撮像素子であって、複数の上記転送
電極のうち、少なくとも、上記第１の半導体層と上記第
２の半導体層との境界領域に隣接する２本が、他の転送
電極と比較して上記チャネル領域の延在する方向に広く
形成されることを特徴とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and comprises a semiconductor substrate of one conductivity type and a first conductivity type semiconductor substrate provided in a surface region of the semiconductor substrate. A second semiconductor layer provided in contact with the first semiconductor layer in a surface region of the semiconductor substrate and having an impurity concentration different from that of the first semiconductor layer; From the semiconductor layer of the above to the second semiconductor layer,
A plurality of channel regions arranged in parallel with each other across the separation region; and a plurality of transfer electrodes arranged in parallel with each other on the first and second semiconductor layers so as to intersect with the channel region. A solid-state imaging device, wherein at least two of the plurality of transfer electrodes adjacent to a boundary region between the first semiconductor layer and the second semiconductor layer are compared with other transfer electrodes; It is characterized by being formed widely in the direction in which the channel region extends.
【０００８】[0008]
【作用】本発明によれば、濃度の異なる半導体層の境界
部分で転送電極の幅を広く形成することにより、境界部
分の転送電極の下で情報電荷を蓄積する領域が広がり、
半導体層の濃度の影響でポテンシャルが浅くなった場合
でも、境界部分以外の領域に比べて十分な量の情報電荷
を蓄積できる。従って、濃度の異なる半導体層の境界部
分で転送能力が低下することがなくなる。According to the present invention, by forming the transfer electrode wider at the boundary between the semiconductor layers having different concentrations, a region for storing information charges under the transfer electrode at the boundary is expanded.
Even when the potential becomes shallow due to the effect of the concentration of the semiconductor layer, a sufficient amount of information charges can be stored as compared with the region other than the boundary portion. Therefore, the transfer capability does not decrease at the boundary between the semiconductor layers having different concentrations.
【０００９】[0009]
【実施例】図１は、本発明の固体撮像素子の撮像部の構
造を示す平面図で、第２図は、そのＸ−Ｘ線断面図であ
る。Ｎ型のシリコン基板２０の一面には、Ｐ型の拡散層
２１が形成される。この拡散層２１は、図６の拡散層１
１と同様に、撮像部で過剰な情報電荷をシリコン基板２
０に吸収させ、蓄積部でシリコン基板２０への情報電荷
の流出を防止するように、蓄積部の濃度が撮像部の濃度
より高く形成される。拡散層２１内には、分離領域２２
を隔てて複数のチャネル領域２３が互いに平行に、撮像
部から蓄積部まで連続するように設けられる。これらの
チャネル領域２３は、基板表面部分にＮ型の埋め込み層
２４が設けられ、埋め込みチャネル構造を成している。
このような分離領域２２及びチャネル領域２３が形成さ
れたシリコン基板２０上には、絶縁膜２５を介して多結
晶シリコンからなる複数の転送電極２６、２７が、チャ
ネル領域２３と交差する方向に配置される。また、撮像
部と蓄積部との境界部分に最も近い位置に配置される２
本の転送電極２７については、その他の転送電極２６と
比較して、電極の幅及び電極どうしの間隔が広く形成さ
れる。これらの転送電極２６、２７上には、同じく多結
晶シリコンからなる２層目の転送電極２８、２９が、１
層目の転送電極２６、２７の間隙を覆うように配置され
る。この２層目の転送電極２８、２９についても、撮像
部と蓄積部との境界部分に最も近い位置に配置される２
本の転送電極２９が、その他の転送電極２８と比較し
て、幅が広く形成される。FIG. 1 is a plan view showing the structure of an image pickup section of a solid-state image pickup device according to the present invention, and FIG. 2 is a sectional view taken along line XX of FIG. On one surface of the N-type silicon substrate 20, a P-type diffusion layer 21 is formed. This diffusion layer 21 corresponds to the diffusion layer 1 shown in FIG.
As in the case of 1, the excess information charges are transferred to the silicon substrate 2 by the imaging unit.
The density of the storage section is formed higher than the density of the imaging section so that the density of the storage section is absorbed to prevent the information charges from flowing out to the silicon substrate 20 in the storage section. In the diffusion layer 21, an isolation region 22 is provided.
A plurality of channel regions 23 are provided in parallel with each other and continuously from the imaging unit to the storage unit. These channel regions 23 are provided with an N-type buried layer 24 on the surface of the substrate to form a buried channel structure.
A plurality of transfer electrodes 26 and 27 made of polycrystalline silicon are arranged on a silicon substrate 20 on which such an isolation region 22 and a channel region 23 are formed in a direction intersecting the channel region 23 via an insulating film 25. Is done. In addition, 2 which is arranged at the position closest to the boundary between the imaging unit and the storage unit.
Regarding the transfer electrodes 27, the width of the electrodes and the interval between the electrodes are formed wider than those of the other transfer electrodes 26. On these transfer electrodes 26 and 27, transfer electrodes 28 and 29 of the second layer also made of polycrystalline silicon
It is arranged so as to cover the gap between the transfer electrodes 26 and 27 of the layer. The transfer electrodes 28 and 29 of the second layer are also arranged at the position closest to the boundary between the imaging unit and the storage unit.
The transfer electrodes 29 are formed wider than the other transfer electrodes 28.
【００１０】これらの転送電極２６〜２９には、撮像部
及び蓄積部でそれぞれ４相の垂直転送クロックφV1〜φ
V4及び蓄積転送クロックφS1〜φS4が印加される。これ
らの垂直転送クロックφV1〜φV4及び蓄積転送クロック
φS1〜φS4については、図６と同一で、情報電荷の転送
期間に両転送クロックが同期して撮像部から転送出力さ
れる情報電荷を蓄積部に取り込むようにしている。この
とき、幅が広く形成される転送電極２７、２９の下のチ
ャネル領域２３では、図３に示すように、１つの転送電
極２７（あるいは２９）により形成されるポテンシャル
がチャネル領域２３の転送方向に広がっているため、ポ
テンシャルが浅くなったとしても、十分な転送能力が確
保されている。従って、撮像部と蓄積部とで同一レベル
の転送クロックを用いたとしても、撮像部から蓄積部へ
円滑に情報電荷を転送することができる。The transfer electrodes 26 to 29 have four-phase vertical transfer clocks φ V1 to φ V at the imaging unit and the storage unit, respectively.
V4 and the accumulation transfer clocks φ S1 to φ S4 are applied. The vertical transfer clocks φ V1 to φ V4 and the accumulation transfer clocks φ S1 to φ S4 are the same as those in FIG. 6, and the information charges transferred and output from the imaging unit in synchronization with both transfer clocks during the transfer period of the information charges. Is stored in the storage unit. At this time, in the channel region 23 below the transfer electrodes 27 and 29 having a wide width, the potential formed by one transfer electrode 27 (or 29) changes the transfer direction of the channel region 23 as shown in FIG. Therefore, even if the potential becomes shallow, sufficient transfer capacity is secured. Therefore, even if the same transfer clock is used for the imaging unit and the storage unit, information charges can be smoothly transferred from the imaging unit to the storage unit.
【００１１】ところで、蓄積部のチャネル領域２３につ
いては、情報電荷を蓄積する部分（ポテンシャル井戸）
が浅くなると同時に、画素を分離する部分（ポテンシャ
ル障壁）が高くなるため、撮像部から離れて幅の狭い転
送電極２８が配置される部分でも、情報電荷の転送能力
自体は所望レベルを維持する。このため、撮像部から蓄
積部に受け渡された情報電荷が、幅の広い転送電極２
７、２９の下のチャネル領域２３から幅の狭い転送電極
２６、２８の下のチャネル領域２３に移っても、その情
報電荷を確実に転送することができる。By the way, with respect to the channel region 23 of the storage section, a portion (potential well) for storing information charges.
And the portion (potential barrier) for separating the pixels becomes higher at the same time as the depth becomes shallower. Therefore, even in the portion where the transfer electrode 28 having a small width is arranged away from the imaging section, the transfer capability of the information charge itself is maintained at a desired level. For this reason, the information charges transferred from the imaging unit to the storage unit are transferred to the wide transfer electrode 2.
Even when the transfer from the channel region 23 below the gate electrodes 7 and 29 to the channel region 23 below the narrow transfer electrodes 26 and 28, the information charges can be surely transferred.
【００１２】また、撮像部と蓄積部との境界部分の転送
電極２７、２９の幅を広く形成することにより、拡散層
２１に対する転送電極２７、２９の位置合わせ精度が緩
和されるため、製造工程が容易になる。なお、以上の実
施例においては、フレームトランスファ型の固体撮像素
子について例示したが、受光素子の情報電荷を一旦垂直
転送部に読み出し、この垂直転送部から蓄積部へ転送す
る所謂フレームインタライントランスファ方式の固体撮
像素子の垂直転送部と蓄積部との接続部分の構造にも採
用可能である。In addition, since the width of the transfer electrodes 27 and 29 at the boundary between the image pickup section and the storage section is widened, the alignment accuracy of the transfer electrodes 27 and 29 with respect to the diffusion layer 21 is eased. Becomes easier. In the above embodiments, the frame transfer type solid-state imaging device has been described as an example. However, a so-called frame interline transfer method in which information charges of a light receiving element are temporarily read out to a vertical transfer unit and transferred from the vertical transfer unit to a storage unit. It is also applicable to the structure of the connection portion between the vertical transfer section and the storage section of the solid-state imaging device.
【００１３】[0013]
【発明の効果】本発明によれば、撮像部から蓄積部（垂
直転送部から蓄積部）へ情報電荷を円滑に転送させるこ
とができ、転送効率の劣化を防止することができる。ま
た、位置合わせ精度の緩和による製造工程の容易化によ
って、製造歩留まりの向上が望めるため、転送効率が良
好で且つ低コストの固体撮像素子を提供することができ
る。According to the present invention, information charges can be smoothly transferred from the imaging section to the storage section (from the vertical transfer section to the storage section), and deterioration of transfer efficiency can be prevented. In addition, since the manufacturing process is expected to be improved by facilitating the manufacturing process by relaxing the alignment accuracy, a solid-state imaging device with good transfer efficiency and low cost can be provided.
【図１】本発明の固体撮像素子の撮像部と蓄積部との接
続部分を示す平面図である。FIG. 1 is a plan view showing a connection portion between an imaging unit and a storage unit of a solid-state imaging device according to the present invention.
【図２】図１のＸ−Ｘ線の断面図である。FIG. 2 is a sectional view taken along line XX of FIG.
【図３】本発明の固体撮像素子のポテンシャルの状態を
示す図である。FIG. 3 is a diagram showing a potential state of the solid-state imaging device of the present invention.
【図４】フレームトランスファ型の固体撮像素子の模式
的平面図である。FIG. 4 is a schematic plan view of a frame transfer type solid-state imaging device.
【図５】従来の固体撮像素子の撮像部と蓄積部との接続
部分を示す平面図である。FIG. 5 is a plan view illustrating a connection portion between an imaging unit and a storage unit of a conventional solid-state imaging device.
【図６】図５のＸ−Ｘ線の断面図である。FIG. 6 is a sectional view taken along line XX of FIG. 5;
【図７】従来の固体撮像素子のポテンシャルの状態を示
す図である。FIG. 7 is a diagram illustrating a potential state of a conventional solid-state imaging device.
１ 撮像部 ２ 蓄積部 ３ 水平転送部 ４ 出力部 １０、２０ シリコン基板 １１、２１ 拡散層 １２、２２ 分離領域 １３、２３ チャネル領域 １４、２４ 埋め込み層 １５、２５ 絶縁膜 １６、１７、２６、２７、２８、２９ 転送電極 DESCRIPTION OF SYMBOLS 1 Image pick-up part 2 Storage part 3 Horizontal transfer part 4 Output part 10, 20 Silicon substrate 11, 21 Diffusion layer 12, 22 Separation area 13, 23 Channel area 14, 24 Embedded layer 15, 25 Insulating film 16, 17, 26, 27 , 28,29 Transfer electrode
Claims (1)
像部に発生する情報電荷を取り込んで蓄積する蓄積部
と、を有する固体撮像素子において、一導電型の半導体
基板と、この半導体基板の上記撮像部領域内に設けら
れ、上記半導体基板とは逆導電型の第１の半導体層と、
上記半導体基板の上記蓄積部領域内で上記第１の半導体
層に上記半導体基板の表面に対して水平方向に接して設
けられ、上記第１の半導体層とは不純物濃度が異なり、
且つ、上記半導体基板とは逆導電型の第２の半導体層
と、上記撮像部領域から上記蓄積部領域まで連続し、分
離領域を隔てて互いに平行に配列される複数のチャネル
領域と、このチャネル領域と交差して上記チャネル領域
及び上記分離領域上に互いに平行に配列される複数の転
送電極と、を備え、複数の上記転送電極のうち、少なく
とも、上記第１の半導体層と上記第２の半導体層との境
界領域に隣接する２本が、他の転送電極と比較して上記
チャネル領域の延在する方向に広く形成されることを特
徴とする固体撮像素子。An imaging unit including a plurality of light receiving pixels;
Storage section that captures and stores information charges generated in the image section
A solid-state imaging device having: a semiconductor substrate of one conductivity type; a first semiconductor layer provided in the imaging unit region of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate ;
The first semiconductor layer is provided in the accumulation portion region of the semiconductor substrate in contact with the surface of the semiconductor substrate in a horizontal direction, and has an impurity concentration different from that of the first semiconductor layer ;
A second semiconductor layer having a conductivity type opposite to that of the semiconductor substrate; a plurality of channel regions continuous from the imaging unit region to the storage unit region and arranged in parallel with each other with a separation region therebetween; The channel region intersecting with the region
And a plurality of transfer electrodes arranged in parallel with each other on the separation region , wherein at least one of the plurality of transfer electrodes is adjacent to a boundary region between the first semiconductor layer and the second semiconductor layer. The solid-state imaging device is characterized in that two of the transfer electrodes are formed wider in the direction in which the channel region extends than other transfer electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10104493A JP3263476B2 (en) | 1993-04-27 | 1993-04-27 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10104493A JP3263476B2 (en) | 1993-04-27 | 1993-04-27 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06310703A JPH06310703A (en) | 1994-11-04 |
| JP3263476B2 true JP3263476B2 (en) | 2002-03-04 |
Family
ID=14290144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10104493A Expired - Fee Related JP3263476B2 (en) | 1993-04-27 | 1993-04-27 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3263476B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4596872B2 (en) * | 2004-09-28 | 2010-12-15 | 三洋電機株式会社 | Solid-state image sensor |
| JP2006222237A (en) * | 2005-02-09 | 2006-08-24 | Sanyo Electric Co Ltd | Solid-state imaging device |
-
1993
- 1993-04-27 JP JP10104493A patent/JP3263476B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06310703A (en) | 1994-11-04 |
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