JP3257225B2 - Planar type semiconductor device and method of manufacturing the same - Google Patents
Planar type semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP3257225B2 JP3257225B2 JP02006094A JP2006094A JP3257225B2 JP 3257225 B2 JP3257225 B2 JP 3257225B2 JP 02006094 A JP02006094 A JP 02006094A JP 2006094 A JP2006094 A JP 2006094A JP 3257225 B2 JP3257225 B2 JP 3257225B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- impurity concentration
- layer
- guard ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ガードリング構造を設
けて高耐圧化を図ったプレーナ型半導体素子およびその
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar semiconductor device having a high breakdown voltage by providing a guard ring structure and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】プレーナ型半導体素子の表面に露出する
空乏層を半導体基体縁部に向かって広げて電界を緩和
し、耐圧を向上するためにガードリング構造あるいはフ
ィールドプレート構造が用いられることはよく知られて
いる。図２はガードリング構造を有する高耐圧ダイオー
ドの縁部構造を示し、ｎ形シリコン基板１には表面から
の不純物拡散によりｐ形アノード領域２を形成すると同
時に、同じ深さのｐ形ガードリング領域３が形成されて
いる。ガードリング領域３が浅いと、可動イオンがガー
ドリング領域上の酸化膜４の表面に蓄積するなど、外界
の影響を受けて耐圧が不安定になるため、その影響を受
けにくくするためアノード領域２と同様に不純物濃度を
高くし、深さを深くしていた。基板の縁部にはカソード
電極の電位と同一電位のｎ+ エッジ領域１１が形成さ
れ、酸化膜４の開口部でｐアノード領域２にはアノード
電極５が、エッジ領域１１には空乏層の伸びを規制する
電位固定電極１２が接触している。2. Description of the Related Art A guard ring structure or a field plate structure is often used to widen a depletion layer exposed on the surface of a planar type semiconductor element toward an edge of a semiconductor substrate to reduce an electric field and improve a breakdown voltage. Are known. FIG. 2 shows an edge structure of a high-breakdown-voltage diode having a guard ring structure. A p-type anode region 2 is formed on an n-type silicon substrate 1 by impurity diffusion from the surface, and a p-type guard ring region having the same depth is formed. 3 are formed. If the guard ring region 3 is shallow, the breakdown voltage becomes unstable due to the influence of the external world such as movable ions accumulating on the surface of the oxide film 4 on the guard ring region. Similarly, the impurity concentration was increased and the depth was increased. An n + edge region 11 having the same potential as that of the cathode electrode is formed at the edge of the substrate, the anode electrode 5 is formed in the p anode region 2 at the opening of the oxide film 4, and the depletion layer is extended in the edge region 11. Are in contact with each other.
【０００３】図３に示すダイオードでは、外界の影響を
少なくするためにガードリング構造にフィールドプレー
ト構造を併用しており、ガードリング領域３の表面にフ
ィールドプレート電極６を接触させ、ガードリング部分
の電界と外部の電界を結び付けている。[0003] In the diode shown in FIG. 3, a field plate structure is used in combination with a guard ring structure in order to reduce the influence of the outside world. The electric field is connected to the external electric field.
【０００４】[0004]
【発明が解決しようとする課題】半導体装置の進歩およ
び要求特性の進展の状況をみると、半導体装置はますま
す高速化が必要となってくる。高速化を達成するために
は、例えば図２、図３に示すダイオードにおいて、ｐア
ノード領域２の不純物濃度を低く、またその拡散深さを
浅くする必要がある。単純に不純物濃度を下げ、拡散深
さを浅くするとＰＮ接合逆耐圧が低下する。同時にガー
ドリング領域３の不純物濃度が下がり、拡散深さが浅く
なるため、外界の影響を強く受け、表面層のキャリア濃
度が変化することなどにより、逆耐圧が不安定となる。
さらに、ガードリング領域３の不純物濃度が低くなる
と、フィールドプレート電極６との間の抵抗が大きくな
り、フィールドプレートによる電界安定の効果も不十分
となる。In view of the progress of semiconductor devices and the progress of required characteristics, it is necessary to increase the speed of semiconductor devices. In order to achieve higher speed, for example, in the diodes shown in FIGS. 2 and 3, it is necessary to lower the impurity concentration of the p anode region 2 and to reduce the diffusion depth. Simply lowering the impurity concentration and decreasing the diffusion depth lowers the reverse breakdown voltage of the PN junction. At the same time, since the impurity concentration of the guard ring region 3 decreases and the diffusion depth decreases, the reverse breakdown voltage becomes unstable due to a strong influence of the external environment and a change in the carrier concentration of the surface layer.
Further, when the impurity concentration of the guard ring region 3 becomes low, the resistance between the guard ring region 3 and the field plate electrode 6 becomes large, and the effect of the field plate to stabilize the electric field becomes insufficient.
【０００５】図３のダイオードにおいて、ｎ基板１とｐ
領域２の間のＰＮ接合に逆バイアスが加わったとき、空
乏層は図４に点線７１で示すようにｎ基板１に、またｐ
ガードリング領域３に沿って延びるが、ｐ領域２の不純
物濃度が低いときには、横方向拡散で形成されるその周
辺部は特に不純物濃度が低く、点線７２に示すようにｐ
領域２の内部にもかなり広がり、アノード電極５に到達
するとパンチスルーが起きてしまう。このパンチスルー
が起きないようにするには、ｐ領域２表面の周縁部を覆
う酸化膜４を１０μｍ程度の幅まで広げ、空乏層端面７
２がアノード電極５の接触面に達しないようにする。し
かしこれによりアノード電極５の接触面積が狭くなるた
め、素子の寸法を大きくしてしまう。[0005] In the diode of FIG.
When a reverse bias is applied to the PN junction between the regions 2, a depletion layer is formed on the n substrate 1 as shown by a dotted line 71 in FIG.
Although extending along the guard ring region 3, when the impurity concentration of the p region 2 is low, the peripheral portion formed by lateral diffusion has a particularly low impurity concentration.
It spreads considerably inside the region 2 and, when it reaches the anode electrode 5, punch-through occurs. To prevent this punch-through from occurring, the oxide film 4 covering the peripheral portion of the surface of the p region 2 is expanded to a width of about 10 μm, and the depletion layer end face 7 is formed.
2 does not reach the contact surface of the anode electrode 5. However, this causes the contact area of the anode electrode 5 to be narrowed, thus increasing the dimensions of the element.
【０００６】本発明の目的は、上記の問題を解決し、第
一導電形の半導体層に形成される第二導電形領域を高速
化のために、不純物濃度を下げ、浅くしても耐圧を低下
させないことのできるプレーナ型半導体素子およびその
製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and reduce the impurity concentration in order to increase the speed of the second conductivity type region formed in the semiconductor layer of the first conductivity type. It is an object of the present invention to provide a planar semiconductor element which can be prevented from lowering and a method for manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、第一導電形の半導体層の表面層に形成
された第二導電形領域に主電極の一つが接触するプレー
ナ型半導体素子において、第二導電形領域の周縁部に高
不純物濃度領域が設けられ、その高不純物濃度領域の内
側の部分の表面に主電極の周縁部が接触しているものと
する。第一導電形の半導体層の表面層に、第二導電形領
域と同時に形成され、その領域をとり囲む第二導電形の
ガードリング領域を有し、そのガードリング領域の表面
層にも高不純物濃度領域が設けられたことが有効であ
る。また、本発明のそのような半導体素子の製造方法
は、第一導電形の半導体層の表面層に第二導電形領域を
形成したのち、表面をドーピング元素を含む絶縁性ガラ
ス層で覆い、熱処理によりそのドーピング元素を拡散さ
せて高不純物濃度領域を形成するものとする。あるい
は、第一導電形の半導体層の表面層に第二導電形領域お
よびそれを囲む第二導電形のガードリング領域を同時に
形成し、次いで表面をドーピング元素を含む絶縁性ガラ
ス層で覆い、熱処理により各領域の表面層に第二導電形
の高不純物濃度領域を同時に形成することが良い。SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a planar electrode in which one of the main electrodes contacts a second conductivity type region formed in a surface layer of a semiconductor layer of a first conductivity type. In the type semiconductor device, it is assumed that a high impurity concentration region is provided at a peripheral portion of the second conductivity type region, and a peripheral portion of the main electrode is in contact with a surface of a portion inside the high impurity concentration region. On the surface layer of the semiconductor layer of the first conductivity type, a guard ring region of the second conductivity type is formed simultaneously with the second conductivity type region and surrounds the region, and the surface layer of the guard ring region also has a high impurity. It is effective that the density region is provided. In addition, the method of manufacturing such a semiconductor device of the present invention includes forming a second conductivity type region on a surface layer of a semiconductor layer of a first conductivity type, covering the surface with an insulating glass layer containing a doping element, and performing a heat treatment. To form a high impurity concentration region by diffusing the doping element. Alternatively, a second conductivity type region and a guard ring region of the second conductivity type surrounding the second conductivity type region are simultaneously formed on the surface layer of the semiconductor layer of the first conductivity type, and then the surface is covered with an insulating glass layer containing a doping element, followed by heat treatment. Therefore, it is preferable to simultaneously form the second conductivity type high impurity concentration regions on the surface layer of each region.
【０００８】[0008]
【作用】第一導電形半導体層とＰＮ接合を形成する第二
導電形領域の周縁部に高不純物濃度領域を設け、その内
側の部分の表面に主電極を接触させたことにより、第二
導電形領域の周縁部でＰＮ接合から空乏層が広がって
も、高不純物濃度領域でその広がりが抑えられるため、
パンチスルーすることがない。ガードリング領域にもそ
れと同時に高不純物濃度を形成すれば、外界の影響を受
けにくくする。A high impurity concentration region is provided on the periphery of the second conductivity type region forming a PN junction with the first conductivity type semiconductor layer, and the main electrode is brought into contact with the inner surface of the high impurity concentration region. Even if the depletion layer spreads from the PN junction at the periphery of the shaped region, the spread is suppressed in the high impurity concentration region.
No punch through. If a high impurity concentration is also formed in the guard ring region at the same time, the guard ring region is less affected by the external environment.
【０００９】[0009]
【実施例】以下、図２、図３、図４と共通の部分に同一
の符号を付した図を引用して本発明の実施例について述
べる。図１は本発明の一実施例のプレーナ型ダイオード
を示し、ｎ基板１の表面層に形成されたｐアノード領域
２の周縁部およびガードリング領域３の中央部の表面層
にほう素がドープされたｐ+ 領域８が形成されている。
そして、その領域にアノード電極５およびフィールドプ
レート電極６が接触している。また、電位固定電極１２
の接触する部分にもほう素ドープｐ+ 領域８が形成され
ている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings in which the same parts as those in FIGS. 2, 3 and 4 are denoted by the same reference numerals. FIG. 1 shows a planar type diode according to one embodiment of the present invention, in which boron is doped into a surface layer at a peripheral portion of a p anode region 2 and a central portion of a guard ring region 3 formed on a surface layer of an n substrate 1. P + region 8 is formed.
The anode electrode 5 and the field plate electrode 6 are in contact with the region. Further, the potential fixing electrode 12
A boron-doped p + region 8 is also formed at the portion where the contact is made.
【００１０】このような素子は図５ (ａ) 〜 (ｆ) の工
程で製造される。先ず、ｎ形シリコン基板１に熱酸化に
より酸化膜４を形成〔同図 (ａ) 〕、フォトリソグラフ
ィで不純物拡散領域に窓を開け〔同図 (ｂ) 〕、ほう素
などの不純物をイオン注入して低い不純物濃度で浅いｐ
アノード領域２およびｐガードリング領域３を形成する
〔同図 (ｃ) 〕。次に、表面にほう素ガラスＢＳＧ膜９
を１μｍの厚さに堆積し〔同図 (ｄ) 〕、１０００℃以
上の拡散工程を行って、酸化膜４の窓を再び利用してほ
う素を表面部に拡散させ、ｐ+ 領域８を形成する〔同図
(ｅ) 〕。このあと、フォトリソグラフィにより絶縁性
のＢＳＧ膜９および酸化膜４に接触孔を明け、金属の蒸
着により電極層を形成したのち、フォトリソグラフィに
よりアノード電極５およびフィールドプレート電極６に
分割する〔同図 (ｆ) 〕。図示しないが裏面側にｎ+ 層
の形成、カソード電極の被着を行う。Such an element is manufactured by the steps shown in FIGS. 5 (a) to 5 (f). First, an oxide film 4 is formed on the n-type silicon substrate 1 by thermal oxidation [FIG. 2A], a window is opened in an impurity diffusion region by photolithography [FIG. 2B], and impurities such as boron are ion-implanted. Low impurity concentration and shallow p
An anode region 2 and a p-guard ring region 3 are formed [FIG. Next, a boron glass BSG film 9 is formed on the surface.
Is deposited to a thickness of 1 μm (FIG. 4D), and a diffusion process at 1000 ° C. or higher is performed to diffuse the boron to the surface portion again using the window of the oxide film 4 to form the p + region 8. Form [same figure
(e)]. Thereafter, contact holes are formed in the insulating BSG film 9 and the oxide film 4 by photolithography, an electrode layer is formed by vapor deposition of metal, and then divided into an anode electrode 5 and a field plate electrode 6 by photolithography [FIG. (f)]. Although not shown, an n + layer is formed on the back surface side, and a cathode electrode is deposited.
【００１１】この素子では、アノード領域２の周縁部表
面層にＢＳＧ膜９よりのほう素拡散によりｐ+ 領域８が
存在するため、ｎ基板１との間のＰＮ接合からｐ領域２
内に広がる空乏層がこのｐ+ 領域８に接触するアノード
電極５に達してパンチスルーを起こすことがない。従っ
て、アノード電極５をＰＮ接合の表面露出部近くまで広
げることができるので、アノード領域２の有効面積が広
がる。In this element, p + region 8 exists in the peripheral surface layer of anode region 2 due to boron diffusion from BSG film 9, so that p + region 8 is formed from PN junction with n substrate 1.
The depletion layer extending inside does not reach the anode electrode 5 in contact with the p + region 8 and does not cause punch-through. Therefore, the anode electrode 5 can be extended to near the surface exposed portion of the PN junction, so that the effective area of the anode region 2 is increased.
【００１２】この実施例では、ＰＮ接合がｎ基板とその
表面層に形成されたｐ領域２により形成されているが、
ｐ基板を用いその表面層にｎ領域を形成する場合にも実
施できることは明らかであり、その場合はＢＳＧ膜の代
わりにりんガラス (ＰＳＧ)膜を用いる。In this embodiment, the PN junction is formed by the n substrate and the p region 2 formed in the surface layer.
Obviously, the present invention can be applied to a case where an n region is formed in a surface layer using a p substrate. In this case, a phosphorus glass (PSG) film is used instead of the BSG film.
【００１３】[0013]
【発明の効果】本発明によれば、第一導電形領域に形成
されるＰＮ接合のための第二導電形領域の周辺部に、前
に第二導電形領域を形成するのに用いたマスクを再び用
いて形成できる高不純物濃度領域を設けることにより、
その第二導電形領域を不純物濃度を低く、深さを浅くし
ても、その領域への空乏層の広がりを抑制してパンチス
ルーが起こるのを防ぐことができる。また、ガードリン
グ領域の表面層に同時に形成できる高不純物濃度領域
も、その領域表面層に対する外界の影響を緩和できる。
これにより、信頼性の高い、高速、高耐圧のダイオード
が完成する。According to the present invention, a mask used to previously form the second conductivity type region around the periphery of the second conductivity type region for the PN junction formed in the first conductivity type region. By providing a high impurity concentration region that can be formed again by using
Even if the impurity concentration of the second conductivity type region is low and the depth is shallow, the spread of the depletion layer to that region can be suppressed, and punch-through can be prevented. In addition, a high impurity concentration region that can be simultaneously formed in the surface layer of the guard ring region can also reduce the influence of the external environment on the region surface layer.
As a result, a highly reliable, high-speed, high-withstand-voltage diode is completed.
【図１】本発明の一実施例のプレーナ型ダイオードの要
部断面図FIG. 1 is a sectional view of a main part of a planar diode according to an embodiment of the present invention.
【図２】従来のガードリング構造付きプレーナ型ダイオ
ードの要部断面図FIG. 2 is a sectional view of a main part of a conventional planar diode having a guard ring structure.
【図３】従来のフィールドプレート構造付きプレーナ型
ダイオードの要部断面図FIG. 3 is a sectional view of a main part of a conventional planar diode having a field plate structure.
【図４】従来のプレーナ型ダイオードでの空乏層を示す
断面図FIG. 4 is a cross-sectional view showing a depletion layer in a conventional planar diode.
【図５】図１のダイオードの製造工程を (ａ) ないし
(ｆ) の順に示す断面図FIGS. 5A to 5D show the manufacturing process of the diode of FIG.
Sectional view shown in order of (f)
１ ｎ形シリコン基板 ２ ｐアノード領域 ３ ｐガードリング領域 ４ 酸化膜 ５ アノード電極 ６ フィールドプレート電極 ８ ｐ+ ほう素ドープ領域 ９ ＢＳＧ膜Reference Signs List 1 n-type silicon substrate 2 p anode region 3 p guard ring region 4 oxide film 5 anode electrode 6 field plate electrode 8 p + boron-doped region 9 BSG film
Claims (4)
た第二導電形領域に主電極の一つが接触するものにおい
て、第二導電形領域の周縁部に高不純物濃度領域が設け
られ、その高不純物濃度領域の内側の部分の表面に前記
主電極の周縁部が接触することを特徴とするプレーナ型
半導体素子。1. A semiconductor device of a first conductivity type, wherein one of the main electrodes contacts a second conductivity type region formed on a surface layer of a semiconductor layer of the first conductivity type, wherein a high impurity concentration region is provided at a peripheral portion of the second conductivity type region. And a peripheral portion of the main electrode is in contact with a surface of a portion inside the high impurity concentration region.
電形領域と同時に形成され、その領域をとり囲む第二導
電形のガードリング領域を有し、そのガードリング領域
の表面層にも高不純物濃度領域が設けられた請求項１記
載のプレーナ型半導体素子。2. A guard ring region of a second conductivity type formed simultaneously with and surrounding a second conductivity type region in a surface layer of a semiconductor layer of a first conductivity type, and a surface of the guard ring region. 2. The planar semiconductor device according to claim 1, wherein a high impurity concentration region is also provided in the layer.
形領域を形成したのち、表面をドーピング元素を含む絶
縁性ガラス層で覆い、熱処理によりそのドーピング元素
を拡散させて第二導電形の高不純物濃度領域を形成する
ことを特徴とする請求項１あるいは２記載のプレーナ型
半導体素子の製造方法。3. A second conductivity type region is formed on a surface layer of a semiconductor layer of a first conductivity type, and the surface is covered with an insulating glass layer containing a doping element. 3. The method according to claim 1, wherein a conductive type high impurity concentration region is formed.
形領域およびそれを囲む第二導電形のガードリング領域
を同時に形成し、次いで表面をドーピング元素を含む絶
縁性ガラス層で覆い、熱処理により各領域の表面層に第
二導電形の高不純物濃度領域を同時に形成する請求項２
記載のプレーナ型半導体素子の製造方法。4. A second conductivity type region and a second conductivity type guard ring region surrounding the second conductivity type region are simultaneously formed on the surface layer of the semiconductor layer of the first conductivity type, and the surface is formed of an insulating glass layer containing a doping element. 3. A high impurity concentration region of the second conductivity type is simultaneously formed on the surface layer of each region by covering and heat treatment.
A manufacturing method of the planar type semiconductor device according to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02006094A JP3257225B2 (en) | 1994-02-17 | 1994-02-17 | Planar type semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02006094A JP3257225B2 (en) | 1994-02-17 | 1994-02-17 | Planar type semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07231104A JPH07231104A (en) | 1995-08-29 |
| JP3257225B2 true JP3257225B2 (en) | 2002-02-18 |
Family
ID=12016542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02006094A Expired - Fee Related JP3257225B2 (en) | 1994-02-17 | 1994-02-17 | Planar type semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3257225B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10238797B4 (en) * | 2002-08-23 | 2007-09-20 | Infineon Technologies Ag | Commutated diode and method for its production |
-
1994
- 1994-02-17 JP JP02006094A patent/JP3257225B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07231104A (en) | 1995-08-29 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |