JP3180672B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3180672B2 JP3180672B2 JP16910696A JP16910696A JP3180672B2 JP 3180672 B2 JP3180672 B2 JP 3180672B2 JP 16910696 A JP16910696 A JP 16910696A JP 16910696 A JP16910696 A JP 16910696A JP 3180672 B2 JP3180672 B2 JP 3180672B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- zener
- base
- semiconductor device
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特にサージ破壊を防止するツェナダイオードを内蔵した
トランジスタに関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a transistor having a built-in Zener diode for preventing surge breakdown.
【０００２】[0002]
【従来の技術】従来のツェナダイオードを内蔵した半導
体装置は、図６に示し、１はシリコンからなるＮ＋型半
導体基板、２はＮ−型コレクタ領域、３はＰ型ベース領
域、４はＮ＋型コレクタ表面領域、５はＮ＋型エミッタ
領域、６はエミッタ電極、７はベース電極、８は酸化膜
である。ここでＰ型ベース領域３をアノード、Ｎ＋型コ
レクタ表面領域４をカソードとしてコレクタ領域２、ベ
ース領域３間でツェナダイオードと、Ｎ＋型エミッタ領
域５、Ｐ型ベース領域３、Ｎ−型コレクタ領域２により
ＮＰＮトランジスタとを構成している。2. Description of the Related Art A conventional semiconductor device having a built-in Zener diode is shown in FIG. 6, wherein 1 is an N + type semiconductor substrate made of silicon, 2 is an N- type collector region, 3 is a P type base region, and 4 is an N + type. A collector surface region, 5 is an N + type emitter region, 6 is an emitter electrode, 7 is a base electrode, and 8 is an oxide film. Here, the P-type base region 3 is used as an anode, the N + -type collector surface region 4 is used as a cathode, and the collector region 2 has a Zener diode between the base region 3 and the N + -type emitter region 5, the P-type base region 3, and the N--type collector region 2. Form an NPN transistor.
【０００３】[0003]
【発明が解決しようとする課題】上記の半導体装置では
コレクタ領域２に正、ベース電極７に負の電圧が印加さ
れることにより、高濃度コレクタ表面領域４の表面で酸
化膜８中の可動イオンや外装樹脂中の可動イオンの影響
により生じる空乏層が高濃度コレクタ表面領域を横方向
に広がりツェナダイオードのブレークダウン電圧（ツェ
ナ耐圧）が変動する問題があった。また、可動イオンの
影響を減らすために、ベース電極で高濃度コレクタ表面
領域上の酸化膜を覆う場合、ベース電極と高濃度コレク
タ表面領域外へのはみ出し長さとの対応関係により耐圧
が安定しないといった問題があった。In the above-described semiconductor device, a positive voltage is applied to the collector region 2 and a negative voltage is applied to the base electrode 7, so that the movable ions in the oxide film 8 on the surface of the high concentration collector surface region 4 are formed. In addition, a depletion layer caused by the influence of mobile ions in the outer resin or the outside resin spreads over the high-concentration collector surface region in a lateral direction, so that the breakdown voltage (zener breakdown voltage) of the Zener diode fluctuates. Also, when the base electrode covers the oxide film on the high-concentration collector surface region in order to reduce the influence of mobile ions, the breakdown voltage is not stable due to the correspondence between the base electrode and the protruding length outside the high-concentration collector surface region. There was a problem.
【０００４】[0004]
【課題を解決するための手段】本発明は上記課題を解決
するために提案されたもので、一導電型半導体基板のコ
レクタ領域の表面に形成した他導電型ベース領域と，こ
のベース領域内の表面に形成した一導電型エミッタ領域
と、各領域の表面に形成した絶縁膜のベース領域とエミ
ッタ領域にコンタクト用の窓をあけて形成したベース電
極とエミッタ電極とを具備する半導体装置において、ベ
ース領域に表面から底部に抜けた他導電型不純物を拡散
しない貫通領域を形成し、この貫通領域にコレクタ領域
より高濃度の一導電型不純物のツェナ領域を設け、少な
くともツェナ領域上にベース領域とツェナ領域間の耐圧
でツェナ領域表面が反転しない厚さの絶縁膜を設け、ベ
ース電極またはエミッタ電極でツェナ領域上の絶縁膜を
介して被覆した半導体装置を提供する。このように、ツ
ェナダイオードの一導電型のツェナ領域が他導電型のベ
ース領域に囲まれることでガードリング効果を有すると
ともに、ツェナ領域の表面部分の絶縁膜の厚さを所望の
ツェナ耐圧以下でツェナ領域に反転層が形成しない厚さ
以上とし、かつ、この絶縁膜をベース電極またはエミッ
タ電極で被覆することにより安定したツェナ耐圧を得る
ことができる。SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and comprises a base region of another conductivity type formed on a surface of a collector region of a semiconductor substrate of one conductivity type and a base region in the base region. A semiconductor device comprising: one conductivity type emitter region formed on the surface; a base electrode and an emitter electrode formed by opening a contact window in the base region and the emitter region of an insulating film formed on the surface of each region; Diffusion of other conductivity type impurities that escaped from the surface to the bottom in the region
A through region is formed, and a zener region of one conductivity type impurity having a higher concentration than the collector region is provided in the through region, and at least a Zener region having a thickness on the zener region that does not invert the surface of the zener region due to withstand voltage between the base region and the zener region. Provided is a semiconductor device provided with an insulating film and covered with a base electrode or an emitter electrode via an insulating film over a zener region. As described above, the zener region of one conductivity type of the zener diode is surrounded by the base region of the other conductivity type, thereby having a guard ring effect, and the thickness of the insulating film on the surface of the zener region is set to a desired zener breakdown voltage or less. A stable Zener withstand voltage can be obtained by setting the thickness to be equal to or larger than the thickness at which the inversion layer is not formed in the Zener region and covering this insulating film with the base electrode or the emitter electrode.
【０００５】上記構成に加えて、貫通領域をベース領域
とコレクタ領域との表面の境界近傍に沿って、かつエミ
ッタ領域を囲んで形成した半導体装置を提供する。この
ように、貫通領域をリング状に形成し、そこにツェナ領
域を形成したので、ツェナ領域の外側のベース領域はガ
ードリングとなり、このガードリングの効果で耐圧は高
くなる。したがって、ツェナ耐圧を安定して得ることが
できる。In addition to the above structure, there is provided a semiconductor device in which a penetrating region is formed along the vicinity of a boundary between the surfaces of a base region and a collector region and surrounding an emitter region. As described above, since the penetrating region is formed in a ring shape and the zener region is formed therein, the base region outside the zener region becomes a guard ring, and the withstand voltage is increased by the effect of the guard ring. Therefore, a stable Zener breakdown voltage can be obtained.
【０００６】上記構成に加えて、貫通領域をベース領域
とコレクタ領域との表面の境界に沿う方向を分断するよ
うに複数に分割して形成した半導体装置を提供する。こ
のように、貫通領域を分割してリング状に形成し、そこ
にツェナ領域を形成したので、ツェナ領域は同じ拡散の
ベース領域で囲まれ、ツェナ耐圧を安定して得ることが
できる。In addition to the above structure, there is provided a semiconductor device formed by dividing a through region into a plurality of parts so as to divide a direction along a boundary between surfaces of a base region and a collector region. As described above, since the penetrating region is divided into a ring shape and the zener region is formed therein, the zener region is surrounded by the same diffusion base region, so that the zener breakdown voltage can be stably obtained.
【０００７】また、一導電型半導体基板のコレクタ領域
表面に形成した他導電型ベース領域と、このベース領域
内の表面に形成した一導電型エミッタ領域と、各領域の
表面に形成した絶縁膜のベース領域とエミッタ領域にコ
ンタクト用の窓をあけて形成したベース電極とエミッタ
電極とを具備する半導体装置において、ベース領域にベ
ース領域とコレクタ領域との境界に沿って、かつエミッ
タ領域を囲んで表面から底部に抜けた他導電型不純物を
拡散しない貫通領域を形成し、この貫通領域に半導体基
板より高濃度の一導電型不純物のツェナ領域を形成し、
絶縁膜を少なくともツェナ領域上にはベース領域とツェ
ナ領域間の耐圧でツェナ領域表面が反転しない厚さに形
成し、ツェナ領域の内側のベース領域と外側のベース領
域をツェナ領域上の絶縁膜を介してベース電極で電気的
に接続した半導体装置を提供する。このように、ツェナ
領域の表面部分の絶縁膜の厚さを所望のツェナ耐圧以下
でツェナ領域に反転層が形成しない厚さ以上とし、ツェ
ナ領域の外側ベース領域と内側ベース領域とをツェナ領
域上の絶縁膜を介してベース電極で電気的に接続したの
で、ツェナ領域が同じ電位のベース領域で囲まれツェナ
耐圧を安定して得ることができる。[0007] Also, a base region of another conductivity type formed on the surface of the collector region of the semiconductor substrate of one conductivity type, an emitter region of one conductivity type formed on the surface in the base region, and an insulating film formed on the surface of each region. In a semiconductor device having a base electrode and an emitter electrode formed with a contact window formed in a base region and an emitter region, a surface of the base region extends along a boundary between the base region and the collector region and surrounds the emitter region. Forming a through region that does not diffuse other conductivity type impurities that have escaped from the bottom to the bottom, and forming a zener region of one conductivity type impurity at a higher concentration than the semiconductor substrate in this through region;
An insulating film is formed at least on the zener region to a thickness such that the surface of the zener region is not inverted by the withstand voltage between the base region and the zener region. And a semiconductor device electrically connected by a base electrode through the semiconductor device. As described above, the thickness of the insulating film on the surface of the zener region is set to be equal to or less than the desired zener breakdown voltage and equal to or greater than the thickness at which the inversion layer is not formed in the zener region, and the outer base region and the inner base region of the zener region are formed on the zener region. Electrically connected by the base electrode via the insulating film described above, the Zener region is surrounded by the base region having the same potential, so that the Zener breakdown voltage can be stably obtained.
【０００８】また、ツェナ領域をベース領域より浅く形
成した半導体装置を提供する。この場合、通常ベース領
域下面と貫通領域のコーナの境界で最も早くブレークダ
ウンするが、この領域のコレクタ領域の濃度が低いた
め、ブレークダウンはツェナ領域でおこりツェナ耐圧を
安定して得ることができる。Another object of the present invention is to provide a semiconductor device having a Zener region formed shallower than a base region. In this case, the breakdown usually occurs first at the boundary between the lower surface of the base region and the corner of the through region. However, since the concentration of the collector region in this region is low, the breakdown occurs in the zener region and the zener breakdown voltage can be stably obtained. .
【０００９】また、絶縁膜をシリコン酸化膜とその上の
リンガラス層で形成した半導体装置を提供する。このよ
うに、リンガラス層を酸化膜上に形成したことにより、
可動イオンをトラップする効果が強いので、ツェナ耐圧
を安定して得ることができる。Another object of the present invention is to provide a semiconductor device in which an insulating film is formed of a silicon oxide film and a phosphorus glass layer thereon. Thus, by forming the phosphorus glass layer on the oxide film,
Since the effect of trapping mobile ions is strong, the Zener breakdown voltage can be stably obtained.
【００１０】また、貫通領域の幅を貫通領域を囲むベー
ス領域から延びる空乏層より広くした半導体装置を提供
する。このように、貫通領域の幅を貫通領域を囲むベー
ス領域から延びる空乏層より広くしたので、両側の空乏
層同志が重なることがなくなる。あるいは、リング状ツ
ェナ領域の内側の空乏層が電気的に分離されたリング状
ツェナ領域の外側のベース領域にぶつかることがなくな
る。その結果、ツェナ領域でブレークダウンし、ツェナ
耐圧を安定して得ることができる。Further, the present invention provides a semiconductor device in which the width of the through region is wider than the depletion layer extending from the base region surrounding the through region. As described above, since the width of the through region is wider than the depletion layer extending from the base region surrounding the through region, the depletion layers on both sides do not overlap. Alternatively, the depletion layer inside the ring-shaped zener region does not hit the base region outside the electrically separated ring-shaped zener region. As a result, breakdown occurs in the zener region, and a stable zener breakdown voltage can be obtained.
【００１１】[0011]
［発明の実施の形態１］本発明の第１の実施の形態につ
いて図１の半導体装置の側断面図、図２の図１のＡ−Ａ
での断面図を用いて説明する。[First Embodiment of the Invention] A first embodiment of the present invention is a side sectional view of the semiconductor device of FIG. 1 and AA of FIG. 2 of FIG.
This will be described with reference to the cross-sectional view of FIG.
【００１２】１１はシリコンからなる一導電型即ちＮ＋
型半導体基板、１２はＮ−型コレクタ領域、１３は他導
電型即ちＰ型ベース領域、１４は貫通領域、１５はＮ型
ツェナ領域、１６はＮ＋型エミッタ領域、１７はエミッ
タ電極、１８はベース電極、１９はシリコン酸化膜、２
０はリンガラス層、２１は絶縁膜で、シリコン酸化膜１
９とその上に形成したリンガラス層２０とを合わせたも
のである。Reference numeral 11 denotes one conductivity type of silicon, ie, N +
Type semiconductor substrate, 12 is an N- type collector region, 13 is another conductivity type, that is, a P type base region, 14 is a through region, 15 is an N type Zener region, 16 is an N + type emitter region, 17 is an emitter electrode, and 18 is a base. Electrode, 19 is a silicon oxide film, 2
0 is a phosphorus glass layer, 21 is an insulating film, and a silicon oxide film 1
9 and the phosphorus glass layer 20 formed thereon.
【００１３】この半導体装置の構造を製造方法を交えて
説明する。Ｎ＋型半導体基板１１の主面にエピタキシャ
ル成長により、Ｎ−型コレクタ領域１２を形成する。コ
レクタ領域１２の表面にフォトリソグラフィを用いてボ
ロンをイオン注入した後に、熱拡散で角が丸い４角形の
Ｐ型ベース領域１３を形成する。また、ベース領域１３
は角が丸くなくてもよい。また、円形でも楕円形でもよ
い。このとき、ベース領域１３にベース領域１３とコレ
クタ領域１２との表面の境界の近傍に沿ってベース領域
１３の表面から底面にかけて、ボロンが拡散されない貫
通領域１４を形成する。貫通領域１４は平面形状が角が
丸く細長い矩形に分割し、４箇所形成する。貫通領域１
４の分割は４箇所に限るものではなく何個に分割しても
よい。また、貫通領域１４は角が丸くなくてもよい。ま
た、円形や楕円形でもよい。ただし、分割したツェナ領
域１５が同じ耐圧になるように分割する必要がある。つ
づいて、フォトリソグラフィを用いてこの貫通領域１４
にリンをイオン注入した後に、熱拡散でベース領域１３
と同じか浅く、コレクタ領域１２より濃度の濃いＮ型ツ
ェナ領域１５を形成する。したがって、ツェナ領域１５
の下にはＮ−型の貫通領域１４が残る。The structure of the semiconductor device will be described together with the manufacturing method. An N- type collector region 12 is formed on the main surface of the N + type semiconductor substrate 11 by epitaxial growth. After boron ions are implanted into the surface of the collector region 12 using photolithography, a quadrangular P-type base region 13 having rounded corners is formed by thermal diffusion. Also, the base region 13
Does not have to have rounded corners. Further, the shape may be circular or elliptical. At this time, a penetrating region 14 where boron is not diffused is formed in the base region 13 along the vicinity of the boundary between the surface of the base region 13 and the collector region 12 from the surface of the base region 13 to the bottom surface. The through region 14 is divided into an elongated rectangle having a plan shape with rounded corners and four locations. Penetration area 1
The division of 4 is not limited to four places, and may be divided into any number. The corners of the penetrating region 14 may not be round. Further, the shape may be circular or elliptical. However, it is necessary to divide the zener regions 15 so that the divided zener regions 15 have the same breakdown voltage. Subsequently, the penetrating region 14 is formed using photolithography.
After ion implantation of phosphorus, the base region 13 is thermally diffused.
An N-type Zener region 15 is formed, which is as shallow or shallower and has a higher concentration than the collector region 12. Therefore, the zener region 15
The N-type penetrating region 14 remains below.
【００１４】つづいて、熱酸化により表面全面にシリコ
ン酸化膜１９を形成する。ＣＶＤにより形成してもよ
い。また、酸化膜に限らず窒化膜でもよい。つづいて、
フォトリソグラフィを用いて、ツェナ領域１５より内側
の内側ベース領域１３ａの一部の表面にリン拡散をして
エミッタ領域１６を形成する。ツェナ領域１５が内側ベ
ース領域１３ａを介してエミッタ領域１６を囲んだ形状
になる。このとき、シリコン酸化膜１９上にリンガラス
層２０が形成される。さらに、必要に応じてリンガラス
層２０をＣＶＤで積層して厚くしてもよい。Subsequently, a silicon oxide film 19 is formed on the entire surface by thermal oxidation. It may be formed by CVD. Further, not only the oxide film but also a nitride film may be used. Then,
Using photolithography, phosphorus is diffused into a part of the surface of the inner base region 13a inside the zener region 15 to form the emitter region 16. The Zener region 15 has a shape surrounding the emitter region 16 via the inner base region 13a. At this time, a phosphorus glass layer 20 is formed on the silicon oxide film 19. Further, if necessary, the phosphorus glass layer 20 may be laminated by CVD to increase the thickness.
【００１５】つづいて、フォトリソグラフィとアルミ蒸
着を用いてベース領域１３とエミッタ領域１６のコンタ
クト領域にベース電極１８とエミッタ電極１７を形成す
る。このとき、ツェナ領域１５上を絶縁膜２１を介して
ベース電極１８で覆い、ツェナ領域１５の内側ベース領
域１３ａとツェナ領域１５の外側の外側ベース領域１３
ｂをベース電極１８で電気的に接続する。また、分割さ
れたツェナ領域１５間で内側ベース領域１３ａと外側ベ
ース領域１３ｂは電気的に接続されているので、外側ベ
ース領域１３ｂをベ−ス電極１８で必ずしも接続する必
要はない。したがって、外側ベース領域１３ｂ上も絶縁
膜２１を介してベース電極１８で覆ってもよい。いづれ
の場合も、ベース電極１８を外側ベース領域１３ｂを越
えてコレクタ領域１２の絶縁膜２１上まで形成してもよ
い。また、トランジスタを動作させるときは、エミッタ
領域１６とベ−ス領域１３の電位差はＶEBだけなので、
ベース電極１８同様にエミッタ電極１７で、ツェナ領域
１５上を絶縁膜２１を介して覆ってもよいし、外側ベー
ス領域１３ｂを越えてコレクタ領域１２の絶縁膜２１上
まで覆ってもよい。Subsequently, a base electrode 18 and an emitter electrode 17 are formed in a contact region between the base region 13 and the emitter region 16 by using photolithography and aluminum evaporation. At this time, the zener region 15 is covered with the base electrode 18 via the insulating film 21, and the inner base region 13 a of the zener region 15 and the outer base region 13 outside the zener region 15 are formed.
b is electrically connected by the base electrode 18. Since the inner base region 13a and the outer base region 13b are electrically connected between the divided Zener regions 15, the outer base region 13b does not necessarily need to be connected with the base electrode 18. Therefore, the outer base region 13b may be covered with the base electrode 18 via the insulating film 21. In either case, the base electrode 18 may be formed over the insulating film 21 of the collector region 12 beyond the outer base region 13b. When the transistor is operated, the potential difference between the emitter region 16 and the base region 13 is only VEB.
Like the base electrode 18, the emitter electrode 17 may cover the zener region 15 via the insulating film 21, or may cover the outer base region 13b to the insulating film 21 of the collector region 12.
【００１６】上記構造でエミッタ領域１６、ベース領域
１３、コレクタ領域１２がエミッタ、ベース、コレクタ
としてＮＰＮトランジスタを構成し、ツェナ領域１５、
ベース領域１３をカソード、アノードとしてコレクタ、
ベース間にツェナダイオードを構成する。In the above structure, the emitter region 16, the base region 13, and the collector region 12 constitute an NPN transistor as an emitter, a base, and a collector.
A base region 13 as a cathode, a collector as an anode,
A zener diode is formed between the bases.
【００１７】この構造において、絶縁膜２１の厚さを所
望の電圧即ちツェナ領域１５でブレークダウンする電圧
で、絶縁膜２１の下のツェナ領域１５の表面に反転層を
形成しない厚さ以上にする。In this structure, the thickness of the insulating film 21 is set to a desired voltage, that is, a voltage at which the breakdown occurs in the zener region 15, so that the thickness of the insulating film 21 does not form an inversion layer on the surface of the zener region 15 below the insulating film 21. .
【００１８】このときの絶縁膜２１の厚さは概ね次式の
通りになる。これは一般にＭＯＳ構造の理論式より ｔox＝（Ｖz −Ｖfb−φs （inv ））（εox・εo ）／
（ｑ・Ｎd ・Ｌd ） ここで、ｔox ：絶縁膜の厚さ Ｖz ：ベース領域１３とツェナ領域１５間の耐圧（ツ
ェナ耐圧） Ｖfb ：フラットバンド電圧 φs （inv ）：反転時の表面ポテンシャル εox ：絶縁膜の比誘電率 εo ：真空の誘電率 ｑ ：電荷 Ｎd ：ツェナ領域のドナーの濃度 Ｌd ：縦方向の空乏層の幅 で導かれ所望のツェナ耐圧により、絶縁膜の厚さを必要
な厚さに設定すれば良い。例えば、ベース領域１３とツ
ェナ領域１５間の所望の耐圧を１００Ｖとすると、絶縁
膜の厚さは１．５μｍ以上が必要となる。At this time, the thickness of the insulating film 21 is approximately expressed by the following equation. This is generally calculated from the theoretical formula of the MOS structure as follows: tox = (Vz−Vfb−φs (inv)) (εox · εo) /
(Q · Nd · Ld) where tox: thickness of insulating film Vz: breakdown voltage between base region 13 and zener region 15 (zener breakdown voltage) Vfb: flat band voltage φs (inv): surface potential at inversion εox: Dielectric constant of insulating film εo: dielectric constant in vacuum q: electric charge Nd: donor concentration in zener region Ld: width of vertical depletion layer Just set it to For example, assuming that the desired withstand voltage between the base region 13 and the zener region 15 is 100 V, the thickness of the insulating film needs to be 1.5 μm or more.
【００１９】シリコン酸化膜１９の上にリンガラス層２
０を形成した場合に可動イオンをトラップして、可動イ
オンの影響を防ぐ効果が強いので、ツェナ耐圧を安定し
て得ることができる。このとき、リンガラス層２０の厚
さをシリコン酸化膜１９の厚さ以上にするとより好まし
い。The phosphorus glass layer 2 is formed on the silicon oxide film 19.
When 0 is formed, mobile ions are trapped and the effect of preventing the influence of mobile ions is strong, so that the Zener breakdown voltage can be stably obtained. At this time, it is more preferable that the thickness of the phosphorus glass layer 20 be equal to or larger than the thickness of the silicon oxide film 19.
【００２０】この半導体装置の構造の特徴とその特徴が
特性等に与える効果を述べる。ツェナ領域１５の深さは
ベース領域１３の深さと同じか浅くする。ツェナ領域１
５の深さをベース領域１３より深くすると、コレクタ領
域１２とエミッタ領域１６間の耐圧が低くなり、Ｌ負荷
耐量が低下するためである。また、ツェナ領域１５の幅
は外側ベース領域１３ｂと内周ベース領域１３ａから延
びる空乏層同志が互いに重なり合わない様な幅に設計す
る。空乏層の延びは不純物濃度が低い程大きい。したが
って、ツェナ領域１５を拡散で形成しているので、ツェ
ナ領域１５内の下方程不純物濃度が低くなる。したがっ
て、空乏層が重なり合うのは貫通領域１４の下端から始
まる。空乏層同志が互いに重なり合うと、その領域より
上のツェナ領域１５ではブレークダウンは起こらず、ベ
ース領域１３底面と貫通領域１４のコーナの境界で起こ
る。この領域でブレークダウンするとサージ破壊がおこ
りやすい。また、空乏層同志が重なりあわないように十
分広くしすぎると半導体装置のペレットサイズが大きく
なる。The features of the structure of the semiconductor device and the effects of the features on the characteristics and the like will be described. The depth of the Zener region 15 is the same as or shallower than the depth of the base region 13. Zena area 1
This is because if the depth of 5 is deeper than the base region 13, the withstand voltage between the collector region 12 and the emitter region 16 decreases, and the L load resistance decreases. The width of the Zener region 15 is designed so that the depletion layers extending from the outer base region 13b and the inner peripheral base region 13a do not overlap each other. The extension of the depletion layer increases as the impurity concentration decreases. Therefore, since the Zener region 15 is formed by diffusion, the impurity concentration becomes lower in the Zener region 15 below. Therefore, the overlapping of the depletion layers starts from the lower end of the through region 14. When the depletion layers overlap each other, breakdown does not occur in the Zener region 15 above that region, but occurs at the boundary between the bottom surface of the base region 13 and the corner of the through region 14. If breakdown occurs in this region, surge breakdown is likely to occur. On the other hand, if the width of the depletion layer is too large so as not to overlap, the pellet size of the semiconductor device becomes large.
【００２１】ベース電極１８は外側ベース領域１３ｂの
外周とコレクタ領域１２の境界を越えた絶縁膜２１上ま
で形成してもよい。このとき、外側ベース領域１３ｂの
外側のコレクタ領域１２の絶縁膜２１の下に空乏層が延
びて、コレクタ領域１２上に延在したベース電極１８の
長さのバラツキにより耐圧が不安定になっても、このと
きの最も低い耐圧よりツェナ領域１５の耐圧が低くなる
ように、ツェナ領域１５の不純物濃度をしておけばよ
い。The base electrode 18 may be formed on the insulating film 21 beyond the boundary between the outer base region 13b and the collector region 12. At this time, the depletion layer extends below the insulating film 21 in the collector region 12 outside the outer base region 13b, and the breakdown voltage becomes unstable due to the variation in the length of the base electrode 18 extending over the collector region 12. However, the impurity concentration of the Zener region 15 may be set so that the breakdown voltage of the Zener region 15 is lower than the lowest breakdown voltage at this time.
【００２２】さらに、ツェナ領域１５と絶縁膜２１とベ
ース電極１８はいわゆるＭＯＳ構造となっており、コレ
クタ、ベース間に逆電圧が印加された場合に絶縁膜２１
が薄いと所望のツェナ耐圧に達する前にツェナ領域１５
の表面が反転する。このため、ツェナ耐圧を決定するツ
ェナ領域１５の空乏層がツェナ領域１５のＮ型不純物の
濃度に係わらず延びなくなり、その他の領域で最も耐圧
の低い領域でブレークダウンする。その結果、ツェナ耐
圧が高くなり所望のツェナ耐圧が得ることができない。
しかし、所望のツェナ耐圧値以下ではツェナ領域１５の
表面が反転しないように絶縁膜２１の厚さを形成するこ
とにより、絶縁膜２１の下のツェナ領域１５のＮ型不純
物の濃度で決まる空乏層でブレークダウンするので、ツ
ェナ耐圧をコントロールすることができる。その結果安
定したツェナ耐圧が得られる。この反転層が発生する場
合と発生しない場合の、耐圧とツェナ領域１５の不純物
濃度関係を図３に示す。Further, the Zener region 15, the insulating film 21 and the base electrode 18 have a so-called MOS structure, and when a reverse voltage is applied between the collector and the base, the insulating film 21 is formed.
Is thinner, the Zener region 15 is not reached before the desired Zener breakdown voltage is reached.
Surface is inverted. For this reason, the depletion layer of the zener region 15 that determines the zener breakdown voltage does not extend regardless of the concentration of the N-type impurity in the zener region 15, and breaks down in the other region having the lowest breakdown voltage. As a result, the Zener breakdown voltage becomes high, and a desired Zener breakdown voltage cannot be obtained.
However, by forming the thickness of the insulating film 21 so that the surface of the Zener region 15 is not inverted below the desired Zener breakdown voltage value, the depletion layer determined by the concentration of the N-type impurity in the Zener region 15 under the insulating film 21 is formed. , The Zener breakdown voltage can be controlled. As a result, a stable Zener breakdown voltage can be obtained. FIG. 3 shows the relationship between the breakdown voltage and the impurity concentration of the Zener region 15 when this inversion layer is generated and when it is not generated.
【００２３】図に示すように、絶縁膜２１の薄い構造で
はツェナ領域の不純物濃度の変化に対する耐圧の変化が
大きいので、耐圧の高い領域での耐圧のコントロールが
困難であった。一方、本発明の絶縁膜の厚い構造では耐
圧の高い領域でも、ツェナ領域１５の不純物濃度の変化
に対する耐圧の変化は緩やかであり、耐圧のコントロー
ルが容易にできる。以上によりコレクターベース間に逆
電圧が印加された場合ツェナ耐圧の変動が生じにくく、
かつ安定した耐圧のトタンジスタを得ることができる。As shown in the figure, in a thin structure of the insulating film 21, since the change in the withstand voltage with respect to the change in the impurity concentration in the zener region is large, it is difficult to control the withstand voltage in the region with a high withstand voltage. On the other hand, in the thick structure of the insulating film of the present invention, even in a region having a high withstand voltage, the change in the withstand voltage with respect to the change in the impurity concentration of the zener region 15 is gradual, and the withstand voltage can be easily controlled. As described above, when a reverse voltage is applied between the collector and the base, the Zener breakdown voltage hardly fluctuates,
Further, a stable withstand voltage transistor can be obtained.
【００２４】ここでは一導電型をＮ型とし他導電型をＰ
型として、ＮＰＮトランジスタについて説明したが、一
導電型をＰ型とし他導電型をＮ型として、ＰＮＰトラン
ジスタにも適用できる。Here, one conductivity type is N type and the other conductivity type is P type.
Although an NPN transistor has been described as a type, the present invention can also be applied to a PNP transistor where one conductivity type is a P type and the other conductivity type is an N type.
【００２５】［発明の実施の形態２］本発明の第２の実
施の形態について図４の半導体装置の側断面図、図５の
図４のＡ−Ａでの断面図を用いて説明する。[Embodiment 2] A second embodiment of the present invention will be described with reference to a side sectional view of a semiconductor device of FIG. 4 and a sectional view taken along line AA of FIG. 4 of FIG.
【００２６】３１はシリコンからなる一導電型即ちＮ＋
型半導体基板、３２はＮ−型コレクタ領域、３３は他導
電型即ちＰ型ベース領域、３４は貫通領域、３５はＮ型
ツェナ領域、３６はＮ＋型エミッタ領域、３７はエミッ
タ電極、３８はベース電極、３９はシリコン酸化膜、４
０はリンガラス層、４１は絶縁膜で、シリコン酸化膜３
９とその上に形成したリンガラス層４０とを合わせたも
のである。Reference numeral 31 denotes one conductivity type of silicon, ie, N +
Type semiconductor substrate, 32 is an N- type collector region, 33 is another conductivity type, that is, a P type base region, 34 is a through region, 35 is an N type Zener region, 36 is an N + type emitter region, 37 is an emitter electrode, and 38 is a base. Electrode, 39 is a silicon oxide film, 4
0 is a phosphorus glass layer, 41 is an insulating film, and a silicon oxide film 3
9 and the phosphor glass layer 40 formed thereon.
【００２７】この半導体装置の構造を製造方法を交えて
説明する。Ｎ＋型半導体基板３１の主面にエピタキシャ
ル成長により、Ｎ−型コレクタ領域３２を形成する。コ
レクタ領域３２の表面にフォトリソグラフィを用いてボ
ロンをイオン注入した後に、熱拡散で角が丸い４角形の
Ｐ型ベース領域３３を形成する。このとき、ベース領域
３３にベース領域３３とコレクタ領域３２との境界近傍
に沿ってベース領域３３の表面から底面にかけて、角が
丸く、かつ同じ幅のリング状のボロンが拡散されない貫
通領域３４を形成する。ベース領域３３も貫通領域３４
も角が丸くなくてもよい。また、円形でも楕円形でもよ
い。つづいて、フォトリソグラフィを用いてこの貫通領
域３４にリンをイオン注入した後に、熱拡散でベース領
域３３より浅く、コレクタ領域３２より濃度の濃いＮ型
ツェナ領域３５を形成する。したがって、ツェナ領域３
５の下にはＮ−型の貫通領域３４が残る。The structure of this semiconductor device will be described together with the manufacturing method. An N- type collector region 32 is formed on the main surface of the N + type semiconductor substrate 31 by epitaxial growth. After boron ions are implanted into the surface of the collector region 32 using photolithography, a quadrangular P-type base region 33 having rounded corners is formed by thermal diffusion. At this time, in the base region 33, from the surface to the bottom surface of the base region 33 along the vicinity of the boundary between the base region 33 and the collector region 32, a ring-shaped through region 34 having a rounded corner and the same width and in which boron is not diffused is formed. I do. Base region 33 is also penetrating region 34
Also, the corners need not be round. Further, the shape may be circular or elliptical. Subsequently, after the phosphorus is ion-implanted into the through region 34 using photolithography, an N-type zener region 35 which is shallower than the base region 33 and has a higher concentration than the collector region 32 is formed by thermal diffusion. Therefore, the zener region 3
5, an N-type penetrating region 34 remains.
【００２８】つづいて、熱酸化により表面全面にシリコ
ン酸化膜３９を形成する。ＣＶＤにより形成してもよ
い。また、窒化膜でもよい。つづいて、フォトリソグラ
フィを用いて、ツェナ領域３５より内側ベース領域３３
ａの表面にリン拡散してエミッタ領域３６を形成する。
ツェナ領域３５が内側ベース領域３３ａを介してエミッ
タ領域を囲んだ形状になる。このとき、シリコン酸化膜
３９上にリンガラス層４０が形成される。さらに、必要
に応じてリンガラス層４０をＣＶＤで積層して厚くして
もよい。Subsequently, a silicon oxide film 39 is formed on the entire surface by thermal oxidation. It may be formed by CVD. Further, a nitride film may be used. Subsequently, the base region 33 inside the zener region 35 is formed using photolithography.
The emitter region 36 is formed by diffusing phosphorus on the surface of a.
The Zener region 35 has a shape surrounding the emitter region via the inner base region 33a. At this time, a phosphorus glass layer 40 is formed on the silicon oxide film 39. Further, if necessary, the phosphorus glass layer 40 may be laminated by CVD to increase the thickness.
【００２９】つづいて、フォトリソグラフィとアルミ蒸
着を用いてベース領域３３とエミッタ領域３６のコンタ
クト領域にベース電極３８とエミッタ電極３７を形成す
る。このとき、ツェナ領域３５上を絶縁膜４１を介して
ベース電極３８で覆い、内側ベース領域３３ａとツェナ
領域３５の外側の外側ベース領域３３ｂをベース電極３
８で電気的に接続する。また、外側ベース領域３３ｂを
ベース電極３８で電気的に接続せず外側ベース領域３３
ｂの上も絶縁膜４１を介してベース電極３８で覆っても
よい。いずれの場合も、ベース電極３８を外側ベース領
域３３ｂを越えてコレクタ領域３２の絶縁膜４１上に形
成してもよい。また、トランジスタを動作させるとき
は、エミッタ領域３６とベ−ス領域３３の電位差はＶBE
であるので、エミッタ電極３７でツェナ領域３５上を絶
縁膜４１を介してもよい。さらに、コレクタ領域３２上
の絶縁膜４１上まで覆ってもよい。Subsequently, a base electrode 38 and an emitter electrode 37 are formed in the contact region between the base region 33 and the emitter region 36 by using photolithography and aluminum evaporation. At this time, the zener region 35 is covered with the base electrode 38 via the insulating film 41, and the inner base region 33 a and the outer base region 33 b outside the zener region 35 are connected to the base electrode 3.
8 to make an electrical connection. Further, the outer base region 33b is not electrically connected to the
b may be covered with the base electrode 38 via the insulating film 41. In any case, the base electrode 38 may be formed on the insulating film 41 in the collector region 32 beyond the outer base region 33b. When the transistor is operated, the potential difference between the emitter region 36 and the base region 33 is VBE
Therefore, the emitter electrode 37 may be provided on the zener region 35 via the insulating film 41. Further, the insulating film 41 on the collector region 32 may be covered.
【００３０】上記構造でエミッタ領域３６、ベース領域
３３、コレクタ領域３２がエミッタ、ベース、コレクタ
としてＮＰＮトランジスタを構成し、ツェナ領域３５、
ベース領域３３をカソード、アノードとしてコレクタ、
ベース間にツェナダイオードを構成する。In the above structure, the emitter region 36, the base region 33 and the collector region 32 constitute an NPN transistor as an emitter, a base and a collector.
A collector using the base region 33 as a cathode and an anode,
A zener diode is formed between the bases.
【００３１】この構造において、絶縁膜４１の厚さを所
望の耐圧以下で、絶縁膜４１の下のツェナ領域３５の表
面に反転層が形成しない厚さ以上にする。このときの絶
縁膜４１の厚さおよび構成は実施の形態１で示した通り
になる。In this structure, the thickness of the insulating film 41 is made equal to or less than a desired withstand voltage and equal to or more than the thickness at which the inversion layer is not formed on the surface of the zener region 35 under the insulating film 41. The thickness and configuration of the insulating film 41 at this time are as described in the first embodiment.
【００３２】この半導体装置の構造の特徴とその特徴が
特性等に与える効果を発明の実施の形態１と異なる事項
についてのみ述べる。ベース電極３８で外側ベース領域
３３ｂと内側ベース領域を電気的に接続しないときは、
接続したときのツェナ領域３５の幅の略１／２にするこ
とができる。これは外側ベース領域３３とツェナ領域３
５間では空乏層ができないためである。The features of the structure of the semiconductor device and the effects of the features on the characteristics and the like will be described only for matters different from the first embodiment of the present invention. When the outer base region 33b and the inner base region are not electrically connected by the base electrode 38,
The width can be reduced to approximately の of the width of the Zener region 35 when connected. This is because the outer base region 33 and the zener region 3
This is because a depletion layer cannot be formed between the five layers.
【００３３】ここでは一導電型をＮ型とし他導電型をＰ
型として、ＮＰＮトランジスタについて説明したが、一
導電型をＰ型とし他導電型をＮ型として、ＰＮＰトラン
ジスタにも適用できる。Here, one conductivity type is N type and the other conductivity type is P type.
Although an NPN transistor has been described as a type, the present invention can also be applied to a PNP transistor where one conductivity type is a P type and the other conductivity type is an N type.
【００３４】[0034]
【発明の効果】本発明はツェナーダイオードの不純物領
域がベース領域に囲まれ、表面部分をツェナー電圧以下
では反転しない厚さを有する絶縁膜を介してベース電極
で覆っているため、酸化膜や外装樹脂中の可動イオンの
影響を受けにくく、ツェナダイオードの不純物領域の不
純物濃度で容易にコントロールできる安定したツェナ耐
圧のトランジスタを得ることができる。According to the present invention, the impurity region of the Zener diode is surrounded by the base region, and the surface portion is covered with the base electrode via an insulating film having a thickness that does not reverse below the Zener voltage. It is possible to obtain a transistor having a stable Zener withstand voltage which is hardly affected by mobile ions in the resin and can be easily controlled by the impurity concentration of the impurity region of the Zener diode.
【００３５】また、シリコン酸化膜の上にリンガラス層
を形成したので、可動イオンのトラップが確実になさ
れ、安定したツェナ耐圧のトランジスタを得ることがで
きる。Further, since the phosphorus glass layer is formed on the silicon oxide film, trapping of mobile ions is ensured, and a transistor having a stable Zener breakdown voltage can be obtained.
【図１】 本発明の第１の実施の形態の半導体装置の側
断面図FIG. 1 is a side sectional view of a semiconductor device according to a first embodiment of the present invention;
【図２】 図１のＡ−Ａ部断面図FIG. 2 is a sectional view taken along the line AA of FIG. 1;
【図３】 耐圧とツェナ領域の不純物濃度との関係FIG. 3 shows a relationship between a breakdown voltage and an impurity concentration in a zener region.
【図４】 本発明の第２の実施の形態の半導体装置の側
断面図FIG. 4 is a side sectional view of a semiconductor device according to a second embodiment of the present invention;
【図５】 図４のＡ−Ａ部断面図FIG. 5 is a sectional view taken along the line AA in FIG . 4 ;
【図６】 従来の半導体装置の側断面図FIG. 6 is a side sectional view of a conventional semiconductor device.
１１、３１ 半導体基板 １２、３２ コレクタ領域 １３、３３ ベース領域 １４、３４ 貫通領域 １５、３５ ツェナ領域 １６、３６ エミッタ領域 １７、３７ エミッタ電極 １８、３８ ベース電極 １９、３９ シリコン酸化膜 ２０、４０ リンガラス層 ２１、４１ 絶縁膜 11, 31 Semiconductor substrate 12, 32 Collector region 13, 33 Base region 14, 34 Penetration region 15, 35 Zener region 16, 36 Emitter region 17, 37 Emitter electrode 18, 38 Base electrode 19, 39 Silicon oxide film 20, 40 Phosphorus Glass layer 21, 41 Insulating film
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平７−122712（ＪＰ，Ａ) 特開 昭61−40062（ＪＰ，Ａ) 特開 昭59−123262（ＪＰ，Ａ) 特開 昭59−123261（ＪＰ，Ａ) 特開 昭57−128963（ＪＰ，Ａ) 特開 昭55−59769（ＪＰ，Ａ) 特開 平９−17804（ＪＰ，Ａ) 実開 昭62−204352（ＪＰ，Ｕ) 実開 昭58−168149（ＪＰ，Ｕ) 実公 昭51−38289（ＪＰ，Ｙ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/06 H01L 29/73 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-122712 (JP, A) JP-A-61-40062 (JP, A) JP-A-59-123262 (JP, A) JP-A-59-123 123261 (JP, A) JP-A-57-128963 (JP, A) JP-A-55-59769 (JP, A) JP-A-9-17804 (JP, A) JP-A-62-204352 (JP, U) Japanese Utility Model Application Sho 58-168149 (JP, U) Japanese Utility Model Application Sho 51-38289 (JP, Y1) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 27/06 H01L 29/73
Claims (7)
に形成した他導電型ベース領域と、このベース領域内の
表面に形成した一導電型エミッタ領域と、前記各領域の
表面に形成した絶縁膜の前記ベース領域と前記エミッタ
領域にコンタクト用の窓をあけて形成したベース電極と
エミッタ電極とを具備する半導体装置において、 前記ベース領域に表面から底部に抜けた他導電型不純物
を拡散しない貫通領域を形成し、この貫通領域に前記コ
レクタ領域より高濃度の一導電型不純物のツェナ領域を
設け、少なくとも前記ツェナ領域上に前記ベース領域と
前記ツェナ領域間の耐圧で前記ツェナ領域表面が反転し
ない厚さの絶縁膜を設け、前記ベース電極または前記エ
ミッタ電極で前記ツェナ領域上の前記絶縁膜を介して被
覆したことを特徴とする半導体装置。1. A base region of another conductivity type formed on a surface of a collector region of a semiconductor substrate of one conductivity type, an emitter region of one conductivity type formed on a surface within the base region, and an insulation formed on a surface of each of the regions. In a semiconductor device having a base electrode and an emitter electrode formed by opening a contact window in the base region and the emitter region of a film, the other conductive type impurity which has escaped from the surface to the bottom in the base region
Forming a through region not diffuse, through the through region provided with the zener region of high concentration of one conductivity type impurity than the collector region, said zener region in breakdown voltage between said base region at least in said zener region said zener region A semiconductor device, comprising: an insulating film having a thickness whose surface is not inverted, and covered with the base electrode or the emitter electrode via the insulating film on the zener region.
クタ領域との表面の境界近傍に沿って、かつ前記エミッ
タ領域を囲んで形成したことを特徴とする請求項１記載
の半導体装置。2. The semiconductor device according to claim 1, wherein said through region is formed along a vicinity of a boundary between surfaces of said base region and said collector region and surrounding said emitter region.
するように複数に分割して形成したことを特徴とする請
求項２記載の半導体装置。3. The semiconductor device according to claim 2, wherein said through region is divided into a plurality of parts so as to divide a direction along said boundary.
に形成した他導電型ベース領域と、このベース領域内の
表面に形成した一導電型エミッタ領域と、前記各領域の
表面に形成した絶縁膜の前記ベース領域と前記エミッタ
領域にコンタクト用の窓をあけて形成したベース電極と
エミッタ電極とを具備する半導体装置において、 前記ベース領域に前記ベース領域と前記コレクタ領域と
の境界に沿って、かつ前記エミッタ領域を囲んで表面か
ら底部に抜けた他導電型不純物を拡散しない貫通領域を
形成し、この貫通領域に前記半導体基板より高濃度の一
導電型不純物のツェナ領域を形成し、前記絶縁膜を少な
くとも前記ツェナ領域上には前記ベース領域と前記ツェ
ナ領域間の耐圧で前記ツェナ領域表面が反転しない厚さ
に形成し、前記ツェナ領域の内側のベース領域と外側の
ベース領域を前記ツェナ領域上の前記絶縁膜を介して前
記ベース電極で電気的に接続したことを特徴とする半導
体装置。4. A base region of another conductivity type formed on the surface of the collector region of the semiconductor substrate of one conductivity type, an emitter region formed on the surface of the base region, and an insulation region formed on the surface of each region. In a semiconductor device having a base electrode and an emitter electrode formed by opening a contact window in the base region and the emitter region of a film, the base region extends along a boundary between the base region and the collector region, And forming a penetrating region surrounding the emitter region and not diffusing impurities of another conductivity type that has escaped from the surface to the bottom, and forming a zener region of one conductivity type impurity at a higher concentration than the semiconductor substrate in the penetrating region; A film is formed on at least the zener region to a thickness such that the surface of the zener region is not inverted by a withstand voltage between the base region and the zener region. A semiconductor device, wherein a base region inside a region and a base region outside the region are electrically connected by the base electrode via the insulating film on the zener region.
形成したことを特徴とする請求項１、請求項２、請求項
３または請求項４記載の半導体装置。5. The semiconductor device according to claim 1, wherein said Zener region is formed shallower than said base region.
ンガラス層で形成したことを特徴とする請求項１、請求
項２、請求項３、請求項４または請求項５記載の半導体
装置。6. The semiconductor device according to claim 1, wherein said insulating film is formed of a silicon oxide film and a phosphorus glass layer thereon. .
記ベース領域から延びる空乏層より広くしたことを特徴
とする請求項１、請求項２、請求項３、請求項４、請求
項５または請求項６記載の半導体装置。7. The semiconductor device according to claim 1, wherein the width of the through region is wider than a depletion layer extending from the base region surrounding the through region. Or the semiconductor device according to claim 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16910696A JP3180672B2 (en) | 1996-06-28 | 1996-06-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16910696A JP3180672B2 (en) | 1996-06-28 | 1996-06-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1022395A JPH1022395A (en) | 1998-01-23 |
| JP3180672B2 true JP3180672B2 (en) | 2001-06-25 |
Family
ID=15880422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16910696A Expired - Fee Related JP3180672B2 (en) | 1996-06-28 | 1996-06-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3180672B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4834305B2 (en) * | 2005-01-13 | 2011-12-14 | パナソニック株式会社 | Semiconductor device |
| JP4834306B2 (en) * | 2005-01-13 | 2011-12-14 | パナソニック株式会社 | Semiconductor device |
| JP5253742B2 (en) * | 2007-02-20 | 2013-07-31 | 新日本無線株式会社 | ESD protection device for vertical PNP bipolar transistor |
| DE112010005272B4 (en) * | 2010-02-16 | 2014-12-24 | Sansha Electric Manufacturing Co., Ltd. | PIN Diodes |
| CN102687276B (en) * | 2010-02-17 | 2015-03-11 | 株式会社三社电机制作所 | Pin diode |
-
1996
- 1996-06-28 JP JP16910696A patent/JP3180672B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1022395A (en) | 1998-01-23 |
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