JP3231888U - Physical dry surface treatment structure of semiconductor wafer - Google Patents

Physical dry surface treatment structure of semiconductor wafer Download PDF

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JP3231888U
JP3231888U JP2021000566U JP2021000566U JP3231888U JP 3231888 U JP3231888 U JP 3231888U JP 2021000566 U JP2021000566 U JP 2021000566U JP 2021000566 U JP2021000566 U JP 2021000566U JP 3231888 U JP3231888 U JP 3231888U
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semiconductor wafer
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謝燿吉
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Hui Ter Co Ltd
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Abstract

【課題】半導体基板表面の除去、研磨又は減厚の効率を高め、迅速かつ安全で破片が生じにくく、環境を汚染せず、作業員が安全に作業することもできる半導体ウェハの物理的乾式表面処理構造を提供する。【解決手段】半導体ウェハの物理的乾式表面処理構造は、少なくとも1つの軟質弾性キャリア50と、複数の硬質微粒子55とを備える。軟質弾性キャリア50の表面には、硬質微粒子55が設けられる。軟質弾性キャリア50は、粘着性を有する弾性材料からなる。軟質弾性キャリア50の粒径は10μm〜150μmである。硬質微粒子55の粒径は、米国材料試験協会の規格によるメッシュ数が1500〜30000である。軟質弾性キャリア50は、プラスチック、ゴム、シリカゲルを基材の原料としてつくった軟質弾性複合物からなる。硬質微粒子55は、天然ダイヤモンド、人工ダイヤモンド又はその混合物からなる。【選択図】図3PROBLEM TO BE SOLVED: To improve the efficiency of removing, polishing or thinning a surface of a semiconductor substrate, to quickly and safely generate debris, to pollute the environment, and to allow workers to work safely on a physically dry surface of a semiconductor wafer. Provides a processing structure. A physical dry surface-treated structure of a semiconductor wafer includes at least one soft elastic carrier 50 and a plurality of hard fine particles 55. Hard fine particles 55 are provided on the surface of the soft elastic carrier 50. The soft elastic carrier 50 is made of an elastic material having adhesiveness. The particle size of the soft elastic carrier 50 is 10 μm to 150 μm. As for the particle size of the hard fine particles 55, the number of meshes according to the standard of the American Society for Testing and Materials is 1500 to 30000. The soft elastic carrier 50 is made of a soft elastic composite made of plastic, rubber, or silica gel as a raw material of a base material. The hard fine particles 55 consist of natural diamond, artificial diamond or a mixture thereof. [Selection diagram] Fig. 3

Description

本考案は、半導体基板の表面処理技術に関し、特に、半導体基板表面の除去、研磨又は減厚の効率を高め、迅速かつ安全で破片が生じにくく、作業する際に化学液体又は水を使用しなくてもよいため、環境を汚染せず、作業員が安全に作業することができる、半導体ウェハの物理的乾式表面処理構造に関する。 The present invention relates to a semiconductor substrate surface treatment technique, in particular, improves the efficiency of removing, polishing or thickening the surface of a semiconductor substrate, is quick and safe, is less prone to debris, and does not use chemical liquids or water when working. Therefore, the present invention relates to a physical dry surface treatment structure of a semiconductor wafer, which does not pollute the environment and allows workers to work safely.

半導体装置の集積回路(Integrated Circuit)の技術は急速に発展して成熟し、半導体産業は大きな発展を遂げた産業の一つとなっている。半導体ウェハは、シリコンウェハなどの基板に対して成膜、露光、エッチング、研削、洗浄など複数の製造工程を行って製造される。従来、ウェハメーカは、大量生産する際、3割又はそれ以上の割合のモニターウェハ(Monitor Wafer)及びダミーウェハ(Dummy Wafer)を使用しなければならず、ASIC(Application−Specific−Integrated Circuit)を生産する場合、4割以上のモニターウェハ及びダミーウェハを使用しなければならなかった。初期のダミーウェハは、使用後、不要となったウェハと一緒に廃棄されていたため、有毒な産業廃棄物が生じていた。その後、産業の急速な発展に伴い、ウェハ材料が大型化され、それにかかるコストも徐々に多くなってきており、再生ウェハ(Reclaimed Wafer)産業も徐々に発展してきており、使用済みのモニターウェハ及び廃棄ウェハの上面のめっき膜(例えば、絶縁薄膜又は金属薄膜)などの回路パターンを研削、研磨すると、再利用することができる。 The technology of integrated circuits of semiconductor devices has rapidly developed and matured, and the semiconductor industry has become one of the industries that have made great progress. A semiconductor wafer is manufactured by performing a plurality of manufacturing processes such as film formation, exposure, etching, grinding, and cleaning on a substrate such as a silicon wafer. Conventionally, a wafer maker has to use a monitor wafer (Motor Wafer) and a dummy wafer (Dummy Wafer) at a ratio of 30% or more in mass production, and produces an ASIC (Application-Specific-Integrated Circuit). In that case, 40% or more of monitor wafers and dummy wafers had to be used. Early dummy wafers were discarded with unnecessary wafers after use, resulting in toxic industrial waste. Since then, with the rapid development of the industry, the wafer material has become larger and the cost has gradually increased, and the recycled wafer industry has also gradually developed, and used monitor wafers and used monitor wafers and When a circuit pattern such as a plating film (for example, an insulating thin film or a metal thin film) on the upper surface of a waste wafer is ground and polished, it can be reused.

従来の半導体ウェハの再生ウェハ方式では、主にウェットエッチング(Wet Etching)技術により、ウェハ表面のめっき膜(例えば、SiO2、Si3N4などの絶縁薄膜又はAl、Cu、Tiなどの金属めっき膜)を除去し、半導体ウェハの表面をラッピング(lapping)及び/又は研削(grinding)してから化学機械研磨(Chemical Mechanical Polish:CMP)を行うか、化学機械研磨を直接行って平坦化し、最終的にウェハ表面を元の状態にしてから、半導体ウェハを所定の厚さ以下にして再利用できるようにしてもよい。 In the conventional recycled wafer method for semiconductor wafers, the plating film on the wafer surface (for example, an insulating thin film such as SiO2 or Si3N4 or a metal plating film such as Al, Cu, Ti) is removed mainly by wet etching technology. Then, the surface of the semiconductor wafer is wrapped and / or grounded and then subjected to chemical mechanical polishing (CMP) or directly subjected to chemical mechanical polishing to flatten the wafer surface. The semiconductor wafer may be reduced to a predetermined thickness or less so that the wafer can be reused.

しかし、めっき膜の組成成分の違いに応じて、それぞれ異なる腐蝕性液体(例えば、フッ化水素酸)を使用して再生ウェハをエッチングしなければならなかったため、エッチング工程の複雑度が上がり、その過程で有毒ガスが発生することもあった。そのため、製造工程の安全性に問題があった。また、腐蝕性液体は、めっき膜組成の違いに応じて腐蝕効率が異なるため、再生ウェハの表面厚さが不均一となる問題が生じやすく、ウェットエッチングされた再生ウェハの表面に、腐蝕液により溶解された金属イオン又は不純物が付着し、汚染物が再生ウェハの表面に残留してしまうことがあった。そのため、まず、残留した汚染物を除去してから後続の製造工程を行わなければならず、製造コストが大きな負担となっていた。この他、化学機械研磨は、研磨廃液、研磨汚泥などの廃棄物が発生し、これらの化学廃棄物も我々の環境を汚染させ、有毒な化学廃液により生態環境が汚染されることを防ぐために、エッチング又は化学機械研磨の過程で発生した化学廃液は不用意に排出することはできなかった。そのため、製造メーカにとっては、化学廃液の回収処理作業、設備及び人件費にさらにコストがかかり、大きな負担となっていた。 However, since the recycled wafer had to be etched using different corrosive liquids (for example, hydrofluoric acid) depending on the composition components of the plating film, the complexity of the etching process increased. Toxic gas was sometimes generated in the process. Therefore, there is a problem in the safety of the manufacturing process. Further, since the corrosive liquid has different corrosive efficiencies depending on the difference in the plating film composition, the problem that the surface thickness of the recycled wafer becomes non-uniform is likely to occur, and the surface of the wet-etched recycled wafer is exposed to the corrosive liquid. Dissolved metal ions or impurities may adhere and the contaminants may remain on the surface of the recycled wafer. Therefore, it is necessary to first remove the residual contaminants and then perform the subsequent manufacturing process, which imposes a heavy burden on the manufacturing cost. In addition, chemical mechanical polishing produces waste such as polishing waste liquid and polishing sludge, and these chemical wastes also pollute our environment, and in order to prevent the ecological environment from being polluted by toxic chemical waste liquid. The chemical waste liquid generated in the process of etching or chemical mechanical polishing could not be discharged carelessly. Therefore, for the manufacturer, the recovery processing work of the chemical waste liquid, the equipment, and the labor cost are further costly, which is a heavy burden.

特許文献1〜3で使用されている乾式サンドブラスト方式は、ウェハ表面のめっき膜を除去し、エッチング又は研削により除去されためっき膜が問題を発生させることを防ぐことができた。しかし、図1に示すように、サンドブラストには、天然ダイヤモンド、人工ダイヤモンド、炭化タングステン、炭化ホウ素などの硬質材が研削材料として使用され、その粒径が約1μm〜10μmであるが、サンドブラスト材料20の噴出速度が速く、ウェハ10の表面15に吹付けられる時間が非常に短いため、ウェハ10内に内部応力が形成され、ウェハ10を損傷させて収率を低下させる虞があった。また、ウェハ10の厚さが小さめであったため、クラックが発生したり割れたりし、研削効果が好ましくないため、めっき膜を除去した後のウェハ10の表面15が平坦でない上(図2を参照する)、残留金属めっき膜Aがあるため、後続工程において化学機械研磨により平坦化させる必要があった。 The dry sandblasting method used in Patent Documents 1 to 3 can remove the plating film on the wafer surface and prevent the plating film removed by etching or grinding from causing a problem. However, as shown in FIG. 1, hard materials such as natural diamond, artificial diamond, tungsten carbide, and boron carbide are used as grinding materials for sandblasting, and the particle size is about 1 μm to 10 μm, but the sandblasting material 20 Since the ejection speed of the wafer 10 is high and the time for spraying on the surface 15 of the wafer 10 is very short, internal stress may be formed in the wafer 10 to damage the wafer 10 and reduce the yield. Further, since the thickness of the wafer 10 is small, cracks are generated or cracked, and the grinding effect is not preferable. Therefore, the surface 15 of the wafer 10 after removing the plating film is not flat (see FIG. 2). Because of the residual metal plating film A, it was necessary to flatten it by chemical mechanical polishing in the subsequent process.

言い換えると、従来の半導体ウェハは、除去、研磨、減厚などの表面処理を行う際、技術的にニーズを完全に満たすことができず、製造工程が複雑である上、除去、研磨又は減厚に多くの時間がかかり、製造装置が高価であり、破損率が高くて収率が低い問題がある上、大量の廃液処理の問題もあった。そのため、それら従来技術の問題点を改善することができる技術が求められていた。 In other words, conventional semiconductor wafers cannot completely meet technical needs when performing surface treatments such as removal, polishing, and thickness reduction, the manufacturing process is complicated, and removal, polishing, or thickness reduction is performed. It takes a lot of time, the manufacturing equipment is expensive, the damage rate is high, the yield is low, and there is also a problem of processing a large amount of waste liquid. Therefore, there has been a demand for a technique capable of improving the problems of these conventional techniques.

台湾実用新案公告第M320168号公報Taiwan Utility Model Announcement No. M320168 台湾実用新案公告第M324847号公報Taiwan Utility Model Announcement No. M324847 台湾特許出願公開第200524031号公報Taiwan Patent Application Publication No. 20054031

本考案の第1の目的は、再生ウェハの表面処理工程を簡素化するとともに、表面加工精度を高め、表面に粗さを改善し、表面処理にかかる時間を短縮することができる、半導体ウェハの物理的乾式表面処理構造を提供することにある。
本考案の第2の目的は、化学薬品による汚染を減らし、廃液処理の工程及び設備を省略することができ、再生ウェハの製造工程は、環境汚染を防いで安全性が高い、半導体ウェハの物理的乾式表面処理構造を提供することにある。
本考案の第3の目的は、研削するときの緩圧作用が好ましく、再生ウェハの表面を除去するときの変質層を減らし、ウェハにクラックが発生することを減らし、製造工程全体の収率を高めることができる、半導体ウェハの物理的乾式表面処理構造を提供することにある。
The first object of the present invention is to simplify the surface treatment process of a recycled wafer, improve the surface processing accuracy, improve the surface roughness, and shorten the time required for the surface treatment of the semiconductor wafer. The purpose is to provide a physical dry surface treatment structure.
The second object of the present invention is to reduce the contamination by chemicals, omit the waste liquid treatment process and equipment, and the recycled wafer manufacturing process is the physics of the semiconductor wafer, which prevents environmental pollution and is highly safe. The purpose is to provide a dry surface treatment structure.
The third object of the present invention is that the slow pressure action at the time of grinding is preferable, the alteration layer at the time of removing the surface of the recycled wafer is reduced, the occurrence of cracks in the wafer is reduced, and the yield of the entire manufacturing process is improved. It is an object of the present invention to provide a physical dry surface treatment structure of a semiconductor wafer which can be enhanced.

こうした現状に鑑み、本考案者は鋭意研究を重ねた結果、従来技術の問題点を改善し、本考案を完成させたものである。
上記課題を解決するために、本考案の第1の形態によれば、少なくとも1つの軟質弾性キャリアと、複数の硬質微粒子とを備えた、半導体ウェハの物理的乾式表面処理構造であって、前記軟質弾性キャリアの表面には、前記硬質微粒子が設けられ、前記軟質弾性キャリアは、粘着性を有する弾性材料からなり、前記軟質弾性キャリアの粒径は10μm〜150μmであり、前記硬質微粒子の粒径は、米国材料試験協会の規格によるメッシュ数が1500〜30000であることを特徴とする、半導体ウェハの物理的乾式表面処理構造を提供する。
In view of this situation, the present inventor has completed the present invention by improving the problems of the prior art as a result of repeated diligent research.
In order to solve the above problems, according to the first aspect of the present invention, there is a physical dry surface treatment structure of a semiconductor wafer including at least one soft elastic carrier and a plurality of hard fine particles. The hard fine particles are provided on the surface of the soft elastic carrier, the soft elastic carrier is made of an elastic material having adhesiveness, and the particle size of the soft elastic carrier is 10 μm to 150 μm, and the particle size of the hard fine particles. Provides a physical dry surface treatment structure for semiconductor wafers, characterized in that the number of meshes according to the standards of the American Materials Testing Association is 1500 to 30000.

本考案の半導体ウェハの物理的乾式表面処理構造は、表面処理構造と半導体ウェハの被処理表面が高速で接触されたときに、軟質弾性キャリアが変形し、被処理表面で高速摩擦摺動され、軟質弾性キャリアの表面に粘着された硬質微粒子により、被処理表面を研削し、半導体ウェハの被処理表面を除去するか研磨する。 In the physical dry surface treatment structure of the semiconductor wafer of the present invention, when the surface treatment structure and the surface to be treated of the semiconductor wafer are brought into contact with each other at high speed, the soft elastic carrier is deformed and is frictionally slid on the surface to be treated at high speed. The surface to be treated is ground by the hard fine particles adhered to the surface of the soft elastic carrier, and the surface to be treated of the semiconductor wafer is removed or polished.

図1は、従来のサンドブラスト技術によりウェハ表面のめっき膜を除去する工程を示す説明図である。FIG. 1 is an explanatory diagram showing a process of removing a plating film on a wafer surface by a conventional sandblasting technique. 図2は、従来のサンドブラスト技術によりウェハ表面のめっき膜を除去した後のウェハ表面を示す拡大図であり、Aは、粗さを表す。FIG. 2 is an enlarged view showing the wafer surface after removing the plating film on the wafer surface by the conventional sandblasting technique, and A represents the roughness. 図3は、本考案の一実施形態に係る半導体ウェハの表面処理構造の混成説明図であり、(A)は表面処理構造の混合図であり、(B)は単体の表面処理構造を示す拡大図である。3A and 3B are mixed explanatory views of a surface-treated structure of a semiconductor wafer according to an embodiment of the present invention, FIG. 3A is a mixed view of a surface-treated structure, and FIG. 3B is an enlarged view showing a single surface-treated structure. It is a figure. 図4は、本考案の一実施形態に係る半導体ウェハの物理的乾式表面処理方法のブラストを行う状態を示す説明図である。FIG. 4 is an explanatory diagram showing a state in which a physical dry surface treatment method for a semiconductor wafer according to an embodiment of the present invention is blasted. 図5は、本考案の一実施形態に係る半導体ウェハの物理的乾式表面処理方法の表面処理構造がウェハ表面にブラストを施す状態を示す説明図であり、(A)は単体の表面処理構造及びウェハ表面が平滑な状態を示す。FIG. 5 is an explanatory view showing a state in which the surface treatment structure of the physical dry surface treatment method for a semiconductor wafer according to an embodiment of the present invention blasts the wafer surface, and FIG. 5A shows a single surface treatment structure and a single surface treatment structure. The wafer surface shows a smooth state. 図6は、本考案の一実施形態に係る半導体ウェハの表面処理構造がウェハ表面にブラストを施した後の状態を示す説明図である。FIG. 6 is an explanatory diagram showing a state after the surface treatment structure of the semiconductor wafer according to the embodiment of the present invention is blasted on the wafer surface.

以下、本考案の実施形態について図に基づいて説明する。なお、これによって本考案が限定されるものではない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that this does not limit the present invention.

本考案の一実施形態に係る半導体ウェハの物理的乾式表面処理構造は、図3の(A)及び(B)に示すように、半導体ウェハの表面処理構造500は、少なくとも1つの軟質弾性キャリア50と、複数の硬質微粒子55とから構成されてなる。複数の軟質弾性キャリア50は、粘着性を有する軟質弾性材料からなる。この軟質弾性材料は、例えば、プラスチック、ゴム又はシリカゲル(silica gel)を基材の原料としてつくった軟質弾性複合物である。これら軟質弾性キャリア50の粒径は10μm〜150μmである。これら硬質微粒子55は、例えば、ダイヤモンド、窒化ホウ素、炭化タングステン、炭化ホウ素などの硬質材から選択され、これら硬質微粒子55の粒径は、米国材料試験協会(American Society for Testing and Materials)の規格によるメッシュ数が1500〜30000であり、複数の硬質微粒子55は、各軟質弾性キャリア50の表面(図3の(B)を参照する)に設けられ、噴射装置が高速で噴射させることができる。 As shown in FIGS. 3A and 3B, the surface treatment structure 500 of the semiconductor wafer has at least one soft elastic carrier 50 as the physical dry surface treatment structure of the semiconductor wafer according to the embodiment of the present invention. And a plurality of hard fine particles 55. The plurality of soft elastic carriers 50 are made of a soft elastic material having adhesiveness. This soft elastic material is, for example, a soft elastic composite made of plastic, rubber or silica gel as a raw material of a base material. The particle size of these soft elastic carriers 50 is 10 μm to 150 μm. These hard fine particles 55 are selected from hard materials such as diamond, boron nitride, tungsten carbide, and boron carbide, and the particle size of these hard fine particles 55 is according to the standards of the American Society for Testing and Materials. The number of meshes is 1500 to 30000, and the plurality of hard fine particles 55 are provided on the surface of each soft elastic carrier 50 (see FIG. 3B), and the injection device can inject at high speed.

図3及び図4を参照する。図3及び図4に示すように、本考案の一実施形態に係る半導体ウェハの物理的乾式表面処理方法の特徴は、特定の噴射角度で表面処理用組合物を噴射し、半導体ウェハ100の被処理表面105を除去する工程を含む表面処理にある。表面処理構造500は、表面に硬質微粒子55が粘着された軟質弾性キャリア50を含み、特定の夾角は2〜60度であり、表面処理構造500の噴出速度は50〜200m/sであり、表面処理構造500と半導体ウェハ100の被処理表面105とが高速で接触されると、図5に示すように、軟質弾性キャリア50が変形し、被処理表面105で高速摩擦摺動され、表面処理構造500の軟質弾性キャリア50の表面に硬質微粒子55が粘着され、半導体ウェハ100の被処理表面105を研削し、半導体ウェハ100の被処理表面105のめっき膜又は被処理表面105を除去する。 See FIGS. 3 and 4. As shown in FIGS. 3 and 4, a feature of the physical dry surface treatment method for a semiconductor wafer according to an embodiment of the present invention is that a surface treatment combination is injected at a specific injection angle to cover the semiconductor wafer 100. The surface treatment includes a step of removing the treated surface 105. The surface-treated structure 500 includes a soft elastic carrier 50 to which hard fine particles 55 are adhered to the surface, a specific angle of curvature is 2 to 60 degrees, the ejection speed of the surface-treated structure 500 is 50 to 200 m / s, and the surface is surface-treated. When the treated structure 500 and the surface 105 to be treated of the semiconductor wafer 100 are brought into contact with each other at high speed, as shown in FIG. 5, the soft elastic carrier 50 is deformed and sliding at high speed on the surface 105 to be treated to form a surface treated structure. Hard fine particles 55 are adhered to the surface of the soft elastic carrier 50 of 500, and the surface 105 to be treated of the semiconductor wafer 100 is ground to remove the plating film or the surface 105 to be treated of the surface 105 to be treated of the semiconductor wafer 100.

本考案の他の実施形態では、表面処理構造500に用いる様々な材料(例えば、ダイヤモンド、窒化ホウ素、炭化タングステン又はその混合物)又は様々な粒径(例えば、メッシュ数が5000、10000又は15000)の硬質微粒子55に基づき、半導体ウェハ100の被処理表面105上の様々な材料からなるめっき膜を除去するために用い、半導体ウェハ100を減厚するか(例えば、メッシュ数が約10000の硬質微粒子55を選択し)、半導体ウェハ100の被処理表面105の平坦化工程又は鏡面研磨工程を行う(例えば、メッシュ数20000の硬質微粒子55)。 In another embodiment of the present invention, of various materials (eg, diamond, boron nitride, tungsten carbide or a mixture thereof) or various particle sizes (eg, mesh number 5000, 10000 or 15000) used for the surface treatment structure 500. Based on the hard fine particles 55, it is used to remove a plating film made of various materials on the surface 105 to be treated of the semiconductor wafer 100, and the semiconductor wafer 100 is thinned (for example, the hard fine particles 55 having about 10,000 meshes). Is selected), and a flattening step or a mirror polishing step of the surface 105 to be treated of the semiconductor wafer 100 is performed (for example, hard fine particles 55 having 20000 meshes).

また、本考案の他の実施形態では、半導体ウェハ100の被処理表面105の状態は、例えば、半導体ウェハ100がめっき膜を有さないか、めっき膜(例えば、絶縁めっき膜又は金属めっき膜)を有し、2工程又は3工程以上のブラスト表面処理工程を行い、各ブラスト表面処理工程の表面処理構造500の硬質微粒子55の粒径が異なるか、半導体ウェハ100の被処理表面105の粗さレベルに対するメーカの様々な要求に基づき、粗除去、微細除去、仕上げ研磨など複数の処理工程を順次行い、加工速度及び加工精度の要求を満たすことができる。勿論、本考案の方法も半導体ウェハ100の製造工程のニーズに基づき、従来のエッチング、化学機械研磨、洗浄など典型的な工程の前後に組み合わせて応用してもよい。 Further, in another embodiment of the present invention, the state of the surface 105 to be treated of the semiconductor wafer 100 is, for example, that the semiconductor wafer 100 does not have a plating film or a plating film (for example, an insulating plating film or a metal plating film). The blast surface treatment step of 2 steps or 3 steps or more is performed, and the particle size of the hard fine particles 55 of the surface treatment structure 500 of each blast surface treatment step is different, or the roughness of the surface 105 to be treated of the semiconductor wafer 100 is different. Based on various requirements of the manufacturer for the level, a plurality of processing steps such as rough removal, fine removal, and finish polishing can be sequentially performed to meet the requirements of processing speed and processing accuracy. Of course, the method of the present invention may also be applied in combination before and after typical processes such as conventional etching, chemical mechanical polishing, and cleaning, based on the needs of the manufacturing process of the semiconductor wafer 100.

また、本考案の他の実施形態に係る半導体ウェハ100は、めっき膜又は研磨表面を除去するために用いるサファイア基板、ガラス基板又は石英基板でもよい。 Further, the semiconductor wafer 100 according to another embodiment of the present invention may be a sapphire substrate, a glass substrate or a quartz substrate used for removing the plating film or the polished surface.

上述したことから分かるように、本考案の半導体ウェハの物理的乾式表面処理方法の特徴は、図4、図5及び図6に示すように、軟質弾性キャリア50及び硬質微粒子55を含む表面処理構造が、半導体ウェハ100の被処理表面105に対してブラスト除去を行い、表面処理構造500の軟質弾性キャリア50が被処理表面105に高速で接触されると、軟質弾性キャリア50自体が変形し、ワークピース表面で摩擦摺動され(図5を参照する)、摩擦摺動により軟質弾性キャリア50の表面の硬質微粒子55により除去又は研磨を行い、その表面の残渣60が掻き取られるため(図5の(A)を参照する)、従来技術で利用するエッチング又は化学機械研磨と比べ、製造工程が非常に簡素で迅速であるとともに、腐蝕性液体(例えば、フッ化水素酸)を使用しなくてもよいため、製造工程で有毒ガスが発生することを防ぎ、製造工程の安全性を高めることができる。また、研磨廃液、研磨汚泥などの廃棄物が発生することがないため、生態環境が汚染されることを防ぎ、化学廃液の回収処理に必要な設備及び人的コストを減らすことができ、本考案は、再生ウェハの表面処理工程を簡素化し、加工精度を高め、表面処理にかかる時間を短縮させることができる。 As can be seen from the above, the features of the physical dry surface treatment method for the semiconductor wafer of the present invention are, as shown in FIGS. 4, 5 and 6, a surface treatment structure containing a soft elastic carrier 50 and hard fine particles 55. However, when the surface 105 to be treated of the semiconductor wafer 100 is blasted and the soft elastic carrier 50 of the surface treatment structure 500 is brought into contact with the surface 105 to be treated at high speed, the soft elastic carrier 50 itself is deformed and the work It is frictionally slid on the surface of the piece (see FIG. 5), and is removed or polished by the hard fine particles 55 on the surface of the soft elastic carrier 50 by frictional sliding, and the residue 60 on the surface is scraped off (FIG. 5). (See (A)), the manufacturing process is much simpler and faster than the etching or chemical mechanical polishing used in the prior art, and without the use of corrosive liquids (eg, hydrofluoric acid). Therefore, it is possible to prevent the generation of toxic gas in the manufacturing process and enhance the safety of the manufacturing process. In addition, since no waste such as polishing waste liquid and polishing sludge is generated, it is possible to prevent the ecological environment from being polluted and reduce the equipment and human cost required for the recovery treatment of the chemical waste liquid. Can simplify the surface treatment process of the recycled wafer, improve the processing accuracy, and shorten the time required for the surface treatment.

同時に、化学薬品の汚染を減らし、廃液処理の工程及び設備を減らすことができ、再生ウェハの工程は環境を汚染せず、安全性が高い。また、半導体ウェハ100を再生させるときの変質層を減らし、製造工程全体の収率を高めることができる。 At the same time, chemical pollution can be reduced, waste liquid treatment processes and equipment can be reduced, and the recycled wafer process does not pollute the environment and is highly safe. In addition, the altered layer when the semiconductor wafer 100 is regenerated can be reduced, and the yield of the entire manufacturing process can be increased.

10 ウェハ
15 表面
20 サンドブラスト材料
50 軟質弾性キャリア
55 硬質微粒子
60 残渣
100 半導体ウェハ
105 被処理表面
500 表面処理構造
A 残留金属めっき膜
10 Wafer 15 Surface 20 Sandblast material 50 Soft elastic carrier 55 Hard fine particles 60 Residue 100 Semiconductor wafer 105 Surface to be treated 500 Surface treatment structure A Residual metal plating film

Claims (5)

少なくとも1つの軟質弾性キャリアと、複数の硬質微粒子とを備えた、半導体ウェハの物理的乾式表面処理構造であって、
前記軟質弾性キャリアの表面には、前記硬質微粒子が設けられ、
前記軟質弾性キャリアは、粘着性を有する弾性材料からなり、
前記軟質弾性キャリアの粒径は10μm〜150μmであり、
前記硬質微粒子の粒径は、米国材料試験協会の規格によるメッシュ数が1500〜30000であることを特徴とする、半導体ウェハの物理的乾式表面処理構造。
A physical dry surface-treated structure of a semiconductor wafer comprising at least one soft elastic carrier and a plurality of hard fine particles.
The hard fine particles are provided on the surface of the soft elastic carrier, and the hard fine particles are provided.
The soft elastic carrier is made of an elastic material having adhesiveness.
The particle size of the soft elastic carrier is 10 μm to 150 μm.
The particle size of the hard fine particles is a physical dry surface treatment structure of a semiconductor wafer, characterized in that the number of meshes is 1500 to 30,000 according to the standards of the American Society for Testing and Materials.
前記軟質弾性キャリアは、プラスチック、ゴム又はシリカゲルを基材の原料としてつくった軟質弾性複合物からなることを特徴とする請求項1に記載の半導体ウェハの物理的乾式表面処理構造。 The physical dry surface treatment structure for a semiconductor wafer according to claim 1, wherein the soft elastic carrier is made of a soft elastic composite made of plastic, rubber or silica gel as a raw material of a base material. 前記硬質微粒子は、天然ダイヤモンド、人工ダイヤモンド又はその混合物からなることを特徴とする請求項1に記載の半導体ウェハの物理的乾式表面処理構造。 The physical dry surface-treated structure of a semiconductor wafer according to claim 1, wherein the hard fine particles are composed of natural diamond, artificial diamond, or a mixture thereof. 前記硬質微粒子は、窒化ホウ素、炭化ホウ素又はその混合物からなることを特徴とする請求項1に記載の半導体ウェハの物理的乾式表面処理構造。 The physical dry surface-treated structure of a semiconductor wafer according to claim 1, wherein the hard fine particles are made of boron nitride, boron carbide, or a mixture thereof. 前記硬質微粒子は、炭化タングステン又はその混合物からなることを特徴とする請求項1に記載の半導体ウェハの物理的乾式表面処理構造。 The physical dry surface-treated structure of a semiconductor wafer according to claim 1, wherein the hard fine particles are made of tungsten carbide or a mixture thereof.
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