JP3209977B2 - 半導体モジュ−ル - Google Patents
半導体モジュ−ルInfo
- Publication number
- JP3209977B2 JP3209977B2 JP09641499A JP9641499A JP3209977B2 JP 3209977 B2 JP3209977 B2 JP 3209977B2 JP 09641499 A JP09641499 A JP 09641499A JP 9641499 A JP9641499 A JP 9641499A JP 3209977 B2 JP3209977 B2 JP 3209977B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- lead
- printed wiring
- wiring board
- conductive material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
の構造、特に半導体装置が搭載されるプリント配線基板
に設けられる接合部のパターン形状に関するものであ
る。
品が搭載されたモジュール製品の一つであるメモリモジ
ュールの外形図である。
ッケージ(例えば、T-SOP(Thin―Small Outline Packag
e))101は、メモリモジュールに実装される。また、電
気的回路を形成するために、複数の表面実装型半導体パ
ッケージ101は、プリント配線基板(例えば、ガラスエ
ポキシ樹脂基板、 セラミック基板等)102上に形成され
る。プリント配線基板102は、絶縁性物質上に導電性パ
ターンを設けた構造を有する。また、モジュール製品を
外部装置(例えば、パーソナルコンピュータ等)に電気
的に接続するために、複数の外部端子103が、プリント
配線基板102上に設けられている。
線切り欠き断面を示した図である。表面実装型半導体パ
ッケージ101は、集積回路が形成された半導体素子20
1と、半導体素子201の電気的信号を外部に伝達するため
のリード202と、半導体素子201の電気的信号をリード20
2に伝達するための金属細線(例えば、金線、アルミ線
等)203と、半導体素子201及び金属細線203を外力から
防ぐための封止樹脂(例えば、エポキシ樹脂、シリコー
ン樹脂等)204と、導電性パターンが形成されたプリン
ト配線基板(例えば、ガラスエポキシ基板、セラミック
基板等)205と、プリント配線基板205上に設けられた半
導体素子201の電気的信号を外部に伝達するためのパッ
ド206と、リード202とパッド206を電気的に接続する導
電性物質(例えば、半田、導電性樹脂、Agペースト
等)207とから構成される。上記のように構成された表
面実装型半導体パッケージ101が、プリント配線基板205
の表面及び裏面に実装されている。
プリント配線基板301上に設けられたパッド302は、
リード304の幅より若干大きい形状であった。
線切り欠き断面を示した図である。
03と、プリント配線基板401に設けられたパッド402と
は、導電性物質404を介して電気的に接続されている。
大きく設定されている。
た従来の半導体モジュ−ルでは、パッドとリードとを電
気的に接続するための導電性物質において、半導体パッ
ケージとプリント配線基板との間の熱膨張係数(一般的
に半導体ハ゜ッケーシ゛は、5〜7ppm、プリント配線基板
は16ppmである。)の違いにより、導電性物質内に
応力が加わることクラックが発生する。これにより、パ
ッドとリードとの間が電気的に導通不可能という問題が
生じていた。
発生によるリ−ドとパッド間の非導通を防止する半導体
モジュ−ルを提供することを目的とする。
に、本発明の半導体モジュ−ルは、集積回路が形成され
たチップと、前記集積回路と電気的に接続された第1の
外部接続端子と、第2の外部接続端子を有するプリント
配線基板と、前記第1及び第2の外部接続端子同士を電気
的に接続する導電性物質とを有し、前記導電性物質が前
記第2の外部接続端子の側壁を覆うように形成されてい
ることを特徴とする。
態の半導体モジュ−ルを示す断面図である。半導体モジ
ュ−ルは、導電性パターンが設けられたプリント配線基
板601、例えば、ガラスエポキシ樹脂基板、セラミック
基板等と、集積回路が形成されたチップ及び、この集積
回路と電気的に接続された第1の外部接続端子としての
リ−ド602とからなる半導体パッケージと、 プリント配
線基板601に形成された第2の外部接続端子としてのパッ
ド603と、リード602とパッド603を電気的に接続するた
めの導電性物質604、例えば、半田、導電性樹脂、Ag
ペースト等とから構成される。
は、パッド603が、リード602の幅と実質的に同一、若し
くはそれ以下の幅を有するように形成し、これによっ
て、導電性物質604が、パッド603の側面まで覆うように
形成されることである。
パッド603に対する導電性物質604の接合面積を増加する
ことになり、半導体パッケージとプリント配線基板601
の熱膨張係数の違いによる導電性物質604に発生するク
ラックを抑えることが可能となる。
モジュ−ルを示す断面図である。半導体モジュ−ルは、
導電性パターンが設けられたプリント配線基板901、例
えば、ガラスエポキシ樹脂基板、セラミック基板等と、
集積回路が形成されたチップ及び、この集積回路と電気
的に接続された第1の外部接続端子としてのリ−ド902と
からなる半導体パッケージと、 プリント配線基板901に
形成された第2の外部接続端子としてのパッド903と、リ
ード902とパッド903を電気的に接続するための導電性物
質904、例えば、半田、導電性樹脂、Agペースト等と
から構成される。
は、パッド903が、リード902の幅と実質的に同一、若し
くはそれ以下の幅を有するように形成し、かつ凸形状を
有する。これによって、導電性物質904が、パッド903の
側面まで覆い、かつパッド903の凸形状部の側面まで覆
うようになる。また、凸形状部は、エッチングまたは、
ミーリング等にて形成する。
第1の実施の形態パッド903に対する導電性物質904の接
合面積を増加することになり、半導体パッケージとプリ
ント配線基板901の熱膨張係数の違いによる導電性物質9
04に発生するクラックを抑えることが可能となる。
型半導体パッケージを適用した半導体装置を例に説明し
たが表面実装型半導体パッケージに限らずBGA(Ba
llGrid Ally)/CSP(Chip Saze
Package)等のパッケージを実装する半導体装
置にも用いることもできる。
ッドが、リードの幅と実質的に同一、若しくはそれ以下
の幅を有するように形成し、これによって、導電性物質
が、パッドの側面まで覆うように形成される。従って、
パッドに対する導電性物質の接合面積を増加することに
なり、半導体パッケージとプリント配線基板の熱膨張係
数の違いによる導電性物質に発生するクラックを抑える
ことが可能となる。
を示す断面図である。
を示す断面図である。
り欠き断面を示した図である。
り欠き断面を示した図である。
Claims (2)
- 【請求項1】 集積回路が形成されたチップと、前記集
積回路と電気的に接続される第1の部分とパッドと対向
する第2の部分とを有するリードと、前記チップ及び前
記リードの第1の部分とを封止する封止樹脂とからなる
樹脂封止型半導体パッケージと、 前記リードの第2の部分における幅と実質的に等しい幅
を有する前記パッドが形成された主表面を有し、前記樹
脂封止型半導体パッケージが搭載される プリント配線基
板と、前記リードの第2の部分と前記パッドとを 電気的に接続
する導電性物質であって、前記リードの第2の部分の側
面及び前記パッドの側面を前記プリント配線基板の主表
面に至って覆う導電性物質とを有することを特徴とする
半導体モジュール。 - 【請求項2】前記パッドは、凸形状であることを特徴と
する請求項1記載の半導体モジュール。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP09641499A JP3209977B2 (ja) | 1999-04-02 | 1999-04-02 | 半導体モジュ−ル |
US09/522,924 US6498308B2 (en) | 1999-04-02 | 2000-03-10 | Semiconductor module |
TW089104572A TW507502B (en) | 1999-04-02 | 2000-03-14 | Semiconductor module |
KR1020000012954A KR100789306B1 (ko) | 1999-04-02 | 2000-03-15 | 반도체 모듈 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP09641499A JP3209977B2 (ja) | 1999-04-02 | 1999-04-02 | 半導体モジュ−ル |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000294892A JP2000294892A (ja) | 2000-10-20 |
JP3209977B2 true JP3209977B2 (ja) | 2001-09-17 |
Family
ID=14164323
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP09641499A Expired - Fee Related JP3209977B2 (ja) | 1999-04-02 | 1999-04-02 | 半導体モジュ−ル |
Country Status (4)
Country | Link |
---|---|
US (1) | US6498308B2 (ja) |
JP (1) | JP3209977B2 (ja) |
KR (1) | KR100789306B1 (ja) |
TW (1) | TW507502B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101148494B1 (ko) | 2009-05-07 | 2012-05-21 | 삼성전기주식회사 | 접속금속층을 갖는 반도체 장치 및 그 제조방법 |
KR20110058061A (ko) * | 2009-11-25 | 2011-06-01 | 삼성전기주식회사 | 다이 실장기판 및 그 제조방법 |
US9142533B2 (en) * | 2010-05-20 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate interconnections having different sizes |
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JPH10135613A (ja) * | 1996-10-28 | 1998-05-22 | Ngk Spark Plug Co Ltd | 配線基板 |
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US6002172A (en) * | 1997-03-12 | 1999-12-14 | International Business Machines Corporation | Substrate structure and method for improving attachment reliability of semiconductor chips and modules |
US5920464A (en) * | 1997-09-22 | 1999-07-06 | Trw Inc. | Reworkable microelectronic multi-chip module |
US6315856B1 (en) * | 1998-03-19 | 2001-11-13 | Kabushiki Kaisha Toshiba | Method of mounting electronic component |
JP2003081672A (ja) * | 2001-09-07 | 2003-03-19 | Sekisui Chem Co Ltd | 無機質硬化体、無機質壁材 |
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- 2000-03-15 KR KR1020000012954A patent/KR100789306B1/ko active IP Right Grant
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US6498308B2 (en) | 2002-12-24 |
KR100789306B1 (ko) | 2007-12-28 |
US20020097566A1 (en) | 2002-07-25 |
JP2000294892A (ja) | 2000-10-20 |
TW507502B (en) | 2002-10-21 |
KR20000071442A (ko) | 2000-11-25 |
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