JP3195828B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3195828B2 JP3195828B2 JP23077692A JP23077692A JP3195828B2 JP 3195828 B2 JP3195828 B2 JP 3195828B2 JP 23077692 A JP23077692 A JP 23077692A JP 23077692 A JP23077692 A JP 23077692A JP 3195828 B2 JP3195828 B2 JP 3195828B2
- Authority
- JP
- Japan
- Prior art keywords
- resistance element
- film
- metal film
- semiconductor device
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置、特に高抵
抗素子に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, particularly to a high resistance element.
【０００２】[0002]
【従来の技術】１９７０年代終わり頃より、ポリシリコ
ンを用いて高抵抗素子を形成する技術が進歩し、スタテ
ィックＲＡＭ（以下、ＳＲＡＭと称す）に高抵抗ポリシ
リコン負荷形セルが使われるようになった。その後高抵
抗ポリシリコン素子の制御技術が進歩し、現在ではＣＭ
ＯＳ−ＳＲＡＭの大半が高抵抗ポリシリコン負荷形セル
で構成されている。2. Description of the Related Art Since the late 1970's, the technology for forming a high-resistance element using polysilicon has advanced, and a high-resistance polysilicon load cell has been used for a static RAM (hereinafter referred to as an SRAM). Was. Since then, control technology for high-resistance polysilicon elements has advanced, and now CM
Most of the OS-SRAM is constituted by a high resistance polysilicon load type cell.
【０００３】図５は従来のＳＲＡＭのメモリーセルの高
抵抗素子部の断面図である。図において１はシリコン基
板（図示せず）上に形成されたシリコン酸化膜、２はシ
リコン酸化膜１上に形成された高抵抗素子、３は高抵抗
素子２を覆ってシリコン酸化膜１上に形成された層間絶
縁酸化膜、４は層間絶縁酸化膜３上に形成された第１の
金属配線層、５は第１の金属配線層４を覆って層間絶縁
酸化膜３上に形成されたプラズマ酸化膜で、この上に形
成された第２の金属配線層（図示せず）と第１の金属配
線層４との層間絶縁膜となる。６はプラズマ酸化膜５上
に形成された保護膜としてのプラズマ窒化膜である。FIG. 5 is a sectional view of a high resistance element portion of a conventional SRAM memory cell. In the figure, 1 is a silicon oxide film formed on a silicon substrate (not shown), 2 is a high resistance element formed on the silicon oxide film 1, and 3 is a silicon oxide film covering the high resistance element 2 on the silicon oxide film 1. The formed interlayer insulating oxide film, 4 is a first metal wiring layer formed on the interlayer insulating oxide film 3, and 5 is a plasma formed on the interlayer insulating oxide film 3 covering the first metal wiring layer 4. The oxide film serves as an interlayer insulating film between the second metal wiring layer (not shown) formed thereon and the first metal wiring layer 4. Reference numeral 6 denotes a plasma nitride film as a protective film formed on the plasma oxide film 5.
【０００４】次に製造方法を説明する。まずシリコン基
板上に形成されたシリコン酸化膜１上にポリシリコンを
約０．１μｍの膜厚に形成し、パターニングを行って高
抵抗素子２を形成する。次に、高抵抗素子２が形成され
たシリコン基板上の全面にＬＰＣＶＤ法によって層間絶
縁酸化膜３を約１μｍの膜厚に形成する。次に例えばア
ルミニウム等による第１の金属配線層４を形成し、その
上にプラズマＣＶＤ法によってプラズマ酸化膜５を約
０．８μｍの膜厚に形成し、さらに第２の金属配線層
（図示せず）を形成する。ここで、層間絶縁酸化膜３は
高抵抗素子２と第１の金属配線層４との絶縁膜であり、
プラズマ酸化膜５は第１の金属配線層４と第２の金属配
線層との絶縁膜である。このＳＲＡＭの２層配線を構成
する第１の金属配線層４および第２の金属配線層は高抵
抗素子２のパターンに依存せずに配設され、図５に示す
断面図の部位には、第２の金属配線層のパターンがない
ものである。最後に、素子の保護膜としてプラズマＣＶ
Ｄ法によりプラズマ窒化膜６を約１μｍの膜厚に形成す
る。Next, a manufacturing method will be described. First, polysilicon is formed to a thickness of about 0.1 μm on a silicon oxide film 1 formed on a silicon substrate, and is patterned to form a high-resistance element 2. Next, an interlayer insulating oxide film 3 is formed to a thickness of about 1 μm on the entire surface of the silicon substrate on which the high-resistance element 2 is formed by LPCVD. Next, a first metal wiring layer 4 made of, for example, aluminum or the like is formed, a plasma oxide film 5 is formed thereon by a plasma CVD method to a thickness of about 0.8 μm, and a second metal wiring layer (not shown) is formed. ) Are formed. Here, the interlayer insulating oxide film 3 is an insulating film between the high resistance element 2 and the first metal wiring layer 4,
The plasma oxide film 5 is an insulating film between the first metal wiring layer 4 and the second metal wiring layer. The first metal wiring layer 4 and the second metal wiring layer constituting the two-layer wiring of this SRAM are provided independently of the pattern of the high-resistance element 2, and the portions of the sectional view shown in FIG. There is no pattern of the second metal wiring layer. Finally, plasma CV is used as a protective film for the device.
The plasma nitride film 6 is formed to a thickness of about 1 μm by the D method.
【０００５】[0005]
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているが、通常プラズマＣＶＤ法で
形成されるシリコン窒化膜には、形成時に使用するシラ
ンガス（ＳiＨ4）から発生する水素を膜中および膜の界
面に大量に含んでいる。このためプラズマ窒化膜６に大
量に含まれる水素がプラズマ酸化膜５および層間絶縁酸
化膜３を通して、高抵抗素子２中に拡散し、抵抗値を変
動させるという問題点があった。While THE INVENTION Problems to be Solved by the conventional semiconductor device is constructed as described above, the silicon nitride film formed by normal plasma CVD method, a silane gas used in the formation (S i H 4) The generated hydrogen is contained in a large amount in the film and at the interface of the film. Therefore, there is a problem that a large amount of hydrogen contained in the plasma nitride film 6 diffuses into the high-resistance element 2 through the plasma oxide film 5 and the interlayer insulating oxide film 3 to change the resistance value.
【０００６】この発明は上記のような問題点を解消する
ためになされたもので、プラズマ窒化膜中の水素が、高
抵抗素子中に拡散することを防止して、高抵抗素子の抵
抗値を安定して高く保つことができる半導体装置を得る
ことを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and prevents the hydrogen in a plasma nitride film from diffusing into a high-resistance element to reduce the resistance of the high-resistance element. It is an object to obtain a semiconductor device which can be stably maintained at a high level.
【０００７】[0007]
【課題を解決するための手段】この発明の請求項１に係
る半導体装置は、半導体基板と、この半導体基板上の多
結晶シリコンからなる高抵抗素子と、この高抵抗素子上
に形成されたシリコン酸化膜のみから成る絶縁膜と、該
絶縁膜上に形成された金属膜と、さらに上層にプラズマ
ＣＶＤ法によって形成された窒化膜とを備え、上記金属
膜がアルミニウムを含む膜から成り、上記高抵抗素子の
形成領域を覆って配設される箇所と、配線として配設さ
れる箇所とを有し、上記金属膜で覆われた上記高抵抗素
子の抵抗値が、上記金属膜で覆われない様に形成した場
合の抵抗値に比して高いものである。またこの発明の請
求項２に係る半導体装置は、絶縁膜がシリコン酸化膜を
含んで構成されたものである。 またこの発明の請求項３
に係る半導体装置は、高抵抗素子を覆う金属膜は、窒化
膜からの水素を遮断して上記高抵抗素子への水素拡散を
抑制するものである。またこの発明の請求項４に係る半
導体装置は、絶縁膜が金属膜よりも水素の拡散係数の大
きな膜のみで構成されたものである。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a high-resistance element made of polycrystalline silicon on the semiconductor substrate ;
An insulating film consisting only of a silicon oxide film formed on
A metal film formed on an insulating film; and a nitride film formed on the insulating film by a plasma CVD method . The metal film is formed of a film containing aluminum , and is disposed so as to cover a formation region of the high-resistance element. And the high-resistance element covered with the metal film.
If the resistor is formed so that the resistance of the
It is higher than the resistance value in this case . The contract of the present invention
The semiconductor device according to claim 2, wherein the insulating film comprises a silicon oxide film.
It is configured to include. Claim 3 of the present invention
In the semiconductor device according to the above, the metal film covering the high-resistance element is nitrided.
Block hydrogen from the film to diffuse hydrogen into the high resistance element.
It is to suppress. In the semiconductor device according to a fourth aspect of the present invention, the insulating film is formed only of a film having a larger diffusion coefficient of hydrogen than a metal film.
【０００８】またこの発明の請求項５に係る半導体装置
は、金属膜が、高抵抗素子の上層で、絶縁膜上の全面に
形成されたものである。またこの発明の請求項６に係る
半導体装置は、金属膜が、高抵抗素子の上層で、短冊状
のパターンに形成されたものである。またこの発明の請
求項７に係る半導体装置は、金属膜が、高抵抗素子の上
層で、網目状のパターンに形成されたものである。According to a fifth aspect of the present invention, in the semiconductor device, the metal film is formed on the entire surface of the insulating film above the high resistance element. According to a sixth aspect of the present invention, in the semiconductor device, the metal film is formed in a strip pattern on the high resistance element. Further, in the semiconductor device according to claim 7 of the present invention, the metal film is formed in a mesh pattern on the high resistance element.
【０００９】またこの発明の請求項８に係る半導体装置
は、高抵抗素子と金属膜との間に第２の金属膜を有する
ものである。The semiconductor device according to claim 8 of the present invention has a second metal film between the high resistance element and the metal film.
【００１０】またこの発明の請求項９に係る半導体装置
は、窒化膜が金属膜に接触して該金属膜上に形成された
ものである。In a semiconductor device according to a ninth aspect of the present invention, the nitride film is formed on the metal film in contact with the metal film.
【００１１】[0011]
【作用】この発明の半導体装置は、金属膜が高抵抗素子
の形成領域を覆っている。このため、プラズマＣＶＤ法
によって形成された窒化膜の膜中および膜の界面に大量
に含まれる水素は、金属膜によって阻まれ、下層の高抵
抗素子に拡散しない。これにより高抵抗素子は水素の影
響による抵抗値の変動を防ぐことができ、安定して高い
抵抗値を得る。According to the semiconductor device of the present invention, the metal film covers the formation region of the high resistance element. Therefore, a large amount of hydrogen contained in the nitride film formed by the plasma CVD method and at the interface between the films is blocked by the metal film and does not diffuse into the underlying high-resistance element. Thereby, the high resistance element can prevent the fluctuation of the resistance value due to the influence of hydrogen, and obtain a high resistance value stably.
【００１２】[0012]
【実施例】実施例１． 以下、この発明の一実施例を図について説明する。図１
はこの発明の実施例１による半導体装置をＳＲＡＭのメ
モリーセルの高抵抗素子部に適用したものの断面図であ
る。図において１〜６は従来のものと同じもの、特に４
は第２の金属膜としての第１の金属配線層、７は絶縁膜
としてのプラズマ酸化膜５上の全面に形成された金属膜
としての第２の金属配線層である。[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG.
1 is a sectional view of a semiconductor device according to a first embodiment of the present invention applied to a high-resistance element portion of a memory cell of an SRAM. In the figure, 1 to 6 are the same as the conventional ones, especially 4
Denotes a first metal wiring layer as a second metal film, and 7 denotes a second metal wiring layer as a metal film formed on the entire surface of the plasma oxide film 5 as an insulating film.
【００１３】次に製造方法について説明する。従来のも
のと同様に、シリコン酸化膜１上にポリシリコンからな
る高抵抗素子２を形成し、層間絶縁酸化膜３、第１の金
属配線層４、およびプラズマ酸化膜５を形成する。次に
例えばアルミニウムなどからなる第２の金属配線層７
を、従来とはパターンを変更させることにより、配線と
して配設される箇所（図示せず）とは別に、高抵抗素子
２領域全面を覆うように、プラズマ酸化膜５上の全面に
形成する。次に保護膜として第２の金属配線層７上の全
面にプラズマＣＶＤ法によりプラズマ窒化膜６を約１μ
ｍの膜厚に形成する。Next, the manufacturing method will be described. As in the conventional case, a high resistance element 2 made of polysilicon is formed on a silicon oxide film 1, and an interlayer insulating oxide film 3, a first metal wiring layer 4, and a plasma oxide film 5 are formed. Next, a second metal wiring layer 7 made of, for example, aluminum or the like
Can be changed by changing the pattern
In addition to a portion (not shown) provided on the plasma oxide film 5, the entire surface of the high-resistance element 2 is formed so as to cover the entire surface. Next, a plasma nitride film 6 having a thickness of about 1 μm is formed on the entire surface of the second metal wiring layer 7 as a protective film by a plasma CVD method.
m.
【００１４】以上のように構成される半導体装置は、第
２の金属配線層７が高抵抗素子２領域全面を覆うように
高抵抗素子２の上層のプラズマ酸化膜５上の全面に形成
され、その上にプラズマ窒化膜６が形成されている。こ
のため、プラズマ窒化膜６の膜中および膜の界面に大量
に含まれる水素は、金属膜の性質により第２の金属配線
層７によって阻まれ、下層の高抵抗素子２に拡散しな
い。このため高抵抗素子２は水素の影響による抵抗値の
変動を防止することができ安定して高い抵抗値を得るこ
とができる。又、第２の金属配線層７にて配線として配
設する箇所と、高抵抗素子２領域全面を覆う箇所とを形
成するようにしたので、従来の工程数を増加させること
なく、上記した効果を得ることができる。 In the semiconductor device configured as described above, the second metal wiring layer 7 is formed over the entire surface of the high-resistance element 2 on the plasma oxide film 5 so as to cover the entire area of the high-resistance element 2. A plasma nitride film 6 is formed thereon. For this reason, a large amount of hydrogen contained in the film of the plasma nitride film 6 and at the interface between the films is blocked by the second metal wiring layer 7 due to the properties of the metal film, and does not diffuse into the underlying high-resistance element 2. Therefore, the high-resistance element 2 can prevent the fluctuation of the resistance value due to the influence of hydrogen and can stably obtain a high resistance value. Also, the wiring is arranged as a wiring in the second metal wiring layer 7.
And the location that covers the entire area of the high-resistance element 2 area.
To increase the number of conventional processes.
Thus, the above-described effects can be obtained.
【００１５】なお、上記実施例では、多層配線構造の第
２層配線層７を金属膜として特定の構成としたが、高抵
抗素子２とプラズマ窒化膜６との間に形成される配線層
であれば、他の配線層を上記金属膜としてもよい。In the above embodiment, the second wiring layer 7 of the multilayer wiring structure has a specific structure as a metal film, but the wiring layer formed between the high-resistance element 2 and the plasma nitride film 6 has a specific structure. If so, another wiring layer may be used as the metal film.
【００１６】実施例２．また、上記実施例１では、第２
の金属配線層７をプラズマ酸化膜５上の全面に形成した
が、高抵抗素子２のパターンのみを覆って、プラズマ酸
化膜５上に短冊状にパターニングしてもよい。この実施
例２による半導体装置の断面図を図２に、特に断面鳥瞰
図を図３に示す。このように第２の金属配線層７のパタ
ーンは高抵抗素子２のパターンを覆って上層に形成され
ているため、実施例１と同様にプラズマ窒化膜６からの
水素の拡散を防いで、同様の効果を奏する。また、第２
の金属配線層７のパターンの面積が小さくなるため、応
力を緩和し、ヒロックも防止しやすい。Embodiment 2 FIG. In the first embodiment, the second
Although the metal wiring layer 7 is formed on the entire surface of the plasma oxide film 5, the metal wiring layer 7 may be patterned in a strip shape on the plasma oxide film 5 by covering only the pattern of the high-resistance element 2. FIG. 2 is a sectional view of the semiconductor device according to the second embodiment, and FIG. As described above, since the pattern of the second metal wiring layer 7 is formed in the upper layer so as to cover the pattern of the high-resistance element 2, diffusion of hydrogen from the plasma nitride film 6 is prevented as in the first embodiment, and Has the effect of Also, the second
Since the area of the pattern of the metal wiring layer 7 becomes small, stress is eased and hillocks are easily prevented.
【００１７】実施例３．また、図４に示す様に、第２の
金属配線層７のパターンを、高抵抗素子２のパターンを
覆ってプラズマ酸化膜５上に網目状に形成しても同様の
効果を奏する。また、この網目状のパターンでは、実施
例２の第２の金属配線層のパターニング時に発生しやす
い、レジスト膜のはがれや第２の金属配線層７のはがれ
が防止できる。Embodiment 3 FIG. Further, as shown in FIG. 4, the same effect can be obtained even if the pattern of the second metal wiring layer 7 is formed in a mesh shape on the plasma oxide film 5 so as to cover the pattern of the high resistance element 2. Further, with this mesh-like pattern, it is possible to prevent peeling of the resist film and peeling of the second metal wiring layer 7 which are likely to occur when patterning the second metal wiring layer of the second embodiment.
【００１８】[0018]
【発明の効果】以上のようにこの発明によれば、高抵抗
素子の形成領域を覆ってアルミニウムを含む金属膜を形
成したため、プラズマ窒化膜から高抵抗素子中へ水素が
拡散するのを防ぐ。このため高抵抗素子の抵抗値を安定
して高く保つことができる。又、１層の金属膜にて高抵
抗素子の形成領域を覆って配設される箇所と、配線とし
て配設される箇所とを備えているので、高抵抗素子の形
成領域を覆う箇所を配線と同時に形成することができ
る。As described above, according to the present invention, since the metal film containing aluminum is formed so as to cover the formation region of the high resistance element, diffusion of hydrogen from the plasma nitride film into the high resistance element is prevented. For this reason, the resistance value of the high resistance element can be stably kept high. In addition, since a portion provided with a single-layer metal film to cover the formation region of the high-resistance element and a portion provided as wiring are provided, the portion covering the formation region of the high-resistance element is connected to the wiring. It can be formed at the same time.
【００１９】また、短冊状や網目状に金属膜をパターニ
ングすることにより面積を小さくして応力を緩和すると
ともにヒロックを防止する。特に網目状のパターンで
は、レジストや金属膜のはがれを防止できる。Further, by patterning the metal film in a strip shape or a mesh shape, the area is reduced to relieve stress and prevent hillocks. In particular, in the case of a mesh pattern, peeling of the resist and the metal film can be prevented.
【図１】この発明の実施例１による半導体装置を示す断
面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】この発明の実施例２による半導体装置を示す断
面図である。FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図３】この発明の実施例２による半導体装置を示す断
面鳥瞰図である。FIG. 3 is a bird's-eye sectional view showing a semiconductor device according to a second embodiment of the present invention;
【図４】この発明の実施例３による半導体装置を示す断
面鳥瞰図である。FIG. 4 is a sectional bird's-eye view showing a semiconductor device according to a third embodiment of the present invention;
【図５】従来の半導体装置を示す断面図である。FIG. 5 is a sectional view showing a conventional semiconductor device.
２ 高抵抗素子 ５ 絶縁膜としてのプラズマ酸化膜 ６ プラズマ窒化膜 ７ 金属膜としての第２の金属配線層 2 High resistance element 5 Plasma oxide film as insulating film 6 Plasma nitride film 7 Second metal wiring layer as metal film
フロントページの続き (56)参考文献 特開 平３−22561（ＪＰ，Ａ) 特開 平３−36757（ＪＰ，Ａ) 特開 平３−70170（ＪＰ，Ａ) 特開 平２−162755（ＪＰ，Ａ) 特開 平３−89549（ＪＰ，Ａ) 特開 昭60−5542（ＪＰ，Ａ) 特開 平３−21053（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/04 H01L 21/3205 H01L 21/822 H01L 21/8244 H01L 27/11 Continuation of the front page (56) References JP-A-3-22561 (JP, A) JP-A-3-36557 (JP, A) JP-A-3-70170 (JP, A) JP-A-2-162755 (JP) JP-A-3-89549 (JP, A) JP-A-60-5542 (JP, A) JP-A-3-21053 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB Name) H01L 27/04 H01L 21/3205 H01L 21/822 H01L 21/8244 H01L 27/11
Claims (9)
晶シリコンからなる高抵抗素子と、この高抵抗素子上に
形成されシリコン酸化膜のみから成る絶縁膜と、該絶縁
膜上に形成された金属膜と、さらに上層にプラズマＣＶ
Ｄ法によって形成された窒化膜とを備え、上記金属膜が
アルミニウムを含む膜から成り、上記高抵抗素子の形成
領域を覆って配設される箇所と、配線として配設される
箇所とを有し、上記金属膜で覆われた上記高抵抗素子の
抵抗値が、上記金属膜で覆われない様に形成した場合の
抵抗値に比して高いことを特徴とする半導体装置。1. A semiconductor substrate, a high-resistance element made of polysilicon on the semiconductor substrate, and a high-resistance element on the high-resistance element .
An insulating film formed only of a silicon oxide film;
The metal film formed on the film and the plasma CV
And a nitride film formed by the D method, organic and locations the metal film is made of a film containing aluminum, is disposed over the formation region of the high resistance element, and a portion disposed as a wiring And the high-resistance element covered with the metal film
When the resistance value is formed so as not to be covered with the metal film,
A semiconductor device characterized by having a higher resistance value .
晶シリコンからなる高抵抗素子と、この高抵抗素子上に
形成されたシリコン酸化膜を含む絶縁膜と、該絶縁膜上
に形成された金属膜と、さらに上層にプラズマＣＶＤ法
によって形成された窒化膜とを備え、上記金属膜がアル
ミニウムを含む膜から成り、上記高抵抗素子の形成領域
を覆って配設される箇所と、配線として配設される箇所
とを有し、上記金属膜で覆われた上記高抵抗素子の抵抗
値が、上記金属膜で覆われない様に形成した場合の抵抗
値に比して高いことを特徴とする半導体装置。2. A semiconductor substrate, a high-resistance element made of polycrystalline silicon on the semiconductor substrate, and a high-resistance element on the high-resistance element .
An insulating film including the formed silicon oxide film;
A metal film formed on the substrate and a nitride film formed thereon by a plasma CVD method , wherein the metal film is made of a film containing aluminum , and is provided so as to cover a formation region of the high-resistance element. And a portion provided as a wiring, the resistance of the high resistance element covered with the metal film.
The resistance when the value is formed so as not to be covered by the above metal film
A semiconductor device characterized by being higher than a value .
晶シリコンからなる高抵抗素子と、この高抵抗素子上に
形成されたシリコン酸化膜を含む絶縁膜と、該絶縁膜上
に形成された金属膜と、さらに上層にプラズマＣＶＤ法
によって形成された窒化膜とを備え、上記金属膜がアル
ミニウムを含む膜から成り、上記高抵抗素子の形成領域
を覆って配設される箇所と、配線として配設される箇所
とを有し、上記高抵抗素子を覆う上記金属膜は、上記窒
化膜からの水素を遮断して上記高抵抗素子への水素拡散
を抑制することを特徴とする半導体装置。3. A semiconductor substrate, a high-resistance element made of polysilicon on the semiconductor substrate, and a high-resistance element on the high-resistance element .
An insulating film including the formed silicon oxide film;
A metal film formed on the substrate and a nitride film formed thereon by a plasma CVD method , wherein the metal film is made of a film containing aluminum , and is provided so as to cover a formation region of the high-resistance element. And a portion provided as a wiring, and the metal film covering the high-resistance element is
Diffusion of hydrogen into the high resistance element by blocking hydrogen from the oxide film
A semiconductor device characterized by suppressing the above .
晶シリコンからなる高抵抗素子と、この高抵抗素子上に
絶縁膜を介して形成された金属膜と、さらに上層にプラ
ズマＣＶＤ法によって形成された窒化膜とを備え、上記
絶縁膜が上記金属膜よりも水素の拡散係数の大きな膜の
みで構成され、上記金属膜がアルミニウムを含む膜から
成り、上記高抵抗素子の形成領域を覆って配設される箇
所と、配線として配設される箇所とを有し、上記金属膜
で覆われた上記高抵抗素子の抵抗値が、上記金属膜で覆
われない様に形成した場合の抵抗値に比して高いことを
特徴とする半導体装置。4. A semiconductor substrate, a high-resistance element made of polycrystalline silicon on the semiconductor substrate, a metal film formed on the high-resistance element via an insulating film, and an upper layer formed by a plasma CVD method. has been a nitride film, the insulating film is composed of only the large membrane diffusion coefficient of hydrogen than the metal film, the upper Symbol metal film is made of a film containing aluminum, covers the formation region of the high-resistance element And a portion provided as wiring, and the metal film
The resistance value of the high-resistance element covered with
A semiconductor device characterized by having a higher resistance value when formed so as not to be disturbed .
上の全面に形成されたことを特徴とする請求項１〜４の
いずれかに記載の半導体装置。5. The method according to claim 1, wherein the metal film is formed on the entire surface of the insulating film over the high resistance element .
The semiconductor device according to any one of the above.
のパターンに形成されたことを特徴とする請求項１〜４
のいずれかに記載の半導体装置。6. A metal film, the upper layer of high-resistance element, according to claim 1-4, characterized in that it is formed into a strip-like pattern
The semiconductor device according to any one of the above.
のパターンに形成されたことを特徴とする請求項１〜４
のいずれかに記載の半導体装置。7. metal film, the upper layer of high-resistance element, according to claim 1-4, characterized in that it is formed in a mesh-like pattern
The semiconductor device according to any one of the above.
膜を有することを特徴とする請求項１〜７のいずれかに
記載の半導体装置。The semiconductor device according to any one of claims 8] Claim 1-7, characterized in that it comprises a second metal layer between the high-resistance element and the metal film.
形成されたことを特徴とする請求項１〜８のいずれかに
記載の半導体装置。9. The semiconductor device according to any one of claims 1-8 in which the nitride film is in contact with the metal film, characterized in that formed on the metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23077692A JP3195828B2 (en) | 1992-08-31 | 1992-08-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23077692A JP3195828B2 (en) | 1992-08-31 | 1992-08-31 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0685175A JPH0685175A (en) | 1994-03-25 |
| JP3195828B2 true JP3195828B2 (en) | 2001-08-06 |
Family
ID=16913089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23077692A Expired - Lifetime JP3195828B2 (en) | 1992-08-31 | 1992-08-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3195828B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7566607B2 (en) | 2004-09-30 | 2009-07-28 | Ricoh Company, Ltd. | Semiconductor device and fabrication process thereof |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2825074B2 (en) * | 1995-10-25 | 1998-11-18 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP5148139B2 (en) | 2007-03-12 | 2013-02-20 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
| JP7010668B2 (en) * | 2017-03-14 | 2022-01-26 | エイブリック株式会社 | Semiconductor device |
| US20180269270A1 (en) * | 2017-03-14 | 2018-09-20 | Ablic Inc. | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH064590Y2 (en) * | 1987-03-02 | 1994-02-02 | 日本電気株式会社 | Integrated circuit device |
| KR910008099B1 (en) * | 1988-07-21 | 1991-10-07 | 삼성반도체통신주식회사 | Power and signal line bussing method for memory device |
| JP2767843B2 (en) * | 1988-12-15 | 1998-06-18 | 日本電気株式会社 | Analog / digital mixed circuit |
| JPH0321053A (en) * | 1989-06-19 | 1991-01-29 | Fujitsu Ltd | Semiconductor device |
| JP3131982B2 (en) * | 1990-08-21 | 2001-02-05 | セイコーエプソン株式会社 | Semiconductor device, semiconductor memory, and method of manufacturing semiconductor device |
| JPH04152562A (en) * | 1990-10-16 | 1992-05-26 | Seiko Epson Corp | Semiconductor device |
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1992
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7566607B2 (en) | 2004-09-30 | 2009-07-28 | Ricoh Company, Ltd. | Semiconductor device and fabrication process thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0685175A (en) | 1994-03-25 |
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