JP3148183B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3148183B2 JP3148183B2 JP24523598A JP24523598A JP3148183B2 JP 3148183 B2 JP3148183 B2 JP 3148183B2 JP 24523598 A JP24523598 A JP 24523598A JP 24523598 A JP24523598 A JP 24523598A JP 3148183 B2 JP3148183 B2 JP 3148183B2
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- Japan
- Prior art keywords
- film
- interlayer insulating
- forming
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、さらに詳述すると、半導体装置の層間絶縁
膜やパッシベーション膜の形成に関するものである。The present invention relates to a method of manufacturing a semiconductor device, and more particularly to the formation of an interlayer insulating film and a passivation film of a semiconductor device.
【０００２】[0002]
【従来の技術】ＩＣの製造分野では、デバイスの高集積
化に伴い、スケーリング則に従った横方向のデバイスの
微細化が進んでいる。これに伴って、配線幅と配線間隔
も縮小化の方向にある。配線間隔が狭くなると、配線間
の寄生容量は配線間隔に反比例して増加する。この配線
間容量の増加はＲＣ時定数を大きくし、配線の信号伝播
速度の遅延を招き、デバイスの処理速度低下の原因とな
るため、デバイスの微細化を進める上で大きな問題とな
っている。2. Description of the Related Art In the field of IC manufacturing, miniaturization of devices in a horizontal direction in accordance with a scaling law is progressing along with high integration of devices. Along with this, the wiring width and the wiring interval have also been reduced. When the wiring interval becomes narrow, the parasitic capacitance between the wirings increases in inverse proportion to the wiring interval. This increase in the capacitance between the wirings increases the RC time constant, causes a delay in the signal propagation speed of the wirings, and causes a reduction in the processing speed of the device. This is a major problem in miniaturizing the device.
【０００３】近年、前述した配線間容量を低減するため
の方法として、従来層間絶縁膜として用いられているＳ
ｉＯ2膜よりも比誘電率の低い絶縁膜を形成することが
検討されている。代表的な低誘電率層間絶縁膜として
は、ＳｉＯＦ膜の他に、ＨＳＱ（Hydrogen Silsesquiox
ane）、ＢＣＢ（Benzocycrobutene）等の無機又は有機
塗布膜、フッ素化アモルファスカーボン膜やパリレン等
をはじめとするＣＶＤ有機膜などが知られている。しか
し、これらの膜、特にＳｉＯＦ膜やフッ素化アモルファ
スカーボン膜などのＦを含む膜は、Ｆの脱離やＨ2Ｏと
の反応による比誘電率の増加や、膜中のＦと下地やＡｌ
配線等との反応が懸念されている。そのため、これらの
問題を解決する目的で、通常は図４に示すように層間膜
を多層構造に形成すること、すなわちＦを含む層間絶縁
膜層４を上下からＳｉＯ2膜３で挟み込む積層構造の形
を採ることが行われている。なお、図４において１は下
地絶縁膜、２はＡｌ配線を示す。In recent years, as a method for reducing the inter-wiring capacitance, the S
It has been studied to form an insulating film having a lower dielectric constant than the iO 2 film. Typical low dielectric constant interlayer insulating films include HSQ (Hydrogen Silsesquiox) in addition to SiOF films.
Inorganic or organic coating films such as ane) and BCB (Benzocycrobutene), and CVD organic films such as fluorinated amorphous carbon films and parylene are known. However, these films, particularly films containing F, such as SiOF films and fluorinated amorphous carbon films, increase the relative dielectric constant due to the desorption of F or the reaction with H 2 O, or the F in the film and the underlayer or Al.
There is concern about reactions with wiring and the like. Therefore, in order to solve these problems, an interlayer film is usually formed in a multilayer structure as shown in FIG. 4, that is, a multilayer structure in which an interlayer insulating film layer 4 including F is sandwiched between SiO 2 films 3 from above and below. Taking shape is taking place. In FIG. 4, 1 indicates a base insulating film, and 2 indicates an Al wiring.
【０００４】しかし、ＳｉＯ2を成膜する方法として一
般的に用いられているのは、ＳｉＨ4を用いたＣＶＤ法
である。このため、ＳｉＯ2の成膜中に、Ｆを含む層間
絶縁膜はＳｉＨ4の分解により生成したＨラジカルに晒
されることになる。また、ＴＥＯＳを用いた場合でも膜
中に多くの水分を含むため、これがＦと反応してしま
う。さらに、ＳｉＯ2膜は一般的にＨ2やＨ2Ｏの拡散に
対する耐性が低いため、成膜後における大気開放中の膜
質の安定性にも問題が残る。そのため、Ｆを含む低誘電
率の層間絶縁膜を半導体デバイスに用いることは困難に
なっている。However, a CVD method using SiH 4 is generally used as a method for forming a SiO 2 film. Therefore, during the formation of SiO 2, the interlayer insulating film containing F is exposed to the H radical generated by the decomposition of SiH 4 . Further, even when TEOS is used, a large amount of water is contained in the film, and this reacts with F. Furthermore, since the SiO 2 film generally has low resistance to diffusion of H 2 and H 2 O, there remains a problem in the stability of the film quality during the opening to the atmosphere after the film formation. For this reason, it is difficult to use a low dielectric constant interlayer insulating film containing F in a semiconductor device.
【０００５】[0005]
【発明が解決しようとする課題】前述したように、従来
の半導体装置の製造、特に層間絶縁膜又はパッシベーシ
ョン膜の形成に関しては、次のような問題があった。 ＳｉＯ2を成膜する方法として一般的に用いられてい
るのは、ＳｉＨ4を用いたＣＶＤ法である。そのため、
ＳｉＯ2の成膜中に、Ｆを含む層間絶縁膜はＳｉＨ4の分
解により生成したＨラジカルに晒されることになり、Ｆ
がＨラジカルと反応する。したがって、Ｈを含まないソ
ースを用いた成膜方法が必要となる。As described above, the following problems have been encountered in the manufacture of a conventional semiconductor device, particularly in the formation of an interlayer insulating film or a passivation film. A commonly used method for forming SiO 2 is a CVD method using SiH 4 . for that reason,
During the film formation of SiO 2, the interlayer insulating film containing F is exposed to H radicals generated by decomposition of SiH 4 ,
Reacts with H radicals. Therefore, a film formation method using a source containing no H is required.
【０００６】ＳｉＨ4を用いたＣＶＤ法で成膜したＳ
ｉＯ2膜中にはＨが残留しているため、このＨがＦと反
応する。また、ＴＥＯＳを用いた場合でも膜中に多くの
水分を含むため、同様にこの水分がＦと反応してしま
う。したがって、ＨやＨ2Ｏを含まない層間膜が必要と
なる。[0006] S formed by CVD using SiH 4
Since H remains in the iO 2 film, this H reacts with F. Even when TEOS is used, a large amount of water is contained in the film, so that the water reacts with F similarly. Therefore, an interlayer film containing neither H nor H 2 O is required.
【０００７】ＳｉＯ2膜はＨ2やＨ2Ｏの拡散に対する
耐性が低いため、成膜後、大気開放中の膜質の安定性に
問題が残る。したがって、Ｈ2やＨ2Ｏの拡散に対する耐
性の高い層間膜が必要となる。Since the SiO 2 film has low resistance to diffusion of H 2 and H 2 O, there remains a problem in the stability of the film quality during the opening to the atmosphere after the film formation. Therefore, an interlayer film having high resistance to diffusion of H 2 or H 2 O is required.
【０００８】以上のように、Ｆを含む低誘電率膜を層間
絶縁膜に用いる場合、その上下に成膜する層間膜の形成
には、成膜ガスとしてＨを含まないガスを用いたＳｉＮ
膜やＳｉＯＮ膜の成膜が必要となってくる。As described above, when a low dielectric constant film containing F is used as an interlayer insulating film, an interlayer film formed above and below the film is formed of SiN using a gas containing no H as a film forming gas.
It is necessary to form a film or a SiON film.
【０００９】本発明は、前述した事情に鑑みてなされた
もので、その目的は、半導体装置において層間絶縁膜あ
るいはパッシベーション膜を形成する際に、比誘電率の
低い、安定な膜質の多層の層間絶縁膜あるいはパッシベ
ーション膜を形成することが可能な方法を提供すること
にある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to form a multilayer film having a low relative dielectric constant and a stable film quality when forming an interlayer insulating film or a passivation film in a semiconductor device. An object is to provide a method capable of forming an insulating film or a passivation film.
【００１０】[0010]
【課題を解決するための手段】本発明は、前記目的を達
成するため、下記（１）〜（６）に示す半導体装置の製
造方法を提供する。In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device as described in the following (1) to (6).
【００１１】（１）２層以上の多層層間絶縁膜の形成方
法であって、Ｆを含む層間絶縁膜を成膜する工程と、そ
の下地及び上地の一方又は両方に、Ｈを含まない無機の
Ｓｉ系ガスとＮ2を用いた高密度プラズマＣＶＤにより
ＳｉＮ膜を成膜する工程とを有し、かつ前記各工程を同
一成膜室内で行うことを特徴とする半導体装置の製造方
法。 （２）２層以上の多層層間絶縁膜の形成方法であって、
Ｆを含む層間絶縁膜を成膜する工程と、その下地及び上
地の一方又は両方に、Ｈを含まない無機のＳｉ系ガスと
Ｎ2とＯ2、Ｈを含まない無機のＳｉ系ガスとＮＯ、又
は、Ｈを含まない無機のＳｉ系ガスとＮ2Ｏを用いた高
密度プラズマＣＶＤによりＳｉＯＮ膜を形成する工程と
を有し、かつ前記各工程を同一成膜室内で行うことを特
徴とする半導体装置の製造方法。 （３）Ｈを含まない無機のＳｉ系ガスとＮ2を用いた高
密度プラズマＣＶＤによりＳｉＮ膜を形成する工程と、
ＳｉＮ膜をＨを含まない雰囲気中で熱処理する工程とを
有することを特徴とする半導体装置の製造方法。(1) A method for forming a multi-layered interlayer insulating film having two or more layers, wherein a step of forming an interlayer insulating film containing F and an inorganic film containing no H on one or both of a base and an upper surface thereof Forming a SiN film by high-density plasma CVD using a Si-based gas and N 2 , and performing each of the steps in the same film forming chamber. (2) A method of forming a multilayer interlayer insulating film having two or more layers,
A step of forming an interlayer insulating film containing F, an inorganic Si-based gas containing no H, an N 2 and O 2 , and an inorganic Si-based gas containing no H Forming a SiON film by high-density plasma CVD using NO or NO-containing inorganic Si-based gas and N 2 O, and performing each of the steps in the same film forming chamber. Manufacturing method of a semiconductor device. (3) forming a SiN film by high-density plasma CVD using H-free inorganic Si-based gas and N 2 ;
Heat treating the SiN film in an atmosphere containing no H.
【００１２】（４）Ｈを含まない無機のＳｉ系ガスが、
ＳｉxＦy又はＳｉxＣｌy（式中ｘ及びｙはそれぞれ1以
上の整数を示す）で表わされるガスであることを特徴と
する（１）〜（３）の半導体装置の製造方法。 （５）ＳｉxＦyで表わされるガスがＳｉＦ4である
（４）の半導体装置の製造方法。 （６）ＳｉxＣｌyで表わされるガスがＳｉＣｌ4である
（４）の半導体装置の製造方法。(4) The inorganic Si-based gas containing no H is
Si x F y or Si x Cl y The method of manufacturing a semiconductor device characterized in that it is a gas represented by (wherein x and y are an integer of 1 or more, respectively) (1) to (3). (5) Si x F gases represented by y is SiF 4 (4) The method for manufacturing a semiconductor device. (6) Si x The method for manufacturing a semiconductor device Cl y gas represented by is SiCl 4 (4).
【００１３】[0013]
【発明の実施の形態】［実施例１］以下に本発明の実施
例１を説明する。図１（ａ）に示すように、シリコン基
板上に成膜された下地絶縁膜１上に、第１の層間絶縁膜
としてＳｉＮ膜５を、高密度プラズマＣＶＤ法によりＳ
ｉＦ4：２０ｓｃｃｍ、Ｎ2：１００ｓｃｃｍ、成膜圧
力：５０ｍＴｏｒｒ、ＩＣＰソースパワー：３０００
Ｗ、バイアスパワー：０Ｗの条件で５０ｎｍ成膜した。
次に、第２の層間絶縁膜としてＳｉＯＦ膜６を４００ｎ
ｍ成膜した。さらに、第３の層間絶縁膜としてＳｉＮ膜
５を前記と同一条件で５０ｎｍ成膜した。ここでは、こ
れら第１、２、３層の層間絶縁膜を同一成膜室内で成膜
することにより、Ｆを含む層間絶縁膜が大気に晒される
のを防止し、Ｆの反応を抑制した。Embodiment 1 Embodiment 1 of the present invention will be described below. As shown in FIG. 1A, a SiN film 5 as a first interlayer insulating film is formed on a base insulating film 1 formed on a silicon substrate by a high-density plasma CVD method.
iF 4 : 20 sccm, N 2 : 100 sccm, film formation pressure: 50 mTorr, ICP source power: 3000
A film having a thickness of 50 nm was formed under the conditions of W and bias power: 0 W.
Next, an SiOF film 6 is formed as a second interlayer insulating film by 400 n.
m was formed. Further, a 50 nm thick SiN film 5 was formed as a third interlayer insulating film under the same conditions as described above. Here, by forming the first, second, and third interlayer insulating films in the same film forming chamber, the interlayer insulating film containing F was prevented from being exposed to the atmosphere, and the reaction of F was suppressed.
【００１４】次いで、図１（ｂ）に示すように、フォト
リソグラフィーとドライエッチングにより溝７を形成し
た。その後、バリヤメタルであるＴａとＣｕをスパッタ
法及びメッキにより成膜し、図１（Ｃ）に示すようにＣ
ＭＰにより層間絶縁膜表面のＴａとＣｕを除去しＣｕ配
線８を形成した。Next, as shown in FIG. 1B, a groove 7 was formed by photolithography and dry etching. Thereafter, a barrier metal Ta and Cu are formed by sputtering and plating, and as shown in FIG.
Ta and Cu on the surface of the interlayer insulating film were removed by MP to form a Cu wiring 8.
【００１５】本例では、第１、第３の層間絶縁膜として
ＳｉＮを成膜したが、Ｎ2Ｏを添加してＳｉＯＮ膜を成
膜してもよい。また、第２の層間絶縁膜としてＳｉＯＦ
膜を用いたが、例えばこれに代わりフッ素化アモルファ
スカーボン、ポリテトラフロオロエチレン、パリレンＡ
Ｆ４（ポリパラキシレン）等のフッ素を含む有機膜を用
いてもよい。In this embodiment, SiN is formed as the first and third interlayer insulating films. However, a SiON film may be formed by adding N 2 O. Further, SiOF is used as a second interlayer insulating film.
A membrane was used, but instead of this, for example, fluorinated amorphous carbon, polytetrafluoroethylene, parylene A
An organic film containing fluorine such as F4 (polyparaxylene) may be used.
【００１６】［実施例２］以下に本発明の実施例２を説
明する。本例では、本発明によるＳｉＮ膜を容量のカバ
ー膜として用い、強誘電体材料が水素により還元される
のを抑制した。まず、図２（ａ）に示すように、シリコ
ン基板上に成膜された下地絶縁膜１上にＰｔ／Ｔｉ下部
電極９、Ｐｂ（Ｚｒ，Ｔｉ）Ｏ3強誘電体１０、Ｉｒ／
ＩｒＯ2上部電極１１の構造の容量を形成した。次に、
図２（ｂ）に示すように、実施例１と同じ条件でＳｉＮ
膜５を５０ｎｍ成膜し、さらにＣＶＤ法によりＳｉＯ2
膜３を６００ｎｍ成膜した。最後に、フォトリソグラフ
ィーとドライエッチングによりコンタクト開口後、図２
（ｃ）に示すようにＷコンタクトとＡｌ配線２を形成し
た。Embodiment 2 Hereinafter, Embodiment 2 of the present invention will be described. In this example, the SiN film according to the present invention was used as a capacitor cover film, and the reduction of the ferroelectric material by hydrogen was suppressed. First, as shown in FIG. 2 (a), a Pt / Ti lower electrode 9, a Pb (Zr, Ti) O 3 ferroelectric 10, an Ir /
A capacitor having the structure of the IrO 2 upper electrode 11 was formed. next,
As shown in FIG. 2B, under the same conditions as in Example 1, SiN
A film 5 is formed to a thickness of 50 nm, and SiO 2 is further formed by a CVD method.
The film 3 was formed to a thickness of 600 nm. Finally, after contact opening by photolithography and dry etching, FIG.
A W contact and an Al wiring 2 were formed as shown in FIG.
【００１７】［実施例３］以下に本発明の実施例３を説
明する。ここでは、Ａｌ配線形成後、パッシベーション
膜を形成するのに本発明を用いた。図３に示すように、
Ａｌ配線２上に、まず第1の層としてＣＶＤによりＳｉ
Ｏ2膜３を１００ｎｍ成膜し、次いで第2の層として実施
例１と同じ条件でＳｉＮ膜５を１μｍ成膜した。そして
最後に、Ｎ 2プラズマアニールをＮ2：５００ｓｃｃｍ、
圧力：５０ｍＴｏｒｒ、ＩＣＰソースパワー：３０００
Ｗの条件で３０秒間行った。[Embodiment 3] Embodiment 3 of the present invention will be described below.
I will tell. Here, passivation after Al wiring formation
The invention was used to form a film. As shown in FIG.
On the Al wiring 2, first, as the first layer,
OTwoFilm 3 is deposited to a thickness of 100 nm and then implemented as a second layer
Under the same conditions as in Example 1, a 1 μm SiN film 5 was formed. And
Finally, N TwoPlasma annealing to NTwo: 500sccm,
Pressure: 50 mTorr, ICP source power: 3000
This was performed for 30 seconds under the condition of W.
【００１８】[0018]
【発明の効果】本発明に係る半導体装置の製造方法は、
以下に述べる効果を奏する。第１の効果は、ＳｉＮ膜形
成時にＦを含む層間絶縁膜でのＨＦ形成を無くすことが
できることである。その理由は、Ｈを含まないガスを用
いてＳｉＮ膜を成膜するため、成膜中にＦを含む層間絶
縁膜がＨラジカル等に晒されることがなく、Ｆとの反応
を抑制できるためである。According to the method of manufacturing a semiconductor device according to the present invention,
The following effects are obtained. A first effect is that HF formation in an interlayer insulating film containing F can be eliminated when forming a SiN film. The reason is that since the SiN film is formed using a gas containing no H, the interlayer insulating film containing F is not exposed to H radicals or the like during the film formation, and the reaction with F can be suppressed. is there.
【００１９】第２の効果は、ＳｉＮ成膜時におけるＦを
含む層間絶縁膜からのＦの脱離を抑制できることであ
る。その理由は、一般にＦを含む層間絶縁膜は高温で熱
するとＦの脱離が起こりやすいが、本発明ではＳｉＮ膜
を高密度プラズマＣＶＤ法で成膜しているので、低温成
膜が可能であり、その結果ＳｉＮ成膜時のＦの脱離を抑
制できるためである。A second effect is that desorption of F from the interlayer insulating film containing F at the time of SiN film formation can be suppressed. The reason is that, generally, when an interlayer insulating film containing F is heated at a high temperature, F is easily desorbed. However, in the present invention, a SiN film is formed by a high-density plasma CVD method. This is because, as a result, the desorption of F at the time of SiN film formation can be suppressed.
【００２０】第３の効果は、層間絶縁膜膜質の長期安定
性の向上を図れることである。その理由は、Ｆを含む層
間絶縁膜をＳｉＯ2膜よりもＨ2やＨ2Ｏの拡散に対して
耐性の高いＳｉＮ膜で挟み込む構造を採っているので、
多層の層間絶縁膜形成後に大気中のＨ2やＨ2ＯとＦとが
反応することを抑制できるためである。A third effect is that the long-term stability of the quality of the interlayer insulating film can be improved. The reason is that a structure is employed in which an interlayer insulating film containing F is sandwiched between SiN films having higher resistance to diffusion of H 2 and H 2 O than SiO 2 films.
This is because it is possible to suppress the reaction between H 2 or H 2 O in the atmosphere and F after the formation of the multilayer interlayer insulating film.
【図１】本発明の第１の実施例の説明図である。FIG. 1 is an explanatory diagram of a first embodiment of the present invention.
【図２】本発明の第２の実施例の説明図である。FIG. 2 is an explanatory diagram of a second embodiment of the present invention.
【図３】本発明の第３の実施例の説明図である。FIG. 3 is an explanatory diagram of a third embodiment of the present invention.
【図４】従来例の説明図である。FIG. 4 is an explanatory diagram of a conventional example.
１ 下地層間絶縁膜 ２ Ａｌ配線 ３ ＳｉＯ2 ４ Ｆを含む層間絶縁膜層 ５ ＳｉＮ ６ ＳｉＯＦ ７ 溝 ８ Ｃｕ配線 ９ 下部電極 １０ 強誘電体 １１ 上部電極REFERENCE SIGNS LIST 1 base interlayer insulating film 2 Al wiring 3 interlayer insulating film layer containing SiO 2 4 F 5 SiN 6 SiOF 7 groove 8 Cu wiring 9 lower electrode 10 ferroelectric 11 upper electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小柳 賢一 東京都港区芝五丁目７番１号 日本電気 株式会社内 (56)参考文献 特開 平５−29301（ＪＰ，Ａ) 特開 平８−227888（ＪＰ，Ａ) 特開 昭57−152132（ＪＰ，Ａ) 特開 平９−17860（ＪＰ，Ａ) 特開 平９−237783（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/312 H01L 21/314 H01L 21/316 H01L 21/318 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Kenichi Koyanagi 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (56) References JP-A-5-29301 (JP, A) JP-A-8 JP-A-227888 (JP, A) JP-A-57-152132 (JP, A) JP-A-9-17860 (JP, A) JP-A-9-237783 (JP, A) (58) Fields investigated (Int. . 7, DB name) H01L 21/312 H01L 21/314 H01L 21/316 H01L 21/318
Claims (6)
あって、Ｆを含む層間絶縁膜を成膜する工程と、その下
地及び上地の一方又は両方に、Ｈを含まない無機のＳｉ
系ガスとＮ2を用いた高密度プラズマＣＶＤによりＳｉ
Ｎ膜を成膜する工程とを有し、かつ前記各工程を同一成
膜室内で行うことを特徴とする半導体装置の製造方法。1. A method for forming a multi-layered interlayer insulating film having two or more layers, comprising: forming an interlayer insulating film containing F; Si
Si by high-density plasma CVD using a base gas and N 2
A step of forming an N film, wherein each of the steps is performed in the same film forming chamber.
あって、Ｆを含む層間絶縁膜を成膜する工程と、その下
地及び上地の一方又は両方に、Ｈを含まない無機のＳｉ
系ガスとＮ2とＯ2、Ｈを含まない無機のＳｉ系ガスとＮ
Ｏ、又は、Ｈを含まない無機のＳｉ系ガスとＮ2Ｏを用
いた高密度プラズマＣＶＤによりＳｉＯＮ膜を形成する
工程とを有し、かつ前記各工程を同一成膜室内で行うこ
とを特徴とする半導体装置の製造方法。2. A method for forming a multi-layered interlayer insulating film having two or more layers, wherein a step of forming an interlayer insulating film containing F and an inorganic material not containing H are provided on one or both of a base and an upper surface thereof. Si
-Based gas and N 2 and O 2 , H-free inorganic Si-based gas and N
Forming a SiON film by high-density plasma CVD using O or H-free inorganic Si-based gas and N 2 O, and performing each of the steps in the same film forming chamber. Manufacturing method of a semiconductor device.
用いた高密度プラズマＣＶＤによりＳｉＮ膜を形成する
工程と、ＳｉＮ膜をＨを含まない雰囲気中で熱処理する
工程とを有することを特徴とする半導体装置の製造方
法。3. A method comprising the steps of: forming a SiN film by high-density plasma CVD using an H-free inorganic Si-based gas and N 2 ; and heat-treating the SiN film in an H-free atmosphere. A method for manufacturing a semiconductor device, comprising:
xＦy又はＳｉxＣｌy（式中ｘ及びｙはそれぞれ1以上の
整数を示す）で表わされるガスであることを特徴とする
請求項１〜３のいずれか１項に記載の半導体装置の製造
方法。4. The method according to claim 1, wherein the inorganic Si-based gas containing no H is Si gas.
x F y or Si x Cl y of the semiconductor device according to claim 1, characterized in that the gas represented by (wherein x and y are an integer of 1 or more, respectively) Production method.
ある請求項４に記載の半導体装置の製造方法。5. A method of manufacturing a semiconductor device according to claim 4 gas represented by Si x F y is SiF 4.
4である請求項４に記載の半導体装置の製造方法。Gas SiCl represented by wherein Si x Cl y
The method for manufacturing a semiconductor device according to claim 4, wherein
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| JP24523598A JP3148183B2 (en) | 1998-08-31 | 1998-08-31 | Method for manufacturing semiconductor device |
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| JP24523598A JP3148183B2 (en) | 1998-08-31 | 1998-08-31 | Method for manufacturing semiconductor device |
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| JP2000077406A JP2000077406A (en) | 2000-03-14 |
| JP3148183B2 true JP3148183B2 (en) | 2001-03-19 |
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| KR20150107655A (en) | 2014-03-13 | 2015-09-23 | 도쿄엘렉트론가부시키가이샤 | Semiconductor device, manufacturing method thereof, and manufacturing apparatus |
| KR20170069991A (en) | 2013-06-28 | 2017-06-21 | 도쿄엘렉트론가부시키가이샤 | Method of forming multi-layered passivation and apparatus of forming multi-layered passivation |
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| JP4260764B2 (en) * | 1999-03-09 | 2009-04-30 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
| WO2000054328A1 (en) | 1999-03-09 | 2000-09-14 | Tokyo Electron Limited | Production method for semiconductor device |
| US6372291B1 (en) * | 1999-12-23 | 2002-04-16 | Applied Materials, Inc. | In situ deposition and integration of silicon nitride in a high density plasma reactor |
| JP2001320026A (en) * | 2000-05-12 | 2001-11-16 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
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| JP2011077323A (en) * | 2009-09-30 | 2011-04-14 | Tokyo Electron Ltd | Method for forming silicon nitride film, and method for producing semiconductor memory device |
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|---|---|---|---|---|
| KR20170069991A (en) | 2013-06-28 | 2017-06-21 | 도쿄엘렉트론가부시키가이샤 | Method of forming multi-layered passivation and apparatus of forming multi-layered passivation |
| KR20150107655A (en) | 2014-03-13 | 2015-09-23 | 도쿄엘렉트론가부시키가이샤 | Semiconductor device, manufacturing method thereof, and manufacturing apparatus |
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| JP2000077406A (en) | 2000-03-14 |
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