JP3123065B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3123065B2
JP3123065B2 JP20897990A JP20897990A JP3123065B2 JP 3123065 B2 JP3123065 B2 JP 3123065B2 JP 20897990 A JP20897990 A JP 20897990A JP 20897990 A JP20897990 A JP 20897990A JP 3123065 B2 JP3123065 B2 JP 3123065B2
Authority
JP
Japan
Prior art keywords
semiconductor device
polycrystalline silicon
film
wafer
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP20897990A
Other languages
Japanese (ja)
Other versions
JPH0492431A (en
Inventor
樹理 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP20897990A priority Critical patent/JP3123065B2/en
Publication of JPH0492431A publication Critical patent/JPH0492431A/en
Application granted granted Critical
Publication of JP3123065B2 publication Critical patent/JP3123065B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。特にpolyci
de電極を持つMOSFETから成る半導体装置の信頼性向上に
おいて有効である。
The present invention relates to a method for manufacturing a semiconductor device. Especially polyci
This is effective in improving the reliability of a semiconductor device including a MOSFET having a de electrode.

〔従来の技術〕[Conventional technology]

従来、polycide電極を持つMOSFETから成る半導体装置
の製造において、該多結晶シリコン薄膜後、該多結晶シ
リコンには、例えばPOCl3ソースからリンを拡散するこ
とによりn+poly−Siを形成後、n+拡散時に該n+poly−Si
表面に生じたSiO2(phospho−silicate−glass;PSG)を
HF水溶液で除去後、CVDまたはスパッタにより高融点金
属シリサイド例えば、WSi2薄膜を形成している。しかし
ながら、従来技術では、該HF水溶液による該PSGの除去
を、HF水溶液中に浸して処理後、ウエーハを水洗槽に移
し、純水に浸し水洗後、スピン・ドライヤーにウエーハ
を移し乾燥していた。HF処理,水洗,乾燥工程が、別々
の槽または処理装置で行なわれることにより、通常各々
の処理間、大気中に数分放置されていた。このため水洗
と乾燥の間に大気中に約60秒以上放置された場合には、
水洗後にウエーハ表現、(すなわちn+poly−Si表面)上
に付着した水滴により、水滴周辺には局所的に20Å程度
のSiO2が形成されたりパーティクルが付着してしまうと
いう不具合が発生した。この局所的なSiO2薄膜は、n+po
ly−Siと高融点金属シリサイドの密着性及び電気的コン
タクトを損ねるため、MOSFETから成るLSIの歩留り低下
及び信頼性の低下を招くものである。
Conventionally, in the manufacture of a semiconductor device comprising a MOSFET having a polycide electrode, after the polycrystalline silicon thin film, n + poly-Si is formed on the polycrystalline silicon by diffusing phosphorus from a POCl 3 source, for example, and then n + During diffusion, the n + poly-Si
SiO 2 (phospho-silicate-glass; PSG) generated on the surface
After removal with an HF aqueous solution, a refractory metal silicide, for example, a WSi 2 thin film is formed by CVD or sputtering. However, in the prior art, the removal of the PSG by the HF aqueous solution was carried out by immersing the wafer in an HF aqueous solution, then transferring the wafer to a washing tank, immersing the wafer in pure water, washing the wafer, transferring the wafer to a spin drier, and drying the wafer. . Since the HF treatment, water washing and drying steps are performed in separate tanks or treatment devices, they are usually left in the atmosphere for several minutes during each treatment. Therefore, if it is left in the air for about 60 seconds or more between washing and drying,
Due to the water expression on the wafer after washing with water (that is, the n + poly-Si surface), there was a problem that about 20 ° of SiO 2 was locally formed around the water droplet or particles adhered. This local SiO 2 thin film is n + po
Since the adhesion between ly-Si and the refractory metal silicide and the electrical contact are impaired, the yield and reliability of the LSI composed of MOSFETs are reduced.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

本発明は、かかる従来の課題を解決し、poly−cide構
造における、n+poly−Siと高融点金属シリサイド間にSi
O2やパーティクルが存在せず、良好な密着性と電気的コ
ンタクトを可能にせしめる半導体装置の製造方法を提供
する。
The present invention solves the above-mentioned conventional problem, and in a poly-cide structure, Si between n + poly-Si and a refractory metal silicide.
Provided is a method of manufacturing a semiconductor device which does not include O 2 and particles and enables good adhesion and electrical contact.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体装置の製造方法は、高融点金属シリサ
イドおよび多結晶シリコン膜の2層構造の電極または配
線を有する半導体装置の製造方法であって、ウェーハ上
に前記多結晶シリコン膜形成後、前記高融点金属シリサ
イド形成前に、a)前記多結晶シリコン膜表面の表面酸
化膜をHFを含んだ水溶液で除去する工程、b)しかるの
ちに純水洗浄を行う工程、c)前記純水洗浄後、前記ウ
ェーハを60秒以内に乾燥させる工程、を有することを特
徴とする。
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having electrodes or wirings having a two-layer structure of a refractory metal silicide and a polycrystalline silicon film, wherein after forming the polycrystalline silicon film on a wafer, Before the formation of the refractory metal silicide, a) a step of removing the surface oxide film on the surface of the polycrystalline silicon film with an aqueous solution containing HF, b) a step of performing pure water cleaning, and c) after the pure water cleaning Drying the wafer within 60 seconds.

そして、前記a)〜c)工程が、同一のスピンナー上
で実施されることを特徴とする。
Then, the steps a) to c) are performed on the same spinner.

また、本発明の半導体装置の製造方法は、高融点金属
シリサイドおよび多結晶シリコン膜の2層構造の電極ま
たは配線を有する半導体装置の製造方法であって、ウェ
ーハ上に前記多結晶シリコン膜形成後、前記高融点金属
シリサイド形成前に、a)前記多結晶シリコン膜表面の
表面酸化膜をHFを含んだ水溶液で除去する工程、b)ア
ンモニア過水水溶液で洗浄する工程、c)前記アンモニ
ア過水水溶液の洗浄工程によって前記多結晶シリコン膜
上に生じた自然酸化膜を2%以下のHFを含んだ水溶液で
除去する工程、d)しかるのちに純水洗浄を行う工程、
e)前記純水洗浄後、ウェーハ表面に付着した前記純水
を乾燥させる工程、を有することを特徴とする。
Further, the method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an electrode or a wiring having a two-layer structure of a refractory metal silicide and a polycrystalline silicon film. A) a step of removing a surface oxide film on the surface of the polycrystalline silicon film with an aqueous solution containing HF before the formation of the refractory metal silicide; b) a step of washing with an aqueous ammonia / hydrogen peroxide solution; Removing a natural oxide film formed on the polycrystalline silicon film by an aqueous solution cleaning step with an aqueous solution containing 2% or less of HF, d) then performing pure water cleaning,
e) after the pure water cleaning, drying the pure water attached to the wafer surface.

そして、前記c)〜e)工程が、同一のスピンナー上
で実施されることを特徴とする。
Then, the steps c) to e) are performed on the same spinner.

〔実施例〕〔Example〕

以下、実施例を用いて本発明を説明する。第1図〜第
4図は、本発明による半導体装置製造方法の工程断面図
を示す。第1図において、Si基板1上には、素子分離Si
O22,ゲート薄膜SiO23が形成され、ゲート電極polycide
の下層のn+poly−Si4が形成されている。該n+poly−Si4
上には、n+拡散時に形成されたPSG5が存在する。このPS
Gは、HF水溶液で除去する。実施例では、HF:H2O=1:4
30秒で除去している。この時、同一スピンナーを用い
て、HFによるPSGエッチング除去,水洗,乾燥を連続的
に処理すれば、局所的なSiO2薄膜の発生を回避すること
ができる。しかしながら、若干濃度の高い(HF:H2O=1:
4)HF水溶液でPSG除去した場合、パーティクルの付着が
多くなるという欠点が残る。そこで、1:4によるPSG除去
後、アンモニア過水(NH4OH:H2O2:H2O=1:1:6,60℃)に
て表面を洗浄,水洗しパーティクルを除去した。さら
に、アンモニア過水洗浄によって生じたn+poly−Si上全
面に存在する自然酸化膜を、希HF水溶液(HF:H2O=1:20
0)により除去する。この時、ウエーハはスピンナーに
載り、ウエーハが回転している状態で、該希HF水溶液を
吹きかけることによりSiO2を除去している。さらに、同
一スピンナーにて、純水洗浄及びスピン乾燥を行なって
いる。2%以下の低濃度HF溶液ではパーティクル付着が
少なく、しかも、水洗後のスピン乾燥が、水洗後10秒以
内に行なわれるため、局所的SiO2の発生も無い。第3図
では、スピン乾燥後、Wシリサイド6(Ti,Mo,Taなど高
融点金属シリサイドでも同じ効果を得る)をCVDまたは
スパッタにより形成している。第4図では、polycideゲ
ート電極4,6をパターニング後、ソース・ドレイン7を
形成して得られるMOSFETの断面図が示されている。
Hereinafter, the present invention will be described with reference to examples. 1 to 4 are sectional views showing the steps of a method for manufacturing a semiconductor device according to the present invention. In FIG. 1, an element isolation Si is provided on a Si substrate 1.
O 2 2, gate thin SiO 2 3 is formed, the gate electrode polycide
Is formed as a lower layer of n + poly-Si4. The n + poly-Si4
Above is PSG5, formed during n + diffusion. This PS
G is removed with an aqueous HF solution. In the embodiment, HF: H 2 O = 1: 4
Removed in 30 seconds. At this time, if the same spinner is used to continuously perform PSG etching removal by HF, washing with water, and drying, local generation of a SiO 2 thin film can be avoided. However, the concentration is slightly higher (HF: H 2 O = 1:
4) When PSG is removed with an HF aqueous solution, there remains a disadvantage that particles adhere more. Then, after removing PSG by 1: 4, the surface was washed with ammonia peroxide (NH 4 OH: H 2 O 2 : H 2 O = 1: 1: 6, 60 ° C.) and washed with water to remove particles. Further, a natural oxide film existing on the entire surface of the n + poly-Si generated by the cleaning with ammonia and hydrogen peroxide is coated with a dilute HF aqueous solution (HF: H 2 O = 1: 20).
0) to remove. At this time, the wafer is placed on a spinner, and while the wafer is rotating, the diluted HF aqueous solution is sprayed to remove SiO 2 . Further, pure water washing and spin drying are performed by the same spinner. In a low concentration HF solution of 2% or less, particle adhesion is small, and spin drying after water washing is performed within 10 seconds after water washing, so that there is no local generation of SiO 2 . In FIG. 3, after spin-drying, W silicide 6 (the same effect is obtained with a high melting point metal silicide such as Ti, Mo, Ta, etc.) is formed by CVD or sputtering. FIG. 4 is a cross-sectional view of a MOSFET obtained by forming the source / drain 7 after patterning the polycide gate electrodes 4 and 6.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明の半導体装置の製造方法
によれば、polycide構造を持つゲート電極(及び配線)
における多結晶Siと高融点金属シリサイドの密着性及び
電気的オーミックコンタクト性が向上し、高歩留りかつ
高信頼性の半導体製造が可能になる。
As described above, according to the method for manufacturing a semiconductor device of the present invention, the gate electrode (and the wiring) having the polycide structure
In this case, the adhesion between polycrystalline Si and the refractory metal silicide and the electrical ohmic contact are improved, and a semiconductor with high yield and high reliability can be manufactured.

【図面の簡単な説明】[Brief description of the drawings]

第1図〜第4図は、本発明による半導体装置製造方法の
工程断面図。 1……Si基板 2……SiO2 3……SiO2 4……n+poly−Si 5……PSG 6……WSi2 7……ソース・ドレイン
1 to 4 are process cross-sectional views of a semiconductor device manufacturing method according to the present invention. 1 ...... Si substrate 2 ...... SiO 2 3 ...... SiO 2 4 ...... n + poly-Si 5 ...... PSG 6 ...... WSi 2 7 ...... drain

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/28 - 21/288 H01L 21/3205 H01L 21/336 H01L 21/768 H01L 29/78 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/28-21/288 H01L 21/3205 H01L 21/336 H01L 21/768 H01L 29/78

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】多結晶シリコン膜上に高融点金属シリサイ
ド膜が形成されたポリサイド構造の電極又は配線を有す
る半導体装置の製造方法であって、多結晶シリコン膜を
形成した後、この多結晶シリコン膜上に高融点金属シリ
サイド膜を形成する前に、 a)多結晶シリコン膜の表面に生じる表面酸化膜をHFを
含んだ水溶液で除去する工程と、 b)ウェーハを純水洗浄する工程と、 c)純水洗浄工程後60秒以内にウェーハを乾燥させる工
程と、をこの順序で有することを特徴とする半導体装置
の製造方法。
1. A method of manufacturing a semiconductor device having an electrode or a wiring having a polycide structure in which a refractory metal silicide film is formed on a polycrystalline silicon film, comprising: forming a polycrystalline silicon film; Before forming a refractory metal silicide film on the film, a) removing a surface oxide film formed on the surface of the polycrystalline silicon film with an aqueous solution containing HF, and b) cleaning the wafer with pure water. c) a step of drying the wafer within 60 seconds after the pure water cleaning step in this order.
【請求項2】請求項1に記載の半導体装置の製造方法に
おいて、前記a)〜c)の工程を同一のスピンナーにて
行うことを特徴とする半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the steps a) to c) are performed by the same spinner.
【請求項3】多結晶シリコン膜上に高融点金属シリサイ
ド膜が形成されたポリサイド構造の電極又は配線を有す
る半導体装置の製造方法であって、多結晶シリコン膜を
形成した後、この多結晶シリコン膜上に高融点金属シリ
サイド膜を形成する前に、 a)多結晶シリコン膜の表面に生じる表面酸化膜をHFを
含んだ水溶液で除去する工程と、 b)ウェーハをアンモニア過水水溶液で洗浄する工程
と、 c)前記アンモニア過水水溶液の洗浄工程によって前記
多結晶シリコン膜上に生じる自然酸化膜を2%以下のHF
を含んだ水溶液で除去する工程と、 d)ウェーハを純水洗浄する工程と、 e)純水洗浄工程後ウェーハを乾燥させる工程と、をこ
の順序で有することを特徴とする半導体装置の製造方
法。
3. A method of manufacturing a semiconductor device having an electrode or a wiring having a polycide structure in which a refractory metal silicide film is formed on a polycrystalline silicon film, comprising: forming a polycrystalline silicon film; Before forming a refractory metal silicide film on the film, a) removing a surface oxide film formed on the surface of the polycrystalline silicon film with an aqueous solution containing HF; and b) cleaning the wafer with an aqueous ammonia / hydrogen peroxide solution And c) reducing the natural oxide film formed on the polycrystalline silicon film by the washing step of the aqueous ammonia and hydrogen peroxide solution to 2% or less of HF.
And d) a step of cleaning the wafer with pure water, and e) a step of drying the wafer after the pure water cleaning step in this order. .
【請求項4】請求項3に記載の半導体装置の製造方法に
おいて、純水洗浄工程後60秒以内に前記e)工程を行う
ことを特徴とする半導体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 3, wherein the step e) is performed within 60 seconds after the pure water cleaning step.
【請求項5】請求項3又は4に記載の半導体装置の製造
方法において、前記c)〜e)の工程を同一のスピンナ
ーにて行うことを特徴とする半導体装置の製造方法。
5. The method for manufacturing a semiconductor device according to claim 3, wherein the steps c) to e) are performed by the same spinner.
JP20897990A 1990-08-07 1990-08-07 Method for manufacturing semiconductor device Expired - Fee Related JP3123065B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20897990A JP3123065B2 (en) 1990-08-07 1990-08-07 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20897990A JP3123065B2 (en) 1990-08-07 1990-08-07 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0492431A JPH0492431A (en) 1992-03-25
JP3123065B2 true JP3123065B2 (en) 2001-01-09

Family

ID=16565329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20897990A Expired - Fee Related JP3123065B2 (en) 1990-08-07 1990-08-07 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3123065B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09115869A (en) * 1995-08-10 1997-05-02 Seiko Epson Corp Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0492431A (en) 1992-03-25

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