JP3114735B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3114735B2 JP3114735B2 JP02418879A JP41887990A JP3114735B2 JP 3114735 B2 JP3114735 B2 JP 3114735B2 JP 02418879 A JP02418879 A JP 02418879A JP 41887990 A JP41887990 A JP 41887990A JP 3114735 B2 JP3114735 B2 JP 3114735B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- metal layer
- semiconductor substrate
- metal film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明はトランジスタ、サイリス
タ等の半導体装置の製造方法に関し、詳細には、半導体
基板の主面に相対的に厚い第１の電極とこれとは離間し
て形成された相対的に薄い制御電極やＥＱＲ等の第２の
電極を備えた半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a transistor or a thyristor, and more particularly, to a relatively thick first electrode formed on a main surface of a semiconductor substrate and spaced apart from the first electrode. The present invention relates to a method for manufacturing a semiconductor device including a relatively thin control electrode and a second electrode such as an EQR.
【０００２】[0002]
【従来の技術】図５は従来のサイリスタの第１の主電極
（カソード電極）が形成された側のチップ構造を示す。
このチップは半導体基板１と、絶縁膜２と、カソード電
極３と、制御電極（ゲート電極）４と、ＥＱＲ（等電位
リング）５を備えている。このサイリスタチップを得る
時にはまず、Ｎ−型領域、Ｐ型領域、Ｎ＋型領域が図示
のように形成された半導体基板１を用意し、この一方の
主面の全体にＳｉＯ２等から成る絶縁膜を形成する。次
に、この絶縁膜にエッチングを施して開口６、７、８を
有する絶縁膜２を形成する。続いて、この半導体基板１
の上面全体にＡｌ（アルミニウム）等から成る金属膜を
形成し、これに所定のエッチングを施してこの金属膜を
カソード電極３とゲート電極４とＥＱＲ５に相当する部
分に分離する。2. Description of the Related Art FIG. 5 shows a chip structure on a side of a conventional thyristor on which a first main electrode (cathode electrode) is formed.
The chip includes a semiconductor substrate 1, an insulating film 2, a cathode electrode 3, a control electrode (gate electrode) 4, and an EQR (equipotential ring) 5. First, when obtaining the thyristor chip, N - -type region, P-type region, N + -type region is a semiconductor substrate 1 formed as shown, the insulation made of SiO 2 or the like to the whole of the one main surface Form a film. Next, this insulating film is etched to form an insulating film 2 having openings 6, 7, and 8. Subsequently, the semiconductor substrate 1
A metal film made of Al (aluminum) or the like is formed on the entire upper surface of the substrate, and this metal film is subjected to predetermined etching to separate the metal film into portions corresponding to the cathode electrode 3, the gate electrode 4, and the EQR5.
【０００３】[0003]
【発明が解決しようとする課題】ところで、この種の半
導体装置において主電極の電流容量を増大する手段とし
て、これを構成する金属膜の厚みを大きくすることは知
られている。図５のサイリスタにおいては、電流容量を
増大するためにカソード電極３を厚く形成する。しか
し、従来の製造方法でカソード電極３を厚く形成するた
めには、厚い金属膜にエッチングを施してこれをカソー
ド電極３、ゲート電極４及びＥＱＲ５に分離しなければ
ならず、横方向（半導体基板の主面が延在する方向）に
進むエッチングいわゆる横方向エッチングの影響が無視
できなくなる。このため、例えば幅狭のＥＱＲ５を良好
に形成することが困難となる。この問題は、サイリスタ
に限られずトランジスタ等においても同様に生じる。As a means for increasing the current capacity of the main electrode in this type of semiconductor device, it is known to increase the thickness of a metal film forming the main electrode. In the thyristor of FIG. 5, the cathode electrode 3 is formed thick to increase the current capacity. However, in order to form the cathode electrode 3 thick by the conventional manufacturing method, a thick metal film must be etched and separated into the cathode electrode 3, the gate electrode 4, and the EQR5, and the lateral direction (semiconductor substrate). (The direction in which the main surface extends), the influence of so-called lateral etching cannot be ignored. For this reason, for example, it is difficult to form a narrow EQR5 well. This problem occurs not only in thyristors but also in transistors and the like.
【０００４】そこで本発明は、肉厚の異なる第１及び第
２の電極を容易且つ良好に形成することができる半導体
装置の製造方法を提供することを目的とする。Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device in which first and second electrodes having different thicknesses can be formed easily and satisfactorily.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
の本発明は、半導体基板の主面上に第１及び第２の電極
を有する半導体装置の製造方法において、前記半導体基
板の前記主面上の前記第１の電極の形成予定領域に下側
金属層を形成する工程と、前記半導体基板の前記主面上
の前記第２の電極の形成予定領域及び前記下側金属層を
覆うように前記下側金属層よりも薄い金属膜を形成する
工程と、前記金属膜を選択的にエッチングすることによ
って前記第２の電極の形成予定領域に前記金属膜を残存
させて前記第２の電極を得ると共に、前記下側金属層の
上にも前記金属膜を残存させて前記第２の電極よりも厚
い前記第１の電極を得る工程とを含むことを特徴とする
半導体装置の製造方法に係わるものである。According to the present invention, there is provided a method of manufacturing a semiconductor device having first and second electrodes on a main surface of a semiconductor substrate. Forming a lower metal layer in an upper region where the first electrode is to be formed, and covering the lower electrode layer and a region where the second electrode is to be formed on the main surface of the semiconductor substrate. Forming a metal film thinner than the lower metal layer ; and selectively etching the metal film to leave the metal film in a region where the second electrode is to be formed, thereby forming the second electrode. And obtaining the first electrode thicker than the second electrode by leaving the metal film also on the lower metal layer. Things.
【０００６】[0006]
【作用】本発明では第１の電極が下側金属層とこれに重
なる上側金属層から成るので、第２の電極よりも厚くな
り、電流容量が増大する。第２の電極は第１の電極の上
側金属層と同一の比較的薄い金属膜をエッチングして得
るので、横方向エッチングの影響をあまり受けずに形成
することができる。したがって、微細なパターンに形成
することが可能である。According to the present invention, since the first electrode is composed of the lower metal layer and the upper metal layer overlapping the lower metal layer, the first electrode is thicker than the second electrode and the current capacity is increased. Since the second electrode is obtained by etching the same relatively thin metal film as the upper metal layer of the first electrode, the second electrode can be formed without being largely affected by the lateral etching. Therefore, it is possible to form a fine pattern.
【０００７】[0007]
【実施例】次に、図１〜図４を参照して本発明の実施例
に係わるサイリスタの製造方法を説明する。まず、図１
に示すように、従来と同様にエピタキシャル成長法や拡
散技術によってＮ−型領域１ａ、Ｐ型領域１ｂ及びＮ＋
型領域１ｃ、１ｄが形成されたシリコン半導体基板１を
用意する。Next, a method for manufacturing a thyristor according to an embodiment of the present invention will be described with reference to FIGS. First, FIG.
As shown in FIG. 2, N - type region 1a, P-type region 1b, and N +
The silicon semiconductor substrate 1 on which the mold regions 1c and 1d are formed is prepared.
【０００８】次に、図２に示すように、半導体基板１の
上面（一方の主面）の全体にシリコン酸化膜を形成し、
これにエッチングを施して開口６、７、８を有する絶縁
膜２を形成する。開口６、７、８からはそれぞれＮ＋型
領域１ｃ、Ｐ型領域１ｂ及びＮ＋型領域１ｄが露出す
る。Next, as shown in FIG. 2, a silicon oxide film is formed on the entire upper surface (one main surface) of the semiconductor substrate 1.
This is etched to form an insulating film 2 having openings 6, 7, and 8. The N + -type region 1c, the P-type region 1b, and the N + -type region 1d are exposed from the openings 6, 7, and 8, respectively.
【０００９】次に、半導体基板１の上面全体にカソード
電極の下側金属層を形成するための金属膜を設ける。こ
の金属膜は相対的に厚い約８μｍの厚さを有するＡｌ
（アルミニウム）から成る。続いて、この金属膜の素子
外周側をエッチングで除去して図３に示すように、カソ
ード電極の下側金属層３ａを形成する。相対的に厚い金
属層３ａの外周側は横方向エッチングの影響によって若
干傾斜する。下側金属層３ａは、平面的に見て開口６の
内側に配設されており、開口６に露出するＮ＋型領域１
ｃと低抵抗接触（オーミックコンタクト）する。Next, a metal film for forming a lower metal layer of the cathode electrode is provided on the entire upper surface of the semiconductor substrate 1. This metal film has a relatively thick Al thickness of about 8 μm.
(Aluminum). Subsequently, the element outer peripheral side of the metal film is removed by etching to form a lower metal layer 3a of the cathode electrode as shown in FIG. The outer peripheral side of the relatively thick metal layer 3a is slightly inclined due to the influence of the lateral etching. The lower metal layer 3a is disposed inside the opening 6 when viewed in a plan view, and the N + type region 1 exposed in the opening 6 is provided.
Low resistance contact (ohmic contact) with c.
【００１０】次に、半導体基板１の上面全体に上記の下
側金属層３ａに重ねてカソード電極の上側金属層、ゲー
ト電極及びＥＱＲを構成するための金属膜を設ける。こ
の金属膜は相対的に薄い約６μｍの厚さのＡｌから成
る。続いて、この金属膜にエッチングを施して、図４に
示すように互いに離間して配設されたカソード電極の上
側金属層３ｂ、ゲート電極４及びＥＱＲ５を形成する。
相対的に薄い金属膜をエッチングして得られた上側金属
層３ｂ、ゲート電極４及びＥＱＲ５の外周部は横方向エ
ッチングの影響で若干傾斜するが無視できる程度であ
る。上側金属層３ｂは平面的に見て下側金属層３ａを被
覆し、更に開口６の外側の絶縁膜２の上まで延在してい
る。下側金属層３ａと上側金属層３ｂが構成されるカソ
ード電極３のボンディングパッド部即ちリード細線等の
取出し電極が接続される部分は、下側金属層３ａと上側
金属層３ｂが重なった二層構造となっており、その厚み
は約１４μｍとゲート電極４及びＥＱＲ５に比べて厚く
なっている。また、ゲート電極４及びＥＱＲ５はそれぞ
れ開口７、８を通じてＰ型領域１ｂ及びＮ＋型領域１ｄ
にオーミックコンタクトしている。Next, a metal film for forming the upper metal layer of the cathode electrode, the gate electrode, and the EQR is provided on the entire upper surface of the semiconductor substrate 1 so as to overlap the lower metal layer 3a. This metal film is made of relatively thin Al having a thickness of about 6 μm. Subsequently, this metal film is etched to form the upper metal layer 3b of the cathode electrode, the gate electrode 4, and the EQR5 which are arranged apart from each other as shown in FIG.
The outer peripheral portions of the upper metal layer 3b, the gate electrode 4, and the EQR5 obtained by etching a relatively thin metal film are slightly inclined by the influence of the lateral etching, but are negligible. The upper metal layer 3b covers the lower metal layer 3a in plan view, and further extends over the insulating film 2 outside the opening 6. The bonding pad portion of the cathode electrode 3 where the lower metal layer 3a and the upper metal layer 3b are formed, that is, the portion to which the extraction electrode such as a thin lead wire is connected is a two-layer structure in which the lower metal layer 3a and the upper metal layer 3b overlap. The thickness is about 14 μm, which is thicker than the gate electrode 4 and the EQR 5. Further, the gate electrode 4 and the EQR 5 are respectively connected to the P-type region 1b and the N + -type region 1d through the openings 7 and 8.
Ohmic contact.
【００１１】本実施例は次の効果を有する。 （１） 第１の電極としてのカソード電極３のボンディ
ングパッド部が厚く形成される。このため、電流容量が
大きくとれる。 （２） 第２の電極としてのゲート電極４及びＥＱＲ５
は比較的薄い金属膜をエッチングして形成するので、横
方向エッチングの影響が小さい。したがって、微細な金
属電極パターンを精度良く形成でき、幅狭の小さいＥＱ
Ｒ５も良好に形成できる。This embodiment has the following effects. (1) The bonding pad portion of the cathode electrode 3 as the first electrode is formed thick. Therefore, a large current capacity can be obtained. (2) Gate electrode 4 as second electrode and EQR5
Is formed by etching a relatively thin metal film, so that the influence of lateral etching is small. Therefore, a fine metal electrode pattern can be formed with high precision, and a narrow EQ can be formed.
R5 can also be formed favorably.
【００１２】[0012]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。（１） 第２の電極としてＥＱＲのみを備えた半導体装置
等にも有効である。（２） 上側金属層、ゲート電極、ＥＱＲを形成するため
の金属膜の厚みは横方向エッチングの影響をあまり受け
ないように、最も細く形成されるパターン（実施例では
ＥＱＲの幅）の1/5 以下とするのが実用的である。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The present invention is also effective for a semiconductor device having only EQR as the second electrode. (2) The thickness of the upper metal layer, the gate electrode, and the metal film for forming the EQR are 1 / th of the thinnest pattern (the width of the EQR in the embodiment) so as not to be greatly affected by the lateral etching. It is practical to set it to 5 or less.
【００１３】[0013]
【発明の効果】上述から明らかなように本発明によれ
ば、第１の電極による電流容量の増大と、第２の電極の
パターン精度の向上との両方を容易に達成することがで
きる。As apparent from the above, according to the present invention, it is possible to easily achieve both an increase in the current capacity by the first electrode and an improvement in the pattern accuracy of the second electrode.
【図１】本発明の実施例に係わるサイリスタの製造方法
を説明するための半導体基板の断面図である。FIG. 1 is a sectional view of a semiconductor substrate for explaining a method of manufacturing a thyristor according to an embodiment of the present invention.
【図２】絶縁膜を設けた半導体基板を示す断面図であ
る。FIG. 2 is a cross-sectional view illustrating a semiconductor substrate provided with an insulating film.
【図３】下側金属層を設けた半導体基板の断面図であ
る。FIG. 3 is a sectional view of a semiconductor substrate provided with a lower metal layer.
【図４】上側金属層を設けた半導体基板の断面図であ
る。FIG. 4 is a cross-sectional view of a semiconductor substrate provided with an upper metal layer.
【図５】従来のサイリスタを示す断面図である。FIG. 5 is a sectional view showing a conventional thyristor.
１ 半導体基板 ２ 絶縁膜 ３ａ 下側金属層 ３ｂ 上側金属層 ４ ゲート電極 ５ ＥＱＲ Reference Signs List 1 semiconductor substrate 2 insulating film 3a lower metal layer 3b upper metal layer 4 gate electrode 5 EQR
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/74 H01L 21/28 301 H01L 21/331 H01L 29/73 H01L 29/78 652 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 29/74 H01L 21/28 301 H01L 21/331 H01L 29/73 H01L 29/78 652
Claims (1)
極を有する半導体装置の製造方法において、 前記半導体基板の前記主面上の前記第１の電極の形成予
定領域に下側金属層を形成する工程と、 前記半導体基板の前記主面上の前記第２の電極の形成予
定領域及び前記下側金属層を覆うように前記下側金属層
よりも薄い金属膜を形成する工程と、 前記金属膜を選択的にエッチングすることによって前記
第２の電極の形成予定領域に前記金属膜を残存させて前
記第２の電極を得ると共に、前記下側金属層の上にも前
記金属膜を残存させて前記第２の電極よりも厚い前記第
１の電極を得る工程とを含むことを特徴とする半導体装
置の製造方法。1. A method of manufacturing a semiconductor device having a first electrode and a second electrode on a main surface of a semiconductor substrate, wherein a lower metal is formed in a region where the first electrode is to be formed on the main surface of the semiconductor substrate. Forming a layer; and forming the lower metal layer so as to cover a region where the second electrode is to be formed on the main surface of the semiconductor substrate and the lower metal layer.
Forming a thinner metal film; and selectively etching the metal film to leave the metal film in a region where the second electrode is to be formed, thereby obtaining the second electrode. Obtaining the first electrode thicker than the second electrode by leaving the metal film also on the side metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02418879A JP3114735B2 (en) | 1990-12-29 | 1990-12-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02418879A JP3114735B2 (en) | 1990-12-29 | 1990-12-29 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04242975A JPH04242975A (en) | 1992-08-31 |
| JP3114735B2 true JP3114735B2 (en) | 2000-12-04 |
Family
ID=18526634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02418879A Expired - Lifetime JP3114735B2 (en) | 1990-12-29 | 1990-12-29 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3114735B2 (en) |
-
1990
- 1990-12-29 JP JP02418879A patent/JP3114735B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04242975A (en) | 1992-08-31 |
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