JP3090240B2 - AD converter test equipment - Google Patents
AD converter test equipmentInfo
- Publication number
- JP3090240B2 JP3090240B2 JP04326903A JP32690392A JP3090240B2 JP 3090240 B2 JP3090240 B2 JP 3090240B2 JP 04326903 A JP04326903 A JP 04326903A JP 32690392 A JP32690392 A JP 32690392A JP 3090240 B2 JP3090240 B2 JP 3090240B2
- Authority
- JP
- Japan
- Prior art keywords
- logic
- output
- conversion output
- expected value
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は例えばＡＤ変換器試験
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an AD converter test apparatus.
【０００２】[0002]
【従来の技術】図４にＡＤ変換器を試験する場合の試験
装置の構成を示す。図中１はパターン発生器を示す。パ
ターン発生器１は被試験ＡＤ変換器２に与えるアナログ
信号ＡＬと、このアナログ信号ＡＬを正しくＡＤ変換し
た期待値パターン信号ＥＸＰＨ，ＥＸＰＬを発生する。
期待値パターン信号ＥＸＰＨ，ＥＸＰＬは被試験ＡＤ変
換器２のＡＤ変換出力信号ＡＤOUT と共に論理比較器３
に与えられ、論理比較器３において論理比較され期待値
と不一致が発生したとき不良と判定し、不良解析メモリ
４に不良を表わすデータを書込む。2. Description of the Related Art FIG. 4 shows a configuration of a test apparatus for testing an AD converter. In the figure, reference numeral 1 denotes a pattern generator. The pattern generator 1 generates an analog signal AL to be supplied to the AD converter under test 2 and expected value pattern signals EXPH and EXPL obtained by correctly AD-converting the analog signal AL.
The expected value pattern signals EXPH and EXPL are output to the logical comparator 3 together with the AD conversion output signal AD OUT of the AD converter 2 under test.
When a logical comparison is made in the logical comparator 3 and a mismatch with the expected value occurs, it is determined to be a failure, and data representing the failure is written to the failure analysis memory 4.
【０００３】論理比較器３は期待値との不一致を表わす
不良表示信号ＦＭＦと、被試験ＡＤ変換器２のＡＤ変換
出力ＡＤOUT の各ビットの論理状態を表わすエラー論理
情報ＦＭＣとを出力する。不良表示信号ＦＭＦはＡＤ変
換出力ＡＤOUT が期待値と不一致になったとき、「１」
論理を出力し、この「１」論理を不良表示信号として第
１不良解析メモリ４に書込む。これと共にパターン発生
の順番を表わす番号も不良表示信号ＦＭＦと同一のアド
レスに書込む。このようにパターン発生の順番を表わす
番号（アドレスに相当する）を不良表示信号ＦＭＦと共
に第１不良解析メモリに書込むことにより、不良解析時
に不良発生の期待値パターンを特定することができる。The logic comparator 3 outputs a failure indication signal FMF indicating a mismatch with an expected value and error logic information FMC indicating a logic state of each bit of an AD conversion output AD OUT of the AD converter 2 under test. The failure display signal FMF is “1” when the AD conversion output AD OUT does not match the expected value.
Logic is output, and this "1" logic is written into the first failure analysis memory 4 as a failure display signal. At the same time, a number indicating the order of pattern generation is also written at the same address as the defect display signal FMF. By writing a number (corresponding to an address) indicating the order of pattern generation in the first failure analysis memory together with the failure display signal FMF, an expected value pattern of failure occurrence can be specified at the time of failure analysis.
【０００４】一方第２不良解析メモリ５には不良発生時
に被試験ＡＤ変換器２が出力したエラー論理情報ＦＭＣ
を書込む。このエラー論理情報を解析することにより、
どのビットの出力が「１」か「０」か何れで期待値と不
一致になったかを知ることができる。図５に論理比較器
３の具体的な構成を示す。図では被試験ＡＤ変換器２の
一つの出力端子のＡＤ変換出力ＡＤOUT を期待値と比較
する部分の構成を示す。図５において３Ａはアナログの
レベル比較部を示す。このレベル比較部３Ａに「１」論
理の基準電圧ＶOHと、「０」論理の基準電圧ＶOLとを与
え、入力信号ＡＤOUTの電圧がＶOHより高ければ「１」
論理と判定し、ＶOLより低ければ「０」論理と判定す
る。この判定結果はラッチ回路３Ｂ，３Ｃに入力され、
ストローブパルスＳＴＲＯＢＥにてラッチされる。ラッ
チ回路３Ｂと３Ｃのラッチ出力はそれぞれ正相出力端子
Ｑと、逆相の出力端子※Ｑとを有し、それぞれのラッチ
出力信号をＦＨ，ＦＺＨ，ＦＬ，ＦＺＬと呼ぶことにす
る。これらのラッチ出力信号ＦＨ，ＦＺＨ，ＦＬ，ＦＺ
Ｌはディジタル比較部３Ｄに入力される。このディジタ
ル比較部３Ｄにはラッチ出力信号ＦＨ，ＦＺＨ，ＦＬ，
ＦＺＬの外に期待値信号ＥＸＰＨ，※ＥＸＰＨ，ＥＸＰ
Ｌ，※ＥＸＰＬが入力され、これら期待値信号ＥＸＰ
Ｈ，※ＥＸＰＨ，ＥＸＰＬ，※ＥＸＰＬとラッチ出力信
号ＦＨ，ＦＺＨ，ＦＬ，ＦＺＬとがナンドゲート群で比
較され、その比較結果がオアゲートＯＲ1 とＯＲ 2 を通
じて取出され、不良表示信号ＦＭＦとエラー論理情報Ｆ
ＭＣとが出力される。On the other hand, when a failure occurs, the second failure analysis memory 5
Logic information FMC output from the AD converter 2 under test
Write. By analyzing this error logic information,
Which bit output is “1” or “0”,
You can know if they match. Figure 5 shows the logical comparator
3 shows a specific configuration. In the figure, the AD converter 2 under test is
AD conversion output AD of one output terminalOUTCompare with expected value
The configuration of the part to be performed is shown. In FIG. 5, 3A is an analog
5 shows a level comparison unit. "1" theory is applied to this level comparison unit 3A.
Reference voltage VOHAnd a reference voltage V of "0" logicOLAnd give
Input signal ADOUTVoltage is VOH"1" if higher
Judge as logic, VOLIf it is lower, it is determined to be "0" logic
You. This determination result is input to the latch circuits 3B and 3C,
It is latched by the strobe pulse STROBE. Luck
The latch outputs of the switch circuits 3B and 3C are positive-phase output terminals, respectively.
Q and output terminal of opposite phase
The output signals will be referred to as FH, FZH, FL, FZL.
You. These latch output signals FH, FZH, FL, FZ
L is input to the digital comparison unit 3D. This digital
The latch comparator 3D has latch output signals FH, FZH, FL,
Expectation signal EXPH, * EXPH, EXP outside FZL
L, * EXPL are input and these expected value signals EXP
H, * EXPH, EXPL, * EXPL and latch output signal
No. FH, FZH, FL, FZL are compared with NAND gate group
Are compared, and the comparison result is OR gate OR1And OR TwoThrough
The fault indication signal FMF and the error logic information F
MC is output.
【０００５】図６にＡＤ変換出力ＡＤOUT の論理と期待
値との比較結果を表にして示す。ＡＤ変換出力ＡＤOUT
がＨ，Ｚ，Ｌ（ＺはＨとＬの中間で高インピーダンス状
態を指す）の順に変化するとき、ラッチ出力ＦＨは
「０」，「１」，「１」、ラッチ出力ＦＬは「１」，
「１」，「０」と変化する。このとき期待値ＥＸＰＨ＝
「０」、ＥＸＰＬ＝「１」つまりＬ論理のとき不良表示
信号ＦＭＦは「１」，「１」「０」の順に変化する。こ
れの意味するところは期待値がＬ論理のときはＡＤ変換
出力ＡＤOUT がＬ論理のときだけ不良表示信号ＦＭＦは
「０」論理（良：ＰＡＳＳ）となり、他は「１」論理
（不良：ＦＡＩＬ）となることを表わしている。またエ
ラー論理情報ＦＭＣは「０」，「１」，「１」の順に変
化する。期待値がＬ論理のとき、エラー論理情報ＦＭＣ
が「０」論理のときはＡＤ変換出力ＡＤOUT がＨ論理
（ＶOHより高い電圧）になっている状態でＦＡＩＬとな
ったことを意味し、他の「１」論理はＡＤ変換出力ＡＤ
OUT がＶOHより低い論理に位置していることを表わして
いる。FIG. 6 is a table showing the comparison result between the logic of the AD conversion output AD OUT and the expected value. AD conversion output AD OUT
Change in the order of H, Z, L (Z indicates a high impedance state between H and L), the latch output FH is “0”, “1”, “1”, and the latch output FL is “1”. ,
It changes to “1” and “0”. At this time, the expected value EXPH =
When “0”, EXPL = “1”, that is, L logic, the failure display signal FMF changes in the order of “1”, “1”, and “0”. This means that when the expected value is L logic, the failure display signal FMF becomes “0” logic (good: PASS) only when the AD conversion output AD OUT is L logic, and “1” logic (bad: FAIL). The error logic information FMC changes in the order of “0”, “1”, and “1”. When the expected value is L logic, error logic information FMC
Is "0" logic, it means that the A / D conversion output AD OUT has become FAIL in the state of H logic (voltage higher than V OH ), and the other "1" logic is the A / D conversion output AD.
OUT indicates that it is located at a logic lower than V OH .
【０００６】従って不良表示信号ＦＭＦが「１」論理に
なる毎に、パターン発生の番号と共にエラー論理情報Ｆ
ＭＣを不良解析メモリに記憶しておくことによりパター
ン番号から期待値を知ることができるから、ＡＤ変換出
力ＡＤOUT がどの論理でＦＡＩＬとなったかを解析する
ことができる。期待値がＨ論理のとき、ＡＤ変換出力Ａ
ＤOUT がＨ，Ｚ，Ｌの順に変化すると、不良表示信号Ｆ
ＭＦは「０」，「１」，「１」の順に変化する。つまり
ＡＤ変換出力ＡＤOUT がＨ論理のときＰＡＳＳとなり、
ＡＤ変換出力ＡＤOUT がＺ，Ｌの状態では不良、ＦＡＩ
Ｌを表わす「１」論理を出力する。エラー論理情報ＦＭ
ＣはＡＤ変換出力ＡＤOUT がＨ，Ｚ，Ｌの順に変化する
とき「１」，「１」，「０」の順に変化する。つまりこ
のときはＡＤ変換出力ＡＤOUT がＶOLより高い電圧にあ
るときＦＭＣは「１」論理を出力し、ＶOLより低い電圧
のときＦＭＣは「０」論理となる。Therefore, every time the failure display signal FMF becomes "1" logic, the error logic information F together with the pattern generation number is displayed.
Since the expected value can be known from the pattern number by storing the MC in the failure analysis memory, it is possible to analyze which logic of the AD conversion output AD OUT is FAIL. When the expected value is H logic, AD conversion output A
When D OUT changes in the order of H, Z, and L, the defective display signal F
The MF changes in the order of “0”, “1”, “1”. That is, when the AD conversion output AD OUT is H logic, it becomes PASS,
Bad when AD conversion output AD OUT is in Z, L state, FAI
The logic "1" representing L is output. Error logic information FM
C changes in the order of “1”, “1”, and “0” when the AD conversion output AD OUT changes in the order of H, Z, and L. That is, at this time, when the AD conversion output AD OUT is at a voltage higher than V OL , the FMC outputs “1” logic, and when the AD conversion output AD OUT is at a voltage lower than V OL, the FMC becomes “0” logic.
【０００７】期待値が高インピーダンスＺのときＡＤ変
換出力ＡＤOUT がＨ，Ｚ，Ｌの順に変化すると不良表示
信号ＦＭＦは「１」，「０」，「１」と変化する。つま
りＡＤ変換出力ＡＤOUT がＶOHとＶOLの間にあるときだ
けＰＡＳＳと判定し、それ以外ではＦＡＩＬと判定する
ことを意味している。このときエラー論理情報ＦＭＣは
「０」，「０」，「１」と変化し、このときはＡＤ変換
出力ＡＤOUT がＶOLより高いとき「０」論理を出力し、
ＶOLより低いとき「１」論理を出力する。When the AD conversion output AD OUT changes in the order of H, Z, and L when the expected value is high impedance Z, the failure display signal FMF changes to “1”, “0”, and “1”. That is, PASS is determined only when the AD conversion output AD OUT is between V OH and V OL , and FAIL is determined otherwise. At this time, the error logic information FMC changes to “0”, “0”, “1”. At this time, when the AD conversion output AD OUT is higher than V OL , “0” logic is output,
When the voltage is lower than V OL , “1” logic is output.
【０００８】期待値がＸ（ドントケア）のときはＡＤ変
換出力ＡＤOUT がどの領域にあってもＰＡＳＳとなる。
以上の説明を要約して示すと、下記の表１のようにな
る。 表１ 期待値 “Ｌ” “Ｈ” “Ｚ” “Ｘ” Ｈ ＦＡＩＬ ＰＡＳＳ ＦＡＩＬ ＰＡＳＳ ＶOH────────・・────・・────・・───── Ｚ ＦＡＩＬ ＦＡＩＬ ＰＡＳＳ ＰＡＳＳ ＶOL────────・・────・・────・・───── Ｌ ＰＡＳＳ ＦＡＩＬ ＦＡＩＬ ＰＡＳＳWhen the expected value is X (don't care), PASS is set regardless of the area of the AD conversion output AD OUT .
Table 1 below summarizes the above description. Table 1 Expected values “L” “H” “Z” “X” H FAIL PASS FAIL PASS V OH ──────── ──── ──── ──── ───── Z FAIL FAIL PASS PASS V OL ──────── ·· ──── ·· ──── ·· ───── L PASS FAIL FAIL PASS
【０００９】[0009]
【発明が解決しようとする課題】被試験体がＡＤ変換器
の場合、連続的に変化するアナログ電圧をＡＤ変換する
ものであるから、ＡＤ変換出力ＡＤOUT の各ビットの論
理はサンプリングのタイミングのズレ等に応じて「１」
論理であるべきが「０」論理となったり、或はその逆に
なったりすることが多い。特に最下位桁（ＬＳＢ）のビ
ット及びこれに近いビットのＡＤ変換出力ＡＤOUT はビ
ット誤差により正確に期待値に合致しない場合が多い。
このため従来の試験装置によってＡＤ変換器を試験する
と不良の判定ばかり出されてしまう欠点がある。When the DUT is an A / D converter, the analog voltage that changes continuously is subjected to A / D conversion. Therefore, the logic of each bit of the A / D conversion output AD OUT is determined by the sampling timing. "1" according to the displacement
It should be logic, but often becomes "0" logic, or vice versa. In particular, the A / D conversion output AD OUT of the least significant bit (LSB) bit and a bit close to this bit often does not exactly match the expected value due to a bit error.
For this reason, there is a disadvantage that when the AD converter is tested by the conventional test apparatus, only a defect is determined.
【００１０】またＡＤ変換器の試験においては良否判定
試験を行なった後にＡＤ変換出力ＡＤOUT をメモリに取
込む作業を行なっている。つまりＡＤ変換出力ＡＤOUT
をメモリに取込み、このメモリに取込んだＡＤ変換出力
ＡＤOUT を例えば高速フーリエ変換装置に与えて周波数
分析し、不用な周波数スペクトルが発生していないか否
かを見る試験も合せて行なっている。In the test of the A / D converter, a work of loading the A / D conversion output AD OUT into a memory after performing a pass / fail judgment test is performed. That is, AD conversion output AD OUT
Is stored in a memory, and an AD conversion output AD OUT captured in the memory is supplied to, for example, a fast Fourier transform device to perform a frequency analysis, and a test is performed to check whether an unnecessary frequency spectrum is generated. .
【００１１】ＡＤ変換出力ＡＤOUT をメモリに取込むに
は、期待値をＨ論理に固定し、この状態でエラー論理情
報ＦＭＣを見ると、図６に示すようにＡＤ変換出力ＡＤ
OUTがＨ論理のとき、ＦＭＣ＝「１」、ＡＤ変換出力Ａ
ＤOUT がＬ論理のときＦＭＣ＝「０」となるからエラー
論理情報ＦＭＣを取出すことにより、ＡＤ変換出力ＡＤ
OUT を取出すことができる。In order to load the AD conversion output AD OUT into the memory, the expected value is fixed to H logic, and when the error logic information FMC is viewed in this state, as shown in FIG.
When OUT is H logic, FMC = "1", AD conversion output A
Since FMC becomes "0" when D OUT is at L logic, the error conversion information FMC is taken out to obtain the AD conversion output AD.
OUT can be taken out.
【００１２】然るにこの場合期待値をＨ論理に固定しな
ければならないから、良否判定試験とＡＤ変換出力ＡＤ
OUT の取込作業とを同時に実行することはできない。従
って従来は良否の判定作業と、ＡＤ変換出力ＡＤOUT の
メモリへの取込作業とを別々に実行しているため試験に
時間が掛る欠点がある。However, in this case, since the expected value must be fixed to the H logic, the pass / fail judgment test and the AD conversion output AD
OUT capture operation cannot be performed simultaneously. Therefore conventionally there is a disadvantage that the time test for running a determination work quality, and capture operations to memory AD conversion output AD OUT separately consuming.
【００１３】[0013]
【課題を解決するための手段】この発明ではＡＤ変換出
力ＡＤOUT の論理が期待値と一致しなくてもＡＤ変換出
力ＡＤOUT の論理がＨ論理か、Ｌ論理の何れか一方の状
態にあればＰＡＳＳと判定する論理比較手段を設けるも
のである。この論理比較手段によればＡＤ変換出力ＡＤ
OUT と期待値の論理が完全に一致しなくても、ＡＤ変換
出力ＡＤOUT がＨ論理か、Ｌ論理にあればＰＡＳＳと判
定し、Ｈ論理とＬ論理の中間の状態にあれば不良と判定
する。従って例えばＨ論理からＬ論理に移る動作、又は
Ｈ論理からＬ論理に移る動作が規定の時間以上掛るよう
な動作を検出することができ、この点でＡＤ変換器の不
良を検出することができる。Means for Solving the Problems The logic of AD conversion output AD OUT even not match the logic expected value of AD conversion output AD OUT in this invention or H logic, it is in one of states of logic L For example, a logical comparison means for determining PASS is provided. According to this logical comparison means, the AD conversion output AD
Even if the logic of OUT and the expected value do not completely match, if the AD conversion output AD OUT is H logic or L logic, it is judged as PASS, and if it is in the middle state between H logic and L logic, it is judged as defective. I do. Therefore, for example, it is possible to detect an operation in which the transition from the H logic to the L logic or the operation from the H logic to the L logic takes a predetermined time or more, and it is possible to detect a defect of the AD converter at this point. .
【００１４】またこの発明による論理比較手段で動作さ
せる場合、エラー論理情報はＡＤ変換出力ＡＤOUT の論
理と一致して取出すことができる。よって良否判定作業
と、ＡＤ変換出力ＡＤOUT の論理波形の取込作業とを一
度に平行して実行することができる。この結果試験に要
する時間を短かくするとができる利点も得られる。When operated by the logic comparison means according to the present invention, the error logic information can be extracted in accordance with the logic of the AD conversion output AD OUT . Therefore, the pass / fail judgment work and the work of taking in the logic waveform of the AD conversion output AD OUT can be executed at the same time. As a result, there is an advantage that the time required for the test can be shortened.
【００１５】[0015]
【実施例】図１にこの発明の一実施例を示す。図１にお
いて、図５と対応する部分には同一符号を付して示す。
この発明ではディジタル比較部３Ｄにモード切替手段１
０及び１１を設け、これらモード切替手段１０及び１１
において入力端子Ａを選択するときは、従来と全く同じ
モードで試験を行なうことができるが、入力端子Ｂを選
択すると、この発明で提案する論理比較手段として動作
する。FIG. 1 shows an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 5 are denoted by the same reference numerals.
According to the present invention, the mode switching means 1 is provided in the digital comparison unit 3D.
0 and 11 are provided, and these mode switching means 10 and 11 are provided.
When the input terminal A is selected, the test can be performed in exactly the same mode as in the prior art, but when the input terminal B is selected, it operates as the logical comparison means proposed in the present invention.
【００１６】つまりモード切替手段１０及び１１は入力
端子Ｓに与える論理値に応じて選択する入力端子が切替
られる。例えば入力端子ＳにＨ論理を与えると入力端子
Ａを選択し、入力端子ＳにＬ論理を与えると入力端子Ｂ
を選択する。モード切替手段１０が入力端子Ａを選択す
ると、図５に示した従来の装置と同様にラッチ出力ＦＺ
ＨとＦＺＬのノアゲート出力をナンドゲート群の一つの
入力端子に与える状態に切替られる。またモード切替手
段１０が入力端子Ｂを選択すると、この状態ではラッチ
出力ＦＨとＦＬをナンドゲートした出力をナンドゲート
群の一つの入力端子に与える状態に切替られる。この切
替によってオアゲートＯＲ1 から出力される不良表示信
号ＦＭＦはＡＤ変換出力ＡＤOUT がＨ論理か、Ｌ論理の
何れか一方の状態にあれば、期待値と論理が合致しなく
てもＦＭＦ＝「０」を出力し、ＰＡＳＳと判定する。That is, the input terminals to be selected by the mode switching means 10 and 11 are switched according to the logical value given to the input terminal S. For example, when H logic is applied to the input terminal S, the input terminal A is selected, and when L logic is applied to the input terminal S, the input terminal B is selected.
Select When the mode switching means 10 selects the input terminal A, the latch output FZ is set in the same manner as in the conventional device shown in FIG.
The state is switched to a state in which the NOR gate outputs of H and FZL are applied to one input terminal of the NAND gate group. When the mode switching means 10 selects the input terminal B, in this state, the state is switched to a state in which an output obtained by NAND gate of the latch outputs FH and FL is applied to one input terminal of the NAND gate group. By this switching, the failure display signal FMF output from the OR gate OR 1 is FMF = “FMF =“, even if the expected value and the logic do not match if the AD conversion output AD OUT is in either the H logic state or the L logic state. "0" is output, and PASS is determined.
【００１７】一方モード切替手段１１は入力端子Ａにオ
アゲートＯＲ2 の出力端子を接続し、入力端子Ｂに期待
値※ＥＸＰＨと※ＥＸＰＬのナンドゲート１２の出力を
取出すと共に、このナンドゲート１２の出力とオアゲー
トＯＲ2 の出力を排他的論理和回路１３で排他的論理を
とり、この排他的論理和をモード切替手段１１の入力端
子Ｂに与える構造としたものである。On the other hand, the mode switching means 11 connects the output terminal of the OR gate OR 2 to the input terminal A, takes out the outputs of the NAND gates 12 of the expected values * EXPH and * EXPL to the input terminal B, and outputs the outputs of the NAND gate 12 and the OR gate. The exclusive OR circuit 13 takes the exclusive OR of the output of the OR 2 and gives the exclusive OR to the input terminal B of the mode switching means 11.
【００１８】この発明の構成によれば図２に示すように
期待値をＺとし、モード切替手段１０と１１を入力端子
Ｂを選択するモードＢに切替ることによりＡＤ変換出力
ＡＤ OUT がＨ論理にあっても、Ｌ論理にあっても不良表
示信号ＦＭＦは「０」論理となりＰＡＳＳと判定する。
これに対し、ＡＤ変換出力ＡＤOUT がＺ領域に存在する
場合には不良表示信号ＦＭＦは「１」論理となり、不良
を表わす信号として出力される。According to the structure of the present invention, as shown in FIG.
The expected value is Z, and the mode switching means 10 and 11 are input terminals.
AD conversion output by switching to mode B for selecting B
AD OUTTable is bad regardless of whether it is in H logic or L logic
The indication signal FMF becomes “0” logic, and is determined as PASS.
On the other hand, the AD conversion output ADOUTExists in the Z region
In this case, the failure display signal FMF becomes logic "1",
Is output as a signal representing
【００１９】従って図３に示すようにＡＤ変換出力ＡＤ
OUT がストローブパルスＳＴＲＯＢＥのタイミングにお
いてＨ論理かＬ論理に存在すればＰＡＳＳと判定される
が、論理の反転動作に時間が掛り、ストローブパルスＳ
ＴＲＯＢＥのタイミングにおいてＡＤ変換出力ＡＤOUT
が高インピーダンス領域Ｚに存在する場合はＦＡＩＬと
判定される。Therefore, as shown in FIG.
If OUT is in H logic or L logic at the timing of the strobe pulse STROBE, it is determined to be PASS. However, the logic inversion operation takes time, and the strobe pulse S
AD conversion output AD OUT at TROBE timing
Is present in the high impedance region Z, it is determined as FAIL.
【００２０】一方この状態（期待値がＺでモードＢ）に
おいて、エラー論理情報ＦＭＣはＡＤ変換出力ＡＤOUT
がＨ論理のとき図２に示すようにＦＭＣ＝「１」、ＡＤ
変換出力ＡＤOUT がＬ論理のときＦＭＣ＝「０」とな
る。よってこのエラー論理情報ＦＭＣをメモリに取込む
ことにより、実質的にＡＤ変換出力ＡＤOUT を取込んだ
と等価となる。On the other hand, in this state (the expected value is Z and the mode is B), the error logic information FMC contains the AD conversion output AD OUT
Is H logic, as shown in FIG.
When the conversion output AD OUT is at L logic, FMC = "0". Thus by taking the error logic information FMC to memory, it becomes substantially equivalent to the taken AD conversion output AD OUT.
【００２１】[0021]
【発明の効果】以上説明したように、この発明によれば
従来と同等の試験の外に、ＡＤ変換出力ＡＤOUT の各ビ
ットの信号の論理がＨ論理か、Ｌ論理の何れの論理に存
在すればＰＡＳＳと判定し、高インピーダンス領域に存
在する場合は不良と判定する試験を行なうことができ
る。よってＡＤ変換出力ＡＤOUT の論理反転が遅れるよ
うな不良現象を検出することができる。As described above, according to the present invention, in addition to the same test as the prior art According to the present invention, logic or H logic of each bit of the signal of the AD converter output AD OUT, present in any logic L logic In this case, a test can be performed in which the signal is determined to be PASS, and when the signal is present in the high impedance region, the signal is determined to be defective. Therefore, it is possible to detect a defect phenomenon in which the logic inversion of the AD conversion output AD OUT is delayed.
【００２２】またこの試験と平行してＡＤ変換出力ＡＤ
OUT と等価な信号（ＦＭＣ）取出すことができるから、
良否判定作業と、ＡＤ変換出力ＡＤOUT の信号の取込作
業を同時に実行することができる。従って試験時間を短
縮することができる利点が得られる。In parallel with this test, the AD conversion output AD
Since the signal equivalent to OUT (FMC) can be extracted,
The pass / fail judgment work and the work of taking in the signal of the AD conversion output AD OUT can be performed simultaneously. Therefore, the advantage that the test time can be shortened is obtained.
【図１】この発明の一実施例を示す接続図。FIG. 1 is a connection diagram showing one embodiment of the present invention.
【図２】この発明の動作を説明するための図。FIG. 2 is a diagram for explaining the operation of the present invention.
【図３】この発明の動作を説明するための波形図。FIG. 3 is a waveform chart for explaining the operation of the present invention.
【図４】ＡＤ変換器を試験する場合の試験装置全体の概
略の構成を説明するためのブロック図。FIG. 4 is a block diagram for explaining a schematic configuration of an entire test apparatus when testing an AD converter.
【図５】従来の技術を説明するための接続図。FIG. 5 is a connection diagram for explaining a conventional technique.
【図６】従来の技術の動作を説明するための図。FIG. 6 is a diagram for explaining the operation of the conventional technique.
１ パターン発生器 ２ 被試験ＡＤ変換器 ３ 論理比較器 ４ 第１不良解析メモリ ５ 第２不良解析メモリ １０，１１ モード切替手段 REFERENCE SIGNS LIST 1 pattern generator 2 AD converter under test 3 logical comparator 4 first failure analysis memory 5 second failure analysis memory 10, 11 mode switching means
Claims (1)
え、そのＡＤ変換出力を論理比較器において期待値と論
理比較し、ＡＤ変換出力が期待値と不一致が発生したと
き、不良と判定するＡＤ変換器試験装置において、 ＡＤ変換出力が期待値の論理に関係なくＨ論理又はＬ論
理の何れかに存在する場合を良と判定し、Ｈ論理とＬ論
理の中間に存在する場合を不良と判定する論理判定手段
を設けたことを特徴とするＡＤ変換器試験装置。An analog signal is supplied to an AD converter under test, the AD converted output is logically compared with an expected value in a logical comparator, and when the AD converted output does not match the expected value, the AD which is determined to be defective is determined. In the converter test device, the case where the AD conversion output exists in either the H logic or the L logic irrespective of the logic of the expected value is determined as good, and the case where the AD conversion output exists between the H logic and the L logic is determined as bad. An AD converter test apparatus, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04326903A JP3090240B2 (en) | 1992-12-07 | 1992-12-07 | AD converter test equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04326903A JP3090240B2 (en) | 1992-12-07 | 1992-12-07 | AD converter test equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06177758A JPH06177758A (en) | 1994-06-24 |
| JP3090240B2 true JP3090240B2 (en) | 2000-09-18 |
Family
ID=18193040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04326903A Expired - Lifetime JP3090240B2 (en) | 1992-12-07 | 1992-12-07 | AD converter test equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3090240B2 (en) |
-
1992
- 1992-12-07 JP JP04326903A patent/JP3090240B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06177758A (en) | 1994-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6789224B2 (en) | Method and apparatus for testing semiconductor devices | |
| US7688658B2 (en) | Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof | |
| KR20000034827A (en) | semiconductor memory test method and apparatus thereof | |
| JPH10188597A (en) | Memory tester | |
| JP3090240B2 (en) | AD converter test equipment | |
| JPH10106292A (en) | Memory tester | |
| JPH06201801A (en) | Improved data analyzer and analyzing method used for bist circuit | |
| US6105156A (en) | LSI tester for use in LSI fault analysis | |
| JPH06119799A (en) | Device for testing memory | |
| JPH063413A (en) | Method and device for inspecting logic signal | |
| JP3455402B2 (en) | Semiconductor memory test equipment | |
| KR100253707B1 (en) | Apparatus and method for testing semiconductor device | |
| KR102670596B1 (en) | Method for configuring address of buffer memory for semiconductor test, and semiconductor test apparatus implementing the same method | |
| JP3472972B2 (en) | IC test equipment | |
| JP3532617B2 (en) | IC test equipment | |
| JP3223924B2 (en) | Logic comparator for IC test equipment | |
| JP2578076Y2 (en) | Defect data acquisition device for IC test equipment | |
| JP3185187B2 (en) | IC test equipment | |
| JPH05281292A (en) | Ic tester using ad circuit | |
| JPS6039186B2 (en) | semiconductor element | |
| JPH1186593A (en) | Integrated circuit test device | |
| JP2000285698A (en) | Memory testing deivce | |
| JP2002168918A (en) | History information recorder for device for testing semiconductor | |
| JPS63233384A (en) | Logical check of printed circuit board unit | |
| JPH0926460A (en) | Semiconductor testing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20000613 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080721 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080721 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090721 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090721 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100721 Year of fee payment: 10 |