JP3036917B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP3036917B2 JP3036917B2 JP3257376A JP25737691A JP3036917B2 JP 3036917 B2 JP3036917 B2 JP 3036917B2 JP 3257376 A JP3257376 A JP 3257376A JP 25737691 A JP25737691 A JP 25737691A JP 3036917 B2 JP3036917 B2 JP 3036917B2
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- power supply
- signal
- supply potential
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Control Of Voltage And Current In General (AREA)
- Dc-Dc Converters (AREA)
- Dram (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特にＶｃｃ／２回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a Vcc / 2 circuit.
【０００２】[0002]
【従来の技術】図３に、従来のＶｃｃ／２回路の一例を
示す。2. Description of the Related Art FIG. 3 shows an example of a conventional Vcc / 2 circuit.
【０００３】図３において、電源電位と接地電位との間
に２つの抵抗Ｒ５，Ｒ６を直列に接続したもので、抵抗
Ｒ５，Ｒ６の接続点より、出力信号３が出力される。In FIG. 3, two resistors R5 and R6 are connected in series between a power supply potential and a ground potential, and an output signal 3 is output from a connection point between the resistors R5 and R6.
【０００４】通常動作時、Ｖｃｃ／２回路の出力信号３
は、抵抗Ｒ５，Ｒ６の抵抗比で出力レベルが決定され
る。また、消費電流を低減させるために、抵抗Ｒ５，Ｒ
６の抵抗値は大きい方が望ましい。During normal operation, the output signal 3 of the Vcc / 2 circuit
Is determined by the resistance ratio of the resistors R5 and R6. In order to reduce current consumption, resistors R5, R5
It is desirable that the resistance value of No. 6 is large.
【０００５】データリテンション動作時に、電源電位が
変動し、低電源電位になった場合に、出力信号３も変動
するが、抵抗Ｒ５，Ｒ６の抵抗値が大きい為、電源電位
の変動に対して出力信号３は追従しなくなり、安定した
電位になるまで長い時間を必要とする。When the power supply potential fluctuates during the data retention operation and the power supply potential becomes low, the output signal 3 also fluctuates. The signal 3 does not follow, and requires a long time to reach a stable potential.
【０００６】[0006]
【発明が解決しようとする課題】前述した従来のＶｃｃ
／２回路では、出力信号３が電源電位の変動に対して追
従するのに、長い時間を必要とする欠点があった。The above-mentioned conventional Vcc
The / 2 circuit has a disadvantage that it takes a long time for the output signal 3 to follow the fluctuation of the power supply potential.
【０００７】そこで、本発明の目的は、前記欠点を解決
し、電源電位の変動に対して短い時間で追従する半導体
集積回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit which solves the above-mentioned drawbacks and follows a change in power supply potential in a short time.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体集積回路
の構成は、電源電位と接地電位との間に２つの抵抗値の
大きい抵抗を直列接続し、前記抵抗の間に２つのトラン
ジスタを直列接続し、前記２つのトランジスタのゲート
電極に通常動作時にはハイレベルになる信号を与える手
段を設け、前記２つのトランジスタの共通接続点より出
力信号を得、前記電源電位と前記接地電位との間に２つ
の抵抗値の小さい抵抗を直列接続し、この抵抗の間に２
つのトランジスタを直列接続し、この２つのトランジス
タのゲート電極に前記電源電位の変動時にハイレベルと
なる信号を与える手段と、このトランジスタの接続点よ
り出力信号を得るように構成したことを特徴とする。According to the structure of the semiconductor integrated circuit of the present invention, two resistors having a large resistance value are connected in series between a power supply potential and a ground potential, and two transistors are connected in series between the resistors. Means for providing a signal which becomes high level during normal operation to a gate electrode of the two transistors, obtains an output signal from a common connection point of the two transistors, and provides a signal between the power supply potential and the ground potential. Two low resistance resistors are connected in series, and 2
Means for connecting two transistors in series, providing a signal that goes to a high level when the power supply potential fluctuates to the gate electrodes of the two transistors, and obtaining an output signal from a connection point of the transistors. .
【０００９】[0009]
【実施例】図１は本発明の一実施例の半導体集積回路を
示す回路図である。FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to one embodiment of the present invention.
【００１０】図２は図１の動作を示す波形図である。図
２において、図１の信号φ１，φ２，φ３，φ４の各波
形が示され、さらに出力信号１，２の各波形が示されて
おり、ノーマル期間，データ・リテンション期間，セル
フ・リフレッシュ期間，さらにノーマル期間に分けられ
る。FIG. 2 is a waveform chart showing the operation of FIG. FIG. 2 shows the waveforms of the signals φ1, φ2, φ3, and φ4 in FIG. 1, and further shows the waveforms of the output signals 1 and 2, respectively, including a normal period, a data retention period, a self-refresh period, It is further divided into normal periods.
【００１１】図１において、本発明の一実施例のＶｃｃ
／２回路は、ブロック１０では、電源電位と接地電位と
の間に２つの抵抗値の大きい抵抗Ｒ１，Ｒ２を直列接続
し、さらに抵抗Ｒ１，Ｒ２の間に２つのトランジスタＱ
１，Ｑ２を直列接続し、トランジスタＱ１，Ｑ２の夫々
のゲート電極に通常動作時にはハイレベルになる信号φ
３を入力し、出力信号１を発生させる回路と、またブロ
ック２０では、電源電位と接地電位との間に２つの抵抗
値の小さい抵抗Ｒ３，Ｒ４を直列接続し、さらに抵抗Ｒ
３，Ｒ４の間に２つのトランジスタＱ３，Ｑ４を直列接
続し、トランジスタＱ３，Ｑ４の夫々のゲート電極に電
源電位の変動時のみハイレベルになる信号φ４を入力
し、出力信号２を発生させる回路とを含む構成となって
いる。In FIG. 1, Vcc of one embodiment of the present invention is shown.
In the block 10, the two resistors R1 and R2 having a large resistance value are connected in series between the power supply potential and the ground potential in the block 10, and two transistors Q are connected between the resistors R1 and R2.
1 and Q2 are connected in series, and a signal φ which becomes a high level during normal operation is applied to each gate electrode of the transistors Q1 and Q2.
3 and a circuit for generating an output signal 1, and in the block 20, two resistors R3 and R4 having a small resistance value are connected in series between a power supply potential and a ground potential, and a resistor R
3, a circuit in which two transistors Q3 and Q4 are connected in series between R3 and R4, and a signal φ4 that goes high only when the power supply potential fluctuates is input to each gate electrode of the transistors Q3 and Q4 to generate an output signal 2. And a configuration including:
【００１２】次に、本実施例の動作を図２の動作波形図
を参照して説明する。Next, the operation of this embodiment will be described with reference to the operation waveform diagram of FIG.
【００１３】図１，図２において、まず、メモリリフレ
ッシュ信号φ１がハイ又はロウ，データリテンション信
号φ２がハイの通常動作時は、信号φ３がハイレベルと
なり、トランジスタＱ１，Ｑ２がＯＮし、出力信号１が
出力されるが、抵抗Ｒ１，Ｒ２の抵抗値が大きい為、消
費電流は少なくすることができる。In FIG. 1 and FIG. 2, during a normal operation in which the memory refresh signal φ1 is high or low and the data retention signal φ2 is high, the signal φ3 goes high, the transistors Q1 and Q2 turn on, and the output signal Although 1 is output, the current consumption can be reduced because the resistance values of the resistors R1 and R2 are large.
【００１４】また、通常動作時からデータリテンション
動作時に電源電位が変動した場合に信号φ２に同期して
時間ｔの間信号φ３がロウレベルになり、トランジスタ
Ｑ１，Ｑ２がＯＦＦし、出力信号（ＶＲ１）のリセット
を行ない、同時に時間ｔの間、信号φ４がハイレベルに
なり、トランジスタＱ３，Ｑ４がＯＮし、出力信号（Ｖ
Ｒ２）が出力され、さらに抵抗Ｒ３，Ｒ４の抵抗値が小
さい為、電源電位の変動に対して、Ｖｃｃ／２回路の出
力（ＶＲ２）が短い時間で追従する。When the power supply potential fluctuates during the data retention operation from the normal operation, the signal φ3 goes low for a time t in synchronization with the signal φ2, the transistors Q1 and Q2 are turned off, and the output signal (VR1) At the same time, the signal φ4 goes high for the time t, the transistors Q3 and Q4 are turned on, and the output signal (V
R2) is output and the resistances of the resistors R3 and R4 are small, so that the output (VR2) of the Vcc / 2 circuit follows the fluctuation of the power supply potential in a short time.
【００１５】[0015]
【発明の効果】以上説明したように、本発明は、電源電
位の変動時のみ特にトランジスタＱ３，Ｑ４に信号φ４
を入力し、且つ抵抗値の小さい抵抗Ｒ３，Ｒ４にするこ
とで、電源電位の変動に短い時間で追従できるという効
果がある。As described above, according to the present invention, the signal φ4 is applied to the transistors Q3 and Q4 only when the power supply potential fluctuates.
Is input and the resistors R3 and R4 having small resistance values have an effect that the fluctuation of the power supply potential can be followed in a short time.
【図１】本発明の一実施例の半導体集積回路を示す回路
図である。FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to one embodiment of the present invention.
【図２】図１の各部の動作を示す波形図である。FIG. 2 is a waveform chart showing the operation of each unit in FIG.
【図３】従来のＶｃｃ／２回路を示す回路図である。FIG. 3 is a circuit diagram showing a conventional Vcc / 2 circuit.
１ 通常動作時の出力信号 ２ 電源電位の変動時の出力信号 ３ 従来の出力信号 Ｑ１〜Ｑ４ ＮチャネルＭＯＳトランジスタ Ｒ１，Ｒ２，Ｒ５，Ｒ６ 抵抗値の大きい抵抗 Ｒ３，Ｒ４ 抵抗値の小さい抵抗 φ１ メモリリフレッシュの外部信号 φ２ 外部のデータリテンション信号 φ３，φ４ 外部信号に同期する信号 ＶＤＲ データリテーション時の電源電圧 １０，２０ ブロック REFERENCE SIGNS LIST 1 Output signal during normal operation 2 Output signal when power supply potential fluctuates 3 Conventional output signal Q1-Q4 N-channel MOS transistors R1, R2, R5, R6 Resistors with large resistance R3, R4 Resistors with small resistance φ1 Memory External refresh signal φ2 External data retention signal φ3, φ4 Signal synchronized with external signal VDR Power supply voltage during data retention 10, 20 blocks
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) G05F 1/10 301 G11C 11/407 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 7 , DB name) G05F 1/10 301 G11C 11/407
Claims (2)
値の大きい抵抗を直列接続し、前記抵抗の間に２つのト
ランジスタを直列接続し、前記２つのトランジスタのゲ
ート電極に通常動作時にはハイレベルになる信号を与え
る手段を設け、前記２つのトランジスタの共通接続点よ
り出力信号を得、前記電源電位と前記接地電位との間に
２つの抵抗値の小さい抵抗を直列接続し、この抵抗の間
に２つのトランジスタを直列接続し、この２つのトラン
ジスタのゲート電極に前記電源電位の変動時にハイレベ
ルとなる信号を与える手段と、このトランジスタの接続
点より出力信号を得るように構成したことを特徴とする
半導体集積回路。1. A high-resistance two resistor is connected in series between a power supply potential and a ground potential, two transistors are connected in series between the resistors, and a gate electrode of the two transistors is connected to a gate electrode during normal operation. Means for giving a high level signal is provided, an output signal is obtained from a common connection point of the two transistors, and two resistors having small resistance values are connected in series between the power supply potential and the ground potential; Means for providing a signal which becomes a high level when the power supply potential fluctuates to a gate electrode of the two transistors, and an output signal obtained from a connection point of the transistors. A semiconductor integrated circuit characterized by the above-mentioned.
界効果トランジスタである請求項１記載の半導体集積回
路。2. The semiconductor integrated circuit according to claim 1, wherein the transistors are all N-channel field effect transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3257376A JP3036917B2 (en) | 1991-10-04 | 1991-10-04 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3257376A JP3036917B2 (en) | 1991-10-04 | 1991-10-04 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05103460A JPH05103460A (en) | 1993-04-23 |
| JP3036917B2 true JP3036917B2 (en) | 2000-04-24 |
Family
ID=17305531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3257376A Expired - Lifetime JP3036917B2 (en) | 1991-10-04 | 1991-10-04 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3036917B2 (en) |
-
1991
- 1991-10-04 JP JP3257376A patent/JP3036917B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05103460A (en) | 1993-04-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20000201 |