JP3029305B2 - Neutral point clamp type power converter controller - Google Patents
Neutral point clamp type power converter controllerInfo
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- JP3029305B2 JP3029305B2 JP03033911A JP3391191A JP3029305B2 JP 3029305 B2 JP3029305 B2 JP 3029305B2 JP 03033911 A JP03033911 A JP 03033911A JP 3391191 A JP3391191 A JP 3391191A JP 3029305 B2 JP3029305 B2 JP 3029305B2
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- signal
- gate
- time
- self
- neutral point
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- Power Conversion In General (AREA)
- Inverter Devices (AREA)
Description
[発明の目的] [Object of the invention]
【0001】[0001]
【産業上の利用分野】本発明は、交流電力を直流電力に
変換するパルス幅変調制御(PWM制御)コンバ―タ
や、直流電力を交流電力に変換するPWM制御インバ―
タ等に適用される3レベルの出力電圧を発生する中性点
クランプ式電力変換器の制御装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation control (PWM control) converter for converting AC power to DC power, and a PWM control inverter for converting DC power to AC power.
The present invention relates to a neutral-point-clamp-type power converter control device that generates a three-level output voltage applied to a power converter or the like.
【0002】[0002]
【従来の技術】図4は、中性点クランプ式インバ―タの
主回路構成図を示す。図は1相分(U相分)を示し、3
相出力インバ―タの場合、V,W相も同様に構成され
る。2. Description of the Related Art FIG. 4 shows a main circuit configuration diagram of a neutral point clamp type inverter. The figure shows one phase (U phase) and 3
In the case of a phase output inverter, the V and W phases are similarly configured.
【0003】図中、Vd1,Vd2は直流電源、S1 〜S4
は自己消弧素子、D1 〜D4 はフリ―ホイリングダイオ
―ド、D5 ,D6 はクランプ用ダイオ―ド、LOADば
負荷である。In the figure, V d1 and V d2 are DC power supplies, S 1 to S 4
The self-turn-off device, D 1 to D 4 is flip - wheeling diode - de, D 5, D 6 are clamping diodes - a de, LOAD if load.
【0004】このインバ―タの出力電圧VU は、4つの
素子S1〜S4 をオン、オフさせることによって、次の
ように変化する。ただし、全体の直流電圧をVd とし、
Vd1=Vd2=Vd /2とする。即ち、 S1 とS2 がオンのとき、VU =+Vd /2 S2 とS3 がオンのとき、VU =0 S3 とS4 がオンのとき、VU =−Vd /2 となる。この時、素子は2個ずつオンさせなければなら
ない。3個同時にオンになると、直流電源を短絡し、過
電流によって素子を破壊してしまう。The output voltage V U of this inverter changes as follows by turning on and off the four elements S 1 to S 4 . However, let the total DC voltage be Vd,
It is assumed that V d1 = V d2 = V d / 2. That is, when S 1 and S 2 are on, V U = + V d / 2 When S 2 and S 3 are on, V U = 0 When S 3 and S 4 are on, V U = −V d / It becomes 2. At this time, the elements must be turned on two by two. If all three are turned on at the same time, the DC power supply is short-circuited, and the element is destroyed by an overcurrent.
【0005】例えば、素子S1 〜S3 にオン信号が入る
と、直流電圧Vd1を素子S1 ―S2―S3 ―ダイオ―ド
D6 で短絡し、過大な短絡電流が素子に流れ、素子を壊
してしまう。For example, when an ON signal is input to the elements S 1 to S 3 , the DC voltage V d1 is short-circuited by the element S 1 -S 2 -S 3 -diode D 6 and an excessive short-circuit current flows through the elements. Will break the element.
【0006】このような直流短絡を防止するため、素子
S1 とS3 を逆動作させ、素子S2S4 を逆動作させて
いる。即ち、素子S1 がオンのときは素子S3 をオフさ
せ、素子S3 がオンのときは素子S1 をオフさせてい
る。同様に、素子S2 がオンのときは素子S4 をオフさ
せ、素子S4 がオンのときは、素子S2 をオフさせてい
る。図5は、中性点クランプ式インバ―タの従来のパル
ス幅変調制御法を説明するためのタイムチャ―ト図であ
る。In order to prevent such a DC short circuit, the elements S 1 and S 3 are operated in reverse, and the elements S 2 and S 4 are operated in reverse. That is, the element S 1 is turned off element S 3 when on, when element S 3 is turned on and turns off the device S 1. Similarly, when element S 2 is turned on to turn off the element S 4, element S 4 is on, and turns off the element S 2. FIG. 5 is a time chart for explaining a conventional pulse width modulation control method of the neutral point clamp type inverter.
【0007】図中、X,YはPWM制御の搬送波信号
で、Xは+EMAX 〜0の間を変化する三角波、Yは−E
MAX 〜0の間を変化する三角波である。また、ei はP
WM制御入力信号である。入力信号ei と三角波X,Y
とを比較し、素子S1 〜S4 のゲ―ト信号g1 ,g2 を
作る。即ち、 ei >Xのとき、g1 =1で、S1 はオン、S3 はオフ ei ≦Xのとき、g1 =0で、S1 はオフ、S3 はオン ei ≧Yのとき、g2 =0で、S4 はオフ、S2 はオン ei <Yのとき、g2 =1で、S4 はオン、S2 はオフ とする。In the drawing, X and Y are carrier signals of PWM control, X is a triangular wave varying between + E MAX and 0, and Y is -E.
This is a triangular wave that changes between MAX and 0. E i is P
This is a WM control input signal. Input signal e i and triangular wave X, Y
To generate gate signals g 1 and g 2 for the elements S 1 to S 4 . That is, when e i > X, g 1 = 1, S 1 is on, and S 3 is off. When e i ≦ X, g 1 = 0, S 1 is off, and S 3 is on e i ≧ Y In this case, g 2 = 0, S 4 is off, and S 2 is on. When e i <Y, g 2 = 1, S 4 is on, and S 2 is off.
【0008】この結果、出力電圧VU は、図の最下段の
ようになり、その平均値(破線で示す)は入力信号ei
に比例した値となる。このように、中性点クランプ式イ
ンバ―タでは、出力電圧VU として、3レベル(+Vd
/2,0,−Vd /2)の電圧が得られ、高調波成分の
少ない電圧波形となる。電動機負荷の場合は、電流の脈
動は小さくなり、トルクリップルも低減できる利点があ
る。As a result, the output voltage V U becomes as shown at the bottom of the figure, and the average value (shown by a broken line) is the input signal e i.
It becomes a value proportional to. Thus, the neutral point clamped inverter - the motor, as the output voltage V U, 3 levels (+ V d
/ 2, 0, −V d / 2), and a voltage waveform with less harmonic components is obtained. In the case of a motor load, there is an advantage that the pulsation of the current is reduced and the torque ripple can be reduced.
【0009】[0009]
【発明が解決しようとする課題】しかし、従来の中性点
クランプ式インバ―タの制御装置には、次のような問題
点がある。図6は、図5と同様に従来のPWM制御方法
を説明するためのタイムチャ―ト図を示すもので、入力
信号ei が急激に変化した場合の動作を表す。However, the conventional control device of the neutral point clamp type inverter has the following problems. FIG. 6 is a time chart for explaining the conventional PWM control method similarly to FIG. 5, and shows an operation when the input signal e i changes abruptly.
【0010】ei がa点で、正から負に急変すると、ゲ
―ト信号g1 は「1」から「0」に、ゲ―ト信号g2 は
「0」から「1」に変化する。このゲ―ト信号に従っ
て、素子S1 〜S4 が瞬時にオン、オフできれば、出力
電圧VU は図示のようになり、何の問題も発生しない。[0010] e i is at a point when sudden change from positive to negative, gate - DOO signal g 1 from "1" to "0", gate - DOO signal g 2 is changed from "0" to "1" . The gate - in accordance DOO signal, on the element S 1 to S 4 is instantly, if off, the output voltage V U is as shown, does not occur any problem.
【0011】しかし、大容量のインバ―タでは、自己消
弧素子としてGTO(ゲ―トタ―ンオフサイリスタ)な
どが使われ、タ―ンオフ時の過電圧を抑制するためスナ
バ回路が設置される。However, in a large-capacity inverter, a GTO (gate turn-off thyristor) or the like is used as a self-turn-off device, and a snubber circuit is provided to suppress an overvoltage at the time of turn-off.
【0012】このスナバ回路のコンデンサの電圧を初期
化する(放電させる)ため、GTOをオンさせた時、一
定時間(最小オン時間:例えば100マイクロ秒程度)
オン状態を維持しなければならない。When the GTO is turned on in order to initialize (discharge) the voltage of the capacitor of this snubber circuit, a certain time (minimum on-time: for example, about 100 microseconds)
It must be kept on.
【0013】図7は、図6のa点付近のゲ―ト信号の動
作を拡大したものでゲ―ト信号g1=1の幅が最小オン
時間ΔtONより狭くなった場合を示す。素子S1 の最小
オン時間ΔtON は素子自体を保護するために不可欠のも
のであり、最終的な素子へのゲートパルスを作る回路に
設けられ、素子には最小オン時間Δt ON が確保されたゲ
ート信号g 1 ´が与えられる。この結果、g1 ´とg2
とが期間δだけ重なり、素子S1 がオン、S2 がオフ、
S3 がオフ、S4 がオンとなる。FIG. 7 is an enlarged view of the operation of the gate signal near point a in FIG. 6 and shows a case where the width of the gate signal g 1 = 1 becomes smaller than the minimum on-time Δt ON . Even the minimum on-time Delta] t ON of the element S 1 is the essential to protect the element itself
In the circuit that creates the gate pulse to the final device
The device has a gate with a minimum on-time Δt ON secured.
A gate signal g 1 ′ is provided . As a result, g 1 ′ and g 2
Overlap for a period δ, the element S 1 is turned on, S 2 is turned off,
S 3 is turned off, S 4 is turned on.
【0014】図4の主回路において、出力電流IU が図
の矢印の向に流れている場合、ダイオ―ドD3 ,D4 が
導通し、かつ素子S1 にオン信号が来ているので、素子
S2に直流全電圧Vd =Vd1+Vd2が印加される。逆
に、出力電流IU が図の矢印と反対方向にながれている
場合は、ダイオ―ドD1 ,D2 が導通し、S4 にオン信
号が入っているので、素子S3 に全電圧Vd が印加され
る。中性点クランプ式インバ―タでは、各素子(各ア―
ム)の耐圧は直流電圧Vd の半分が印加されるものとし
て設計されており、全電圧が印加された場合、過電圧に
より素子破壊に至ってしまう。In the main circuit shown in FIG. 4, when the output current I U flows in the direction of the arrow in the figure, the diodes D 3 and D 4 conduct, and the ON signal comes to the element S 1 . , A total DC voltage V d = V d1 + V d2 is applied to the element S 2 . Conversely, when the output current I U is flowing in the direction opposite to the arrow in the figure, diode - de D 1, D 2 conducts, because it contains the ON signals to S 4, the total voltage to the device S 3 Vd is applied. In the neutral point clamp type inverter, each element (each
Breakdown voltage of the beam) is designed as a half of the DC voltage V d is applied, if the total voltage is applied, thus leading to device destruction by overvoltage.
【0015】このように従来の中性点クランプ式インバ
―タのPWM制御装置では、入力信号ei が急変した場
合、素子S2 或いはS3 のいずれかに直流全電圧が印加
される危険があり、最悪の場合、素子破壊に至り、装置
の運転を停止せざるを得なくなる。As described above, in the conventional PWM controller of the neutral point clamp type inverter, when the input signal e i changes suddenly, there is a danger that the full DC voltage is applied to either the element S 2 or S 3. In the worst case, the device is destroyed, and the operation of the apparatus must be stopped.
【0016】本発明は、以上の問題点に鑑みてなされた
もので、PWM制御の入力信号eiが急激に変化しても
1つの素子に直流全電圧が印加されることのないような
中性点クランプ式電力変換器の制御装置を提供すること
を目的とする。 [発明の構成][0016] The present invention has been made in view of the above problems, in such as not to input signal e i is a DC full voltage to one element is also changing rapidly in the PWM control is applied An object of the present invention is to provide a control device for a power clamped power converter. [Configuration of the Invention]
【0017】[0017]
【課題を解決するための手段】前記目的を達成するため
に本発明は、直流端子間に接続され中性点出力端子を備
えた直流電源と、前記直流端子間に同一極性で直列接続
された4個の自己消弧素子S1 ,S2 ,S3 ,S4 と、
これらの各素子にそれぞれ逆並列接続されるフリ―ホイ
リングダイオ―ドD1 ,D2 ,D3 ,D4 と、直列接続
されている前記2個の自己消弧素子S2 ,S3 に逆並列
接続されるクランプ用ダイオ―ドD5 ,D6 の直列回路
と、前記自己消弧素子S1 とS3 及びS2 とS4 とが逆
動作するように最小オン・オフ時間が確保されたゲート
信号でオンオフ制御するゲート制御手段を備え、前記ク
ランプ用ダイオ―ドD5 ,D6 の直列接続点と前記中性
点出力端子とを接続し、前記4個の自己消弧素子S1 ,
S2 ,S3 ,S4 の直列回路の中間接続点に交流端子を
設けた中性点クランプ式電力変換器において、パルス幅
変調制御用搬送波として、1つは零と+Emax 間で変化
する三角波X、もう1つは該三角波Xと周波数と位相が
一致し零と−Emax 間で変化する三角波Yを発生する手
段と、−Emax ≦ei ≦+Emax を満すPWM制御入力
信号ei を発生する手段と、この2つの三角波X,Yと
PWM制御入力信号ei とを比較し、 ei >Xのとき、g1 =1 ei ≦Xのとき、g1 =0 ei ≧Yのとき、g2 =0 ei <Yのとき、g2 =1 となる第1及び第2のゲ―ト信号g1 ,g2 を作る手段
と、前記第1のゲ―ト信号g1 が「1」から「0」に変
化するとき素子の最少オン時間ΔtONより長い一定時間
Δtだけ「0」状態を保持した信号を発生する手段と、
該手段の信号に基づいて前記第2のゲ―ト信号g2 を前
記時間Δtだけ「0」の状態に固定させた新たなゲ―ト
信号g22を作る手段と、前記第2のゲ―ト信号g2 が
「1」から「0」に変化するとき素子の最少オン時間Δ
tONより長い一定時間Δtだけ「0」状態を保持した信
号を発生する手段と、該手段の信号に基づいて前記第1
のゲ―ト信号g1 を前記時間Δtだけ「0」の状態に固
定させた新たなゲ―ト信号g11を作る手段を設け、前記
新たなゲ―ト信号g 11 及びg 22 を前記ゲート制御手段を
介して最小オン・オフ時間を確保して前記4個の自己消
弧素子S 1 ,S 2 ,S 3 ,S 4 に与え前記新たなゲ―ト
信号g 11 で前記自己消弧素子S 1 とS 3 が、前記新たな
ゲ―ト信号g 22 で前記自己消弧素子S 2 とS 4 とが逆動
作するようパルス幅変調制御する。According to the present invention, there is provided a DC power supply having a neutral point output terminal connected between DC terminals, and a DC power supply having the same polarity connected in series between the DC terminals. Four self-extinguishing elements S 1 , S 2 , S 3 , S 4 ,
The free-wheeling diodes D 1 , D 2 , D 3 , D 4 connected in anti-parallel to these elements, respectively, and the two self-turn-off elements S 2 , S 3 connected in series. The minimum on / off time is ensured so that the series circuit of the clamping diodes D 5 and D 6 connected in anti-parallel and the self-turn-off devices S 1 and S 3 and S 2 and S 4 operate in reverse. Gate control means for controlling the on / off state by the applied gate signal, connecting the series connection point of the clamping diodes D 5 and D 6 to the neutral point output terminal, and connecting the four self-extinguishing elements S 1 ,
In a neutral point clamp type power converter provided with an AC terminal at an intermediate connection point of the series circuit of S 2 , S 3 , and S 4 , one is a triangular wave varying between zero and + Emax as a carrier for pulse width modulation control. X, and one means for generating a triangular wave Y of the triangular wave X and the frequency and phase changes between matched zero and -Emax, the -Emax ≦ e i ≦ + Emax the full to PWM control input signal e i generated And the two triangular waves X and Y are compared with the PWM control input signal e i . When e i > X, g 1 = 1 e i ≦ X, and g 1 = 0 e i ≧ Y When g 2 = 0 e i <Y, means for producing first and second gate signals g 1 and g 2 satisfying g 2 = 1, and the first gate signal g 1 is generating a signal held long predetermined time Delta] t to "0" state from the minimum on-time Delta] t oN of the device when changing from "1" to "0" And the stage,
Said means signal Based on the second gate of the - DOO signal g 2 only the time Δt "0" new gate was fixed in a state of - means for making bets signals g 22, the second gate - minimum on-time of the device when the Doo signal g 2 is changed from "1" to "0" Δ
means for generating a signal that maintains a "0" state for a fixed time Δt longer than t ON;
The gate - DOO signal g 1 only the time Δt "0" state to a new gate was fixed - a means to make bets signals g 11, wherein
New gate - the door signal g 11 and g 22 of the gate control means
The minimum on / off time is ensured through
The new gate given to the arc elements S 1 , S 2 , S 3 , S 4
Signal the self-turn-off devices in g 11 S 1 and S 3 is the new
Gate - said in preparative signal g 22 self-turn-off device S 2 and S 4 and the reversing
Pulse-width modulation control to work.
【0018】[0018]
【作用】前述のように構成することにより、PWM制御
の入力信号ei が急変し、ゲ―ト信号g1 が「1」から
「0」に、g2 が「0」から「1」に、それぞれ変化し
た場合、当該信号g1 の立下がり、(1から0)から一
定時間Δtだけg22=0とし、その後、g22=g2 とな
るような新たなゲ―ト信号g22を作り、素子S2及びS
4 をオン、オフさせる。By constructing as [action] described above, to change suddenly the input signal e i of the PWM control, gate - to "0" DOO signal g 1 from "1", "1" g 2 from "0" , when each change, falls of the signals g 1, by a predetermined time Δt from (1 0) and g 22 = 0, then, g 22 = g 2 become such a new gate - the door signal g 22 Make the elements S 2 and S
Turn 4 on and off.
【0019】又、ゲ―ト信号g2 が「1」から「0」に
ゲ―ト信号g1 が「0」から「1」にそれぞれ変化した
場合、当該信号g2 立下がり(1から0)から一定時間
Δtだけg11=0とし、その後、g11=g1 となるよう
な新たなゲ―ト信号g11を作り、素子S1 ,S3 をオ
ン、オフさせる。前記時間Δtは素子の最小オン時間な
どを考慮して定める。[0019] Further, gate - DOO signal gate g 2 from "1" to "0" - If DOO signal g 1 is changed respectively to "1" from "0", 0 from the signal g 2 Fall (1 ), G 11 = 0 for a fixed time Δt, and then a new gate signal g 11 that satisfies g 11 = g 1 is generated to turn on and off the elements S 1 and S 3 . The time Δt is determined in consideration of the minimum on-time of the element and the like.
【0020】この結果、新たなゲ―ト信号は、g11=1
からg22=1に移るとき、及びg22=1からg11=1に
移る時、その間に必ずg11=0、g22=0のモ―ドを介
在するようになる。言い代えると、素子S1 とS2 がオ
ンの状態から、素子S3 とS4 がオンになる状態に直接
移ることはなくなり、必ず素子S2 とS3 がオン(S1
とS4 はオフ)になるモ―ドを介してゲ―ト信号が与え
られる。従って、素子の最小オン時間などによりパルス
幅が広げられてゲ―ト信号が与えられても、S1 がオン
で、S2 がオフとなるモ―ド(或いはS4 がオンで、S
3 がオフとなるモ―ド)はなくなり、素子S2 或いはS
3 に直流全電圧Vd が印加されることはなくなり、従来
の問題点を解決することができる。As a result, the new gate signal is g 11 = 1
When g <b> 22 = 1 and g <b> 22 = 1 to g <b> 11 = 1, a mode of g 11 = 0 and g 22 = 0 always intervenes between them. In other words, the state where the elements S 1 and S 2 are on is not directly shifted to the state where the elements S 3 and S 4 are on, and the elements S 2 and S 3 are always on (S 1
And S 4 are motor turned off) - DOO signal is given - gate through the de. Thus, the pulse width is widened due minimum on time of the device gate - even given a preparative signals, S 1 is turned on, S 2 is off mode - de (or S 4 is on, S
3 is turned off), and the element S 2 or S
3 DC full voltage V d is not being applied, it is possible to solve the conventional problems.
【0021】[0021]
【実施例】図1は、本発明の中性点クランプ式インバ―
タの制御装置を説明するための主回路構成図および制御
装置のブロック図の一実施例を示す。FIG. 1 shows a neutral point clamp type inverter according to the present invention.
FIG. 1 shows an embodiment of a main circuit configuration diagram for explaining a control device of a controller and a block diagram of the control device.
【0022】図中、Vd1,Vd2は直流電源、S1 ,
S2 ,S3 ,S4 は自己消弧素子、D1D2 ,D3 ,D
4 はフリ―ホイリングダイオ―ド、D5 ,D6 はクラン
プ用ダイオ―ド、LOADは負荷、CTU は電流検出器
である。又、制御回路として、比較器CU ,C1 ,
C2 、電流制御補償回路GU (s) 、三角波発生器TR
G、シュミット回路SH1 ,SH2 、モノマルチ回路M
M1 ,MM2 、論理積回路AND1 ,AND2 が設けら
れている。この図は1相分(U相分)のみを示している
が、3相負荷の場合、他の2相(V相,W相)も同様に
構成される。In the figure, V d1 and V d2 are DC power supplies, S 1 and
S 2 , S 3 , S 4 are self-extinguishing elements, D 1 D 2 , D 3 , D
4 flip - wheeling diode - de, D 5, D 6 are clamping diodes - de, LOAD is the load, CT U is a current detector. In addition, comparators C U , C 1 ,
C 2 , current control compensation circuit G U (s), triangular wave generator TR
G, Schmitt circuits SH 1 , SH 2 , mono-multi circuit M
M 1 , MM 2 and AND circuits AND 1 , AND 2 are provided. This figure shows only one phase (U phase), but in the case of a three-phase load, the other two phases (V phase, W phase) are similarly configured.
【0023】U相の負荷電流IU を電流検出器CTU に
より検出し、電流制御回路の比較器CU に入力する。比
較器CU は電流指令値IU * と電流検出値IU とを比較
し、偏差εU =IU * −IU を求める。当該偏差εU を
次の制御補償回路GU (s) で増幅し、PWM制御の入力
信号ei とする。[0023] The load current I U of the U-phase detected by the current detector CT U, is input to a comparator C U of the current control circuit. The comparator C U has a current command value I U * And the detected current value I U, and the deviation ε U = I U * Seek -I U. The deviation εU is amplified by the next control compensation circuit G U (s) and used as an input signal e i for PWM control.
【0024】三角波発生器TRGは2つの三角波X,Y
を発生し、比較器C1 ,C2 に入力する。比較器C1 は
三角波Xと前記入力信号ei を比較しシュミット回路S
H1を介して第1のゲ―ト信号g1 (以下単にゲ―ト信
号g 1 と記す)を作る。又、比較器C2 は三角波Yと前
記入力信号ei を比較し、シュミット回路SH2 を介し
て第2のゲ―ト信号g2 (以下単にゲ―ト信号g 2 と記
す)を作る。The triangular wave generator TRG has two triangular waves X and Y.
Is generated and input to the comparators C 1 and C 2 . The comparator C 1 compares the triangular wave X with the input signal e i and determines the Schmitt circuit S
The first gate via the H 1 - DOO signal g 1 (hereinafter simply gate - DOO Shin
Make the No. g 1 hereinafter). Further, the comparator C 2 compares the input signal e i a triangular wave Y, the second through the Schmitt circuit SH 2 gate - DOO signal g 2 (hereinafter simply gate - and preparative signal g 2 serial
Make ) .
【0025】ゲ―ト信号g1 の立下がりをトリガとして
モノマルチ回路MM1 を動作させる。モノマルチ回路M
M1 の出力は素子の最小オン時間Δt ON 時間より長い一
定時間Δtの間「0」となる。同様に、ゲ―ト信号g2
の立下がりをトリガとしてモノマルチ回路MM2 を動作
させる。モノマルチ回路MM2 の出力は素子の最小オン
時間Δt ON 時間より長い一定時間Δtの間「0」とな
る。The gate - operating the mono-multi circuit MM 1 falling bets signals g 1 as a trigger. Mono-multi circuit M
The output of the M 1 is longer than the minimum on-time Delta] t ON time-element
It becomes “0” during the fixed time Δt. Similarly, the gate signal g 2
The fall of the trigger operating the mono-multi circuit MM 2. The output of the multivibrator circuit MM 2 is minimum on the element
It becomes “0” for a fixed time Δt longer than the time Δt ON time .
【0026】論理積回路AND1 により、ゲ―ト信号g
1 とモノマルチ回路MM2 の出力信号の論理積をとり、
ゲ―ト信号g 2 が「1」から「0」に変化するとき素子
の最小オン時間Δt ON 時間より長い一定時間Δtだけゲ
―ト信号g 1 を「0」の状態に固定させた新たなゲ―ト
信号g11を作る。即ち、当該ゲ―ト信号g11はモノマル
チ回路MM2 の出力が「0」の間、g11=0となり、他
はg11=g1 となる。[0026] The AND circuit the AND 1, gate - DOO signal g
AND the output signal of 1 and the mono-multi circuit MM 2 and
Element when the gate signal g 2 changes from “1” to “0”
For a fixed time Δt longer than the minimum ON time Δt ON
- a new gate was fixed the door signal g 1 in the state of "0" - make a door signal g 11. That is, the gate - Conclusions signal g 11 output of the multivibrator circuit MM 2 is "0", g 11 = 0, and the other is the g 11 = g 1.
【0027】又、論理積回路AND2 により、ゲ―ト信
号g2 とモノマルチ回路MM1 の出力信号の論理積をと
り、ゲ―ト信号g 1 が「1」から「0」に変化するとき
素子の最小オン時間Δt ON 時間より長い一定時間Δtだ
けゲ―ト信号g 2 を「0」の状態に固定させた新たなゲ
―ト信号g22を作る。即ち、当該ゲ―ト信号g22はモノ
マルチ回路MM1 の出力が「0」の間、g22=0とな
り、他はg22=g2 となる。図2は、本発明の動作を説
明するためのタイムチャ―ト図である。[0027] Furthermore, the AND circuit the AND 2, gate - takes the logical product of the output signal of the preparative signal g 2 and mono-multi circuit MM 1, gate - DOO signal g 1 is changed from "1" to "0" When
It is a fixed time Δt longer than the minimum ON time Δt ON time of the device
Only gate - door signal g 2 new gate was secured to the state of "0" - make a door signal g 22. That is, the gate - Conclusions signal g 22 output of the multivibrator circuit MM 1 is "0", g 22 = 0, and the other is the g 22 = g 2. FIG. 2 is a time chart for explaining the operation of the present invention.
【0028】PWM制御の搬送波Xは0〜+EMAX の間
で変化する一定周波数の三角波である。又、搬送波Yは
0〜−EMAX の間で変化する一定周波数の三角波で、搬
送波Xと同相になっている。PWM制御入力信号ei が
a点でステップ状に変化した場合を考える。PWM制御
入力信号ei と上記三角波X,Yとを比較し、ゲ―ト信
号g1 g2を作る。即ち、 ei >Xのとき、g1 =1 ei ≦Xのとき、g1 =0 ei ≧Yのとき、g2 =0 ei <Yのとき、g2 =1 とする。モノマルチ回路MM1 はゲ―ト信号g1 の立下
がりによって動作し、Δtの時間「0」を出力する。同
様に、モノマルチ回路MM2 はゲ―ト信号g2 の立下が
りによって動作し、Δtの時間「0」を出力する。The carrier X of the PWM control is a triangular wave of a constant frequency varying between 0 to + E MAX. Further, the carrier Y is a triangle wave of a predetermined frequency varying between 0 to-E MAX, which is a carrier wave X in phase. Consider a case where the PWM control input signal e i changes stepwise at point a. The PWM control input signal e i is compared with the triangular waves X and Y to generate a gate signal g 1 g 2 . That is, when e i > X, g 1 = 1 when e i ≦ X, g 1 = 0 e i ≧ Y, g 2 = 0, and when e i <Y, g 2 = 1. Mono-multi circuit MM 1 is gate - operated by the fall of bets signals g 1, and outputs the time "0" of Delta] t. Similarly, the multivibrator circuit MM 2 gate - operated by the fall of bets signals g 2, and outputs the time "0" of Delta] t.
【0029】論理積回路AND1 により、ゲ―ト信号g
1 とモノマルチ回路MM2 の出力信号 m2 との論理積
をとり、新たなゲ―ト信号g11を得る。又、論理積回路
AND2 により、ゲ―ト信号g2 とモノマルチ回路MM
1 の出力信号m1 との論理積をとり、新たなゲ―ト信号
g22を得る。即ち、 g11=g1 ・m2 ,g22=g2 ・m1 となる。インバ―タを構成する素子S1 ,S2 ,S3,
S4 は新しいゲ―ト信号g11およびg22によって次のよ
うにオン、オフ制御される。即ち、 g11=1のとき、素子S1 をオン(素子S3 をオフ) g11=0のとき、素子S3 をオン(素子S1 をオフ) g22=0のとき、素子S2 をオン(素子S4 をオフ) g22=1のとき、素子S4 をオン(素子S2 をオフ) となる。[0029] The AND circuit the AND 1, gate - DOO signal g
Takes a 1 and a logic product of the output signal m 2 of the multivibrator circuit MM 2, new gate - get DOO signal g 11. The gate signal g 2 and the mono-multi circuit MM are output by the AND circuit AND 2.
ANDs the first output signal m 1, a new gate - get DOO signal g 22. That is, g 11 = g 1 · m 2 and g 22 = g 2 · m 1 . The elements S 1 , S 2 , S 3 ,
S 4 new gate - one as follows by preparative signals g 11 and g 22, are off-controlled. That is, when g 11 = 1, the element S 1 is turned on (the element S 3 is turned off). When g 11 = 0, the element S 3 is turned on (the element S 1 is turned off). When g 22 = 0, the element S 2 is turned on. Is turned on (the element S 4 is turned off). When g 22 = 1, the element S 4 is turned on (the element S 2 is turned off).
【0030】又、インバ―タの出力電圧VU は、素子S
1 ,S2 ,S3 ,S4 のオン、オフにより、次のように
変化する。但し、全体の直流電圧をVd とし、Vd1=V
d2=Vd /2とする。即ち、 素子S1 とS2 がオンのとき、VU =+Vd /2 素子S2 とS3 がオンのとき、VU =0 素子S3 とS4 がオンのとき、VU =−Vd /2 となり、3レベルの出力電圧となる。その平均値VU は
上記入力信号ei に比例位した値となる。The output voltage V U of the inverter is the same as that of the element S.
1, on the S 2, S 3, S 4 , the off varies as follows. Here, the entire DC voltage is V d, and V d1 = V
It is assumed that d2 = Vd / 2. That is, when the elements S 1 and S 2 are on, V U = + V d / 2, when the elements S 2 and S 3 are on, V U = 0 When the elements S 3 and S 4 are on, V U = − Vd / 2, which is a three-level output voltage. The average value V U is a value proportional to the input signal e i .
【0031】今、a点で入力信号e1 が急変した場合を
考える。ゲート信号g1 の幅が素子S1 の最小オン時間
Δtonより短くなるが、新しいゲート信号g11は、図示
しない回路にて、最終的に当該素子の最小オン時間Δt
onを確保するように破線で示す信号となる。Now, consider a case where the input signal e 1 changes suddenly at the point a. Although the width of the gate signal g 1 is shorter than the minimum on-time Δt on of the element S 1 , a new gate signal g 11 is shown in FIG.
Finally, the minimum on-time Δt of the device
The signal is indicated by a broken line so that on is secured.
【0032】一方、ゲート信号g 2 はaの時点で「1」
に変化するがモノマルチ回路MM 1 の出力m 1 が「0」
になるため、新しいゲート信号g 22 はモノマルチ回路M
M 1 の設定時間Δtだけ「0」の状態を保つ。 On the other hand, the gate signal g 2 becomes “1” at the time of a.
"0" is changed to the output m 1 of the multivibrator circuit MM 1 is
, The new gate signal g 22 is converted to the mono-multi circuit M
The state of “0” is maintained for the set time Δt of M 1 .
【0033】図3は、図2のa点付近を拡大したもので
ある。a点でモノマルチ回路MM1が動作し、Δtの時
間だけm1 =0となり、前のゲ―ト信号g2 がa点で
「0」から「1」に変っても、新しいゲ―ト信号g22は
「0」の状態を保っていることを示す。もう一方の新し
いゲ―ト信号g11は素子最小オン時間ΔtONだけパルス
幅が広げられるが、Δt>ΔtONに選ぶことにより、従
来問題となっていたモ―ドの発生はなくなる。FIG. 3 is an enlarged view of the vicinity of the point a in FIG. mono-multi circuit MM 1 operates at a point of time only m 1 = 0 next to Delta] t, the previous gate - also Hen' preparative signal g 2 from "0" at a point "1", a new gate - DOO signal g 22 indicates that retain the state of "0". The other new gate - DOO signal g 11 but the pulse width is widened by a minimum on-time Delta] t ON elements, by selecting the Delta] t> Delta] t ON, motor has conventionally been a problem - the generation of de will not.
【0034】即ち、g11=1のとき、素子S1 はオンに
なるが、図3からも解るようにg11=1のときは必ずg
22=0となり、素子S1 がオンのときS2 も必ずオンと
なり直流全電圧が素子S2 に印加されることはなくな
る。同様に、g22=1となるとときは必ずg11=0とな
り、素子S3 がオンのときS4 も必ずオンとなって、直
流全電圧が素子S3 に印加されることはなくなる。[0034] That is, when g 11 = 1, while element S 1 is turned on, always g when g 11 = 1 as can be seen from FIG. 3
22 = 0, and when the element S 1 is on, S 2 is always on, and the full DC voltage is not applied to the element S 2 . Similarly, when g 22 = 1, g 11 = 0 always, and when element S 3 is on, S 4 is also always on, so that the full DC voltage is not applied to element S 3 .
【0035】これを言い代えると、素子S2 がオフのと
き素子S1 もオフとなっており、図1の出力電流IU が
矢印の向きに流れている場合、ダイオ―ドD3 ,D4 が
導通し、全電圧Vd が素子S1 とS2 の直列回路に印加
されるが、両者ともオフなので、各素子にはVd /2の
電圧が印加される。同様に、素子S3 がオフのときは素
子S4 もオフとなっており、やはり各素子にはVd /2
以上の電圧は印加されない。In other words, when the element S 1 is off when the element S 2 is off, and when the output current I U of FIG. 1 is flowing in the direction of the arrow, the diodes D 3 and D 3 4 is rendered conductive, the entire voltage V d is applied to the series circuit of elements S 1 and S 2, since off both, each element voltage V d / 2 is applied. Similarly, element S 4 when element S 3 is turned off is also turned off, also the respective elements V d / 2
The above voltage is not applied.
【0036】即ち、従来のPWM制御装置によると、入
力信号ei が急激に変化すると、4つの素子S1 ,
S2 ,S3 ,S4 のうち、内側の素子S2 かS3 のいず
れかに直流全電圧がVd が印加される危険があったが、
本発明によれば、その危険をなくすることができるよに
なる。That is, according to the conventional PWM controller, when the input signal e i changes rapidly, the four elements S 1 ,
Among the S 2 , S 3 , and S 4 , there was a danger that the full DC voltage Vd was applied to either the inner element S 2 or S 3 ,
According to the present invention, the danger can be eliminated.
【0037】以上はU相分のインバ―タについて説明し
たが、V相、W相も同様に制御され、従来の問題点は解
決される。又、3相3線式の負荷にも同様に適用できる
ことは言うまでもない。The inverters for the U-phase have been described above. However, the V-phase and the W-phase are similarly controlled to solve the conventional problems. Needless to say, the present invention can be similarly applied to a three-phase three-wire load.
【0038】又、図1の制御回路は説明を分り易くする
ため、モノマルチ回路MM1,MM2やアンド回路AN
D1,AND2等を用いてハードウェアの制御ブロック
図として表わしたが、マイクロコンピータ等を用いて本
発明をソフトウェアによる演算で行なうことができるこ
とは言うまでもない。The control circuit shown in FIG. 1 uses the mono-multi circuits MM1 and MM2 and the AND circuit AN for easy understanding.
Although the control block diagram of the hardware is shown using D1, AND2, etc., it is needless to say that the present invention can be performed by a software operation using a microcomputer or the like.
【0039】以上は直流電力を交流電力に変換するイン
バ―タについて説明したが、交流電力を直流電力に変換
するコンバ―タについても同様に適用することができる
ことは言うまでもない。Although the inverter for converting DC power into AC power has been described above, it is needless to say that the same can be applied to a converter for converting AC power into DC power.
【0040】[0040]
【発明の効果】以上説明のように、本発明の中性点クラ
ンプ式電力変換器の制御装置によれば、PWM制御の入
力信号が急変しても、1つの素子に直流全電圧が印加さ
れるようなモ―ドを避けることができ、素子破壊の危険
をなくすることが可能となる。As described above, according to the controller of the neutral point clamp type power converter of the present invention, even if the input signal of the PWM control changes suddenly, the full DC voltage is applied to one element. Such a mode can be avoided, and the danger of element destruction can be eliminated.
【図1】本発明の中性点クランプ式電力変換器の制御装
置の一実施例を示す主回路構成図と制御装置のブロック
図。FIG. 1 is a main circuit configuration diagram showing a control device of a neutral point clamp type power converter according to an embodiment of the present invention, and a block diagram of the control device.
【図2】本発明の動作を説明するためのタイムチャ―ト
図。FIG. 2 is a time chart for explaining the operation of the present invention.
【図3】本発明の動作を説明するための[図2]のタイ
ムチャ―ト図の一部拡大図。FIG. 3 is a partially enlarged view of the time chart of FIG. 2 for explaining the operation of the present invention.
【図4】本発明が適用される中性点クランプ式電力変換
器の主回路構成図。FIG. 4 is a main circuit configuration diagram of a neutral point clamp type power converter to which the present invention is applied.
【図5】従来の中性点クランプ式電力変換器の制御装置
の動作を説明するためのタイムチャ―ト図。FIG. 5 is a time chart for explaining the operation of a conventional control device for a neutral point clamp type power converter.
【図6】従来の中性点クランプ式電力変換器の制御装置
において、PWM制御入力信号を急変させた場合のタイ
ムチャ―ト図。FIG. 6 is a time chart when a PWM control input signal is suddenly changed in a conventional neutral point clamp type power converter control device.
【図7】従来の中性点クランプ式電力変換器の制御装置
の動作を説明するための[図6]のタイムチャ―ト図の
一部拡大図。FIG. 7 is a partial enlarged view of the time chart of FIG. 6 for explaining the operation of the control device of the conventional neutral point clamp type power converter.
Vd1,Vd2…直流電源、S1 ,S2 ,S3 ,S4 …自己
消弧素子、D1 ,D2,D3 ,D4 …フリ―ホイリング
ダイオ―ド、D5 ,D6 …クランプ用ダイオ―ド、LO
AD…負荷、CTU …電流検出器、CU ,C1 ,C2 …
比較器、GU (s)…電流制御補償回路、TRG…三角波
発生器、SH1 ,SH2 …シュミット回路、MM1 ,M
M2 …モノマルチ回路、AND1 ,AND2 …論理積回
路。V d1, V d2 ... DC power source, S 1, S 2, S 3, S 4 ... self-turn-off device, D 1, D 2, D 3, D 4 ... flip - wheeling diode - de, D 5, D 6 ... clamp diode, LO
AD ... load, CT U ... current detector, C U, C 1, C 2 ...
Comparator, G U (s) ... current control compensation circuit, TRG ... triangular wave generator, SH 1, SH 2 ... Schmitt circuit, MM 1, M
M 2 : mono-multi circuit, AND 1 , AND 2 : AND circuit
Claims (1)
備えた直流電源と、前記直流端子間に同一極性で直列接
続された4個の自己消弧素子S1 ,S2 ,S3 ,S
4 と、これらの各素子にそれぞれ逆並列接続されるフリ
―ホイリングダイオ―ドD1 ,D2 ,D3 ,D4 と、直
列接続されている前記2個の自己消弧素子S2,S3 に
逆並列接続されるクランプ用ダイオ―ドD5 ,D6 の直
列回路と、前記自己消弧素子S1 とS3 及びS2 とS4
とが逆動作するように最小オン・オフ時間が確保された
ゲート信号でオンオフ制御するゲート制御手段を備え、
前記クランプ用ダイオ―ドD5 ,D6 の直列接続点と前
記中性点出力端子とを接続し、前記4個の自己消弧素子
S1 ,S2 ,S3 ,S4 の直列回路の中間接続点に交流
端子を設けた中性点クランプ式電力変換器において、 パルス幅変調制御用搬送波として、1つは零と+Emax
間で変化する三角波X、もう1つは該三角波Xと周波数
と位相が一致し零と−Emax 間で変化する三角波Yを発
生する手段と、−Emax ≦ei ≦+Emax を満すPWM
制御入力信号ei を発生する手段と、 この2つの三角波X,YとPWM制御入力信号ei とを
比較し、 ei >Xのとき、g1 =1 ei ≦Xのとき、g1 =0 ei ≧Yのとき、g2 =0 ei <Yのとき、g2 =1 となる第1及び第2のゲ―ト信号g1 ,g2 を作る手段
と、 前記第1のゲ―ト信号g1 が「1」から「0」に変化す
るとき素子の最少オン時間ΔtONより長い一定時間Δt
だけ「0」状態を保持した信号を発生する手段と、該手
段の信号に基づいて前記第2のゲ―ト信号g2 を前記時
間Δtだけ「0」の状態に固定させた新たなゲ―ト信号
g22を作る手段と、 前記第2のゲ―ト信号g2 が「1」から「0」に変化す
るとき素子の最少オン時間ΔtONより長い一定時間Δt
だけ「0」状態を保持した信号を発生する手段と、該手
段の信号に基づいて前記第1のゲ―ト信号g1 を前記時
間Δtだけ「0」の状態に固定させた新たなゲ―ト信号
g11を作る手段を設け、前記新たなゲ―ト信号g 11 及び
g 22 を前記ゲート制御手段を介して最小オン・オフ時間
を確保し て前記4個の自己消弧素子S 1 ,S 2 ,S 3 ,
S 4 に与え前記新たなゲ―ト信号g 11 で前記自己消弧素
子S 1 とS 3 が、前記新たなゲ―ト信号g 22 で前記自己
消弧素子S 2 とS 4 とが逆動作するようパルス幅変調制
御するようにしたことを特徴とする中性点クランプ式電
力変換器の制御装置。1. A DC power supply connected between DC terminals and having a neutral point output terminal, and four self-extinguishing elements S 1 , S 2 and S 3 connected in series with the same polarity between the DC terminals. , S
4 , free-wheeling diodes D 1 , D 2 , D 3 , D 4 connected in anti-parallel to these elements, respectively, and the two self-turn-off elements S 2 , connected in series. A series circuit of clamping diodes D 5 and D 6 connected in anti-parallel to S 3 , and the self-extinguishing elements S 1 and S 3 and S 2 and S 4
And gate control means for performing on / off control with a gate signal for which a minimum on / off time is secured so that the reverse operation is performed,
Said clamping diode - de D 5, connected in series connection point D 6 between the said neutral point output terminal, the series circuit of the four self-turn-off devices S 1, S 2, S 3 , S 4 In a neutral point clamp type power converter provided with an AC terminal at an intermediate connection point, one is zero and + Emax as a carrier for pulse width modulation control.
Triangular wave X which varies between, and one means for generating a triangular wave Y which varies between the triangular wave X and the frequency and phase match zero and -Emax, fully to PWM the -Emax ≦ e i ≦ + Emax
Comparing means for generating a control input signal e i, the two triangular wave X, and Y and the PWM control input signal e i, when e i> X, when g 1 = 1 e i ≦ X , g 1 Means for generating first and second gate signals g 1 and g 2 satisfying g 2 = 1 when g 2 = 0 e i <Y when = 0 e i ≧ Y; When the gate signal g 1 changes from “1” to “0”, a fixed time Δt longer than the minimum ON time Δt ON of the element
Only "0" state and the means for generating a held signal and on the basis of the signal of the unit the second gate - DOO signal g 2 only the time Δt "0" new gate which is fixed to the state - means for making bets signals g 22, the second gate - DOO signal g 2 is "1" from "0" to change long predetermined time than the minimum on-time Delta] t oN of the device when Delta] t
Only "0" state and the means for generating a held signal and on the basis of the signal of said means first gate - DOO signal g 1 only the time Δt "0" new gate which is fixed to the state - means for making bets signals g 11 provided, the new gate - DOO signals g 11 and
minimum on off time of g 22 via the gate control means
And the four self-extinguishing elements S 1 , S 2 , S 3 ,
The new gate applied to S 4 - the in preparative signal g 11 self Shokomoto
Child S 1 and S 3, the new gate - the self by preparative signal g 22
Controller of the neutral point clamped power converter, characterized in that the extinguishing element S 2 and S 4 is such that the pulse width modulation control to reverse action.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03033911A JP3029305B2 (en) | 1991-02-28 | 1991-02-28 | Neutral point clamp type power converter controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03033911A JP3029305B2 (en) | 1991-02-28 | 1991-02-28 | Neutral point clamp type power converter controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04275058A JPH04275058A (en) | 1992-09-30 |
JP3029305B2 true JP3029305B2 (en) | 2000-04-04 |
Family
ID=12399706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP03033911A Expired - Fee Related JP3029305B2 (en) | 1991-02-28 | 1991-02-28 | Neutral point clamp type power converter controller |
Country Status (1)
Country | Link |
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JP (1) | JP3029305B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH077957A (en) * | 1993-06-14 | 1995-01-10 | Toshiba Corp | Power converter |
JP3864307B2 (en) * | 2002-06-12 | 2006-12-27 | 株式会社安川電機 | PWM inverter control device and control method |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2821168B2 (en) * | 1989-03-31 | 1998-11-05 | 株式会社日立製作所 | Inverter device and AC motor drive system |
-
1991
- 1991-02-28 JP JP03033911A patent/JP3029305B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH04275058A (en) | 1992-09-30 |
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