JP3012575B2 - Manufacturing method of LOC semiconductor device - Google Patents

Manufacturing method of LOC semiconductor device

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Publication number
JP3012575B2
JP3012575B2 JP9271233A JP27123397A JP3012575B2 JP 3012575 B2 JP3012575 B2 JP 3012575B2 JP 9271233 A JP9271233 A JP 9271233A JP 27123397 A JP27123397 A JP 27123397A JP 3012575 B2 JP3012575 B2 JP 3012575B2
Authority
JP
Japan
Prior art keywords
adhesive
semiconductor chip
semiconductor device
loc
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9271233A
Other languages
Japanese (ja)
Other versions
JPH11111739A (en
Inventor
伸之 森
Original Assignee
九州日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 九州日本電気株式会社 filed Critical 九州日本電気株式会社
Priority to JP9271233A priority Critical patent/JP3012575B2/en
Publication of JPH11111739A publication Critical patent/JPH11111739A/en
Application granted granted Critical
Publication of JP3012575B2 publication Critical patent/JP3012575B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To increase the bonding strength of an adhesive in contact with resin protective film formed on a semiconductor chip and to prevent the leak defect of the semiconductor chip, by softening the adhesive by cleaning it with organic solvent or by activating the surface of the adhesive by plasma-cleaning it with inert gas before it is pressed. SOLUTION: An adhesive 3 on the side to which an inner lead 1 is not bonded is dipped in an acetone solvent 8 until the adhesive 3 is softened or slightly fused. Then, a polyimide film 4 to which the dipped adhesive 3 is bonded is pressed at a temperature of about 200 deg.C on a semiconductor chip 6 to which a polyimide resin 5 acting as a protective film is bonded. If the adhesive is cleaned with organic solvent in this way, the adhesive is softened to prevent air bubbles from being trapped therein and hence to improve the wetting of bonding interface, which increases a bonding force. Further, if the adhesive is plasma-cleaned with inert gas, the surface of the adhesive is activated to improve the bonding force.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ＬＯＣ（リードオ
ンチップ）構造を有する半導体装置の製造方法に関し、
特に半導体チップとインナーリードとの接合強度を向上
させたＬＯＣ型半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device having a LOC (lead-on-chip) structure.
In particular, the present invention relates to a method for manufacturing a LOC semiconductor device with improved bonding strength between a semiconductor chip and inner leads.

【０００２】[0002]

【従来の技術】従来、樹脂封止型半導体装置の製造方法
としては、リードフレームのアイランドに半導体チップ
を搭載し、この半導体チップとリードフレームのインナ
ーリードとをボンディングワイヤで接続し、その後、樹
脂モールド封止を行う方法が一般的である。しかし、最
近はアイランドを省いたリードフレームを使用し、半導
体チップを直接インナーリードに接合することによっ
て、半導体チップをリードフレームに固定する方法が広
く用いられている。2. Description of the Related Art Conventionally, as a method of manufacturing a resin-encapsulated semiconductor device, a semiconductor chip is mounted on an island of a lead frame, and the semiconductor chip and inner leads of the lead frame are connected by bonding wires. A method of performing mold sealing is general. However, recently, a method of fixing a semiconductor chip to a lead frame by using a lead frame without an island and directly bonding the semiconductor chip to inner leads has been widely used.

【０００３】その一つの方法として、半導体チップの上
面に直接インナーリードを接合するＬＯＣ構造の半導体
装置がある。この従来のＬＯＣ構造の半導体装置は、図
３（ａ）の接合前の断面図に示すように、半導体チップ
６の上面の回路形成面上に、電極パッド７を除く部分を
ポリイミド樹脂５で被覆した保護膜を設け（特開平４−
２９１９４７号公報）、一方、表裏両面にエポキシ樹脂
からなる接着剤２，３を付着させた絶縁フィルムである
ポリイミドフィルム４を、インナーリード１にあらかじ
め接着剤２を介して接合させたリードフレームを準備す
る。As one of the methods, there is a semiconductor device having a LOC structure in which an inner lead is directly joined to an upper surface of a semiconductor chip. In this conventional semiconductor device having a LOC structure, as shown in a cross-sectional view before bonding in FIG. 3A, a portion excluding an electrode pad 7 is covered with a polyimide resin 5 on a circuit forming surface on an upper surface of a semiconductor chip 6. (See Japanese Unexamined Patent Publication No.
On the other hand, a lead frame is prepared in which a polyimide film 4 which is an insulating film having adhesives 2 and 3 made of an epoxy resin adhered to both front and back surfaces is bonded to an inner lead 1 in advance via an adhesive 2. I do.

【０００４】次いで、図３（ｂ）の接合後の断面図に示
すように、この絶縁フィルム付きのリードフレームを、
接着剤３により半導体チップ６上のポリイミド樹脂５に
約２００℃で熱圧着し、その後、インナーリード１と電
極パッド７との間をボンディングワイヤで接続し、モー
ルド樹脂で封止してパッケージを完成する。なお、上記
の絶縁フィルム付きリードフレームは、リードフレーム
メーカーからインナーリード部にポリイミドフィルムを
接着した状態で納入されている。[0004] Next, as shown in the cross-sectional view after bonding in FIG.
A thermocompression bonding is performed on the polyimide resin 5 on the semiconductor chip 6 with the adhesive 3 at about 200 ° C., and then the inner lead 1 and the electrode pad 7 are connected with a bonding wire and sealed with a mold resin to complete a package. I do. The above lead frame with an insulating film is supplied by a lead frame maker with a polyimide film adhered to an inner lead portion.

【０００５】[0005]

【発明が解決しようとする課題】この従来のＬＯＣ型半
導体装置は、パッケージ信頼性試験、特に耐湿性加速試
験で、ポリイミドフィルム４の接着剤３と半導体チップ
６上のポリイミド樹脂５との界面に剥離を生じ、それが
進行して電極パッド７まで達し、そこへ水分が溜まりや
すくなって回路配線のアルミニウムが腐食を起こし、パ
ッケージがリーク不良を起こすことが知られている。This conventional LOC type semiconductor device can be used in a package reliability test, especially in an accelerated moisture resistance test, at the interface between the adhesive 3 of the polyimide film 4 and the polyimide resin 5 on the semiconductor chip 6. It is known that peeling occurs, which progresses to reach the electrode pad 7, where water easily accumulates, aluminum of the circuit wiring is corroded, and a package causes a leak failure.

【０００６】その理由は、接着剤３と半導体チップ６上
のポリイミド樹脂５との間の密着力が弱いためと考えら
れる。しかし、接着剤３と同じ材質である接着剤２と、
ポリイミド樹脂５と同じ材質であるポリイミドフィルム
４との間の密着性は、信頼性試験では問題がないことか
ら、半導体チップ６とインナーリード１とを熱圧着する
前の、接着剤３とポリイミド樹脂５の表面状態が関係し
ていることが考えられる。本発明は、上記問題点を解消
し、接着剤３とポリイミド樹脂５との密着性を向上させ
ることによって、半導体チップ６とインナーリード１と
の接合強度を高め、半導体装置のリーク不良を防止する
ことを目的とする。It is considered that the reason is that the adhesive force between the adhesive 3 and the polyimide resin 5 on the semiconductor chip 6 is weak. However, the adhesive 2 which is the same material as the adhesive 3,
Since the adhesion between the polyimide resin 5 and the polyimide film 4 made of the same material has no problem in the reliability test, the adhesive 3 and the polyimide resin before the semiconductor chip 6 and the inner lead 1 are thermocompression-bonded. It is considered that the surface state of No. 5 is related. The present invention solves the above problems and improves the adhesiveness between the adhesive 3 and the polyimide resin 5, thereby increasing the bonding strength between the semiconductor chip 6 and the inner lead 1 and preventing the semiconductor device from leaking. The purpose is to:

【０００７】[0007]

【課題を解決するための手段】本発明は、表裏両面に接
着剤を付着させた絶縁フィルムを介して、上面に樹脂保
護膜を形成した半導体チップとインナーリードとを熱圧
着により接合するＬＯＣ型半導体装置の製造方法におい
て、前記半導体チップ上に形成された樹脂保護膜と接触
する接着剤を、熱圧着前に有機溶剤洗浄により軟化処理
するか、または、接着剤表面を不活性ガスのプラズマ洗
浄により活性化処理することを特徴とするＬＯＣ型半導
体装置の製造方法である。According to the present invention, there is provided a LOC type in which a semiconductor chip having a resin protective film formed on an upper surface and an inner lead are joined by thermocompression bonding via an insulating film having an adhesive adhered to both surfaces. In the method of manufacturing a semiconductor device, the adhesive which comes into contact with the resin protective film formed on the semiconductor chip is softened by washing with an organic solvent before thermocompression bonding, or the surface of the adhesive is washed with an inert gas by plasma. A method for manufacturing a LOC-type semiconductor device, characterized by performing an activation process.

【０００８】[0008]

【発明の実施の形態】まず、本発明が解決すべき手段の
作用効果について説明する。従来技術で述べたように、
ポリイミドフィルム上の接着剤はエポキシ樹脂であり、
これをアセトン等の有機溶剤に浸すとエポキシ樹脂は軟
化する。これを半導体チップ上のポリイミド樹脂へ圧着
させると、気泡ができにくくなる。また、界面の濡れ性
が向上することにより、ポリイミドフィルム上の接着剤
と半導体チップ上のポリイミド樹脂との密着力が向上す
る。また、前記接着剤をアルゴン等の不活性ガスでプラ
ズマ洗浄すると、接着剤表面が活性化されることにより
樹脂同志の結合力が向上する。よって、ポリイミドフィ
ルム上の接着剤と半導体チップ上のポリイミド樹脂との
密着力が向上する。DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the function and effect of the means to be solved by the present invention will be described. As mentioned in the prior art,
The adhesive on the polyimide film is an epoxy resin,
When this is immersed in an organic solvent such as acetone, the epoxy resin softens. When this is pressed against the polyimide resin on the semiconductor chip, bubbles are less likely to be formed. Further, by improving the wettability of the interface, the adhesion between the adhesive on the polyimide film and the polyimide resin on the semiconductor chip is improved. When the adhesive is plasma-cleaned with an inert gas such as argon, the surface of the adhesive is activated, thereby improving the bonding strength between the resins. Therefore, the adhesive force between the adhesive on the polyimide film and the polyimide resin on the semiconductor chip is improved.

【０００９】次に、本発明の第１の実施の形態を図１を
用いて説明する。図１（ａ）は溶剤処理方法を示す断面
図、図１（ｂ）は接合後の断面図である。まず、インナ
ーリード１に絶縁フィルムであるポリイミドフィルム４
を接着剤２を介して接着させたリードフレームを準備
し、図１（ａ）に示すように、インナーリード１の接合
されていない側の接着剤３をアセトン溶剤８に浸漬させ
る。浸漬は、接着剤３が軟化あるいは若干溶融状態にな
るまで行う。アセトン溶剤８の温度は、常温でもよいが
多少加熱しておいた方が好ましい。Next, a first embodiment of the present invention will be described with reference to FIG. FIG. 1A is a cross-sectional view illustrating a solvent processing method, and FIG. 1B is a cross-sectional view after bonding. First, a polyimide film 4 which is an insulating film is
Is prepared by bonding an adhesive 3 via an adhesive 2, and the adhesive 3 on the unbonded side of the inner lead 1 is immersed in an acetone solvent 8 as shown in FIG. The immersion is performed until the adhesive 3 is softened or slightly melted. The temperature of the acetone solvent 8 may be room temperature, but is preferably slightly heated.

【００１０】その後、図１（ｂ）に示すように、保護膜
であるポリイミド樹脂５が被着された半導体チップ６
に、浸漬処理を行った接着剤３が被着されているポリイ
ミドフィルム４を約２００℃で熱圧着させる。そして、
全体を中性雰囲気または大気中で２００℃、１時間の加
熱処理を行うことにより接着剤３を硬化させ、半導体チ
ップ６にインナーリード１を固着させる。そして、最後
に樹脂モールド封止を行い、ＬＯＣ型パッケージを完成
させる。After that, as shown in FIG. 1B, a semiconductor chip 6 on which a polyimide resin 5 as a protective film is adhered.
Then, the polyimide film 4 on which the adhesive 3 subjected to the immersion treatment is adhered is thermocompression-bonded at about 200 ° C. And
The adhesive 3 is cured by performing a heat treatment at 200 ° C. for 1 hour in a neutral atmosphere or the atmosphere to fix the inner lead 1 to the semiconductor chip 6. Finally, resin molding is performed to complete the LOC package.

【００１１】次に、本発明の第２の実施の形態について
図２を用いて説明する。図２（ａ）はプラズマ処理方法
を示す図、図２（ｂ）は接合後の断面図である。まず、
第１の実施の形態と同様、インナーリード１にポリイミ
ドフィルム４を接着剤２を介して接着させたリードフレ
ームを準備する。そして、図２（ａ）に示すように、イ
ンナーリード１と反対側の接着剤３に不活性ガス、例え
ばアルゴンガスのプラズマ９で洗浄する。Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2A is a diagram showing a plasma processing method, and FIG. 2B is a cross-sectional view after bonding. First,
As in the first embodiment, a lead frame in which a polyimide film 4 is adhered to the inner leads 1 via an adhesive 2 is prepared. Then, as shown in FIG. 2A, the adhesive 3 on the side opposite to the inner lead 1 is cleaned with a plasma 9 of an inert gas, for example, argon gas.

【００１２】そして、図２（ｂ）に示すように、このプ
ラズマ処理を施した接着剤３と、半導体チップ６上のポ
リイミド樹脂５とを熱圧着させる。この際、接着剤３の
表面が活性化しているため結合力が向上する。その後、
全体を雰囲気中で加熱処理し、半導体チップ６にインナ
ーリード１を固着させる。なお、熱圧着および加熱処理
の条件は、第１の実施の形態と同じである。そして、最
後に樹脂モールド封止を行い、ＬＯＣ型パッケージを完
成させる。Then, as shown in FIG. 2B, the adhesive 3 subjected to the plasma treatment and the polyimide resin 5 on the semiconductor chip 6 are thermocompression bonded. At this time, the bonding force is improved because the surface of the adhesive 3 is activated. afterwards,
The whole is subjected to a heat treatment in an atmosphere to fix the inner leads 1 to the semiconductor chip 6. The conditions of the thermocompression bonding and the heat treatment are the same as in the first embodiment. Finally, resin molding is performed to complete the LOC package.

【００１３】以上、第１および第２の実施の形態で述べ
た本発明のＬＯＣ型半導体装置に、耐湿性加速試験（温
度サイクル、ベーク、恒温恒湿保管、半田リフローなど
の前処理後、湿度１００％、温度１２５℃、２．３気
圧、２８８時間の試験）を行い、その後、超音波による
非破壊検査を実施した結果、パッケージ内においてイン
ナーリードの剥離が発生していないことが確認できた。As described above, the LOC type semiconductor device of the present invention described in the first and second embodiments is subjected to a humidity resistance accelerated test (temperature cycle, baking, constant temperature / humidity storage, pretreatment such as solder reflow, humidity 100%, a temperature of 125 ° C., a pressure of 2.3 atm, and a test of 288 hours), and then a non-destructive inspection by ultrasonic wave was performed. As a result, it was confirmed that the inner lead did not peel in the package. .

【００１４】[0014]

【発明の効果】本発明によれば、ポリイミドフィルムの
接着剤と半導体チップ上のポリイミド樹脂との界面の密
着力の向上が得られ、その結果、耐湿性加速試験による
リーク不良の発生がなくなる。その理由は、接着剤を有
機溶剤で洗浄すると接着剤が軟化し、熱圧着時に気泡の
混入がなくなるとともに接着界面の濡れ性が向上するた
め密着力が向上するからである。また、接着剤を不活性
ガス等でプラズマ洗浄すると、接着剤表面が活性化さ
れ、半導体チップ上のポリイミド樹脂との結合力が向上
し、密着性が向上するからである。According to the present invention, the adhesion at the interface between the adhesive of the polyimide film and the polyimide resin on the semiconductor chip can be improved, and as a result, the occurrence of leak failure due to the accelerated moisture resistance test is eliminated. The reason for this is that when the adhesive is washed with an organic solvent, the adhesive is softened, bubbles are not mixed during thermocompression bonding, and the wettability of the adhesive interface is improved, so that the adhesion is improved. Further, when the adhesive is plasma-cleaned with an inert gas or the like, the surface of the adhesive is activated, the bonding force with the polyimide resin on the semiconductor chip is improved, and the adhesion is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態を説明する図で、図
（ａ）は溶剤処理方法を示す断面図、図（ｂ）は接合後
の断面図である。FIGS. 1A and 1B are diagrams illustrating a first embodiment of the present invention. FIG. 1A is a cross-sectional view illustrating a solvent processing method, and FIG. 1B is a cross-sectional view after bonding.

【図２】本発明の第２の実施の形態を説明する図で、図
（ａ）はプラズマ処理方法を示す断面図、図（ｂ）は接
合後の断面図である。FIGS. 2A and 2B are views for explaining a second embodiment of the present invention. FIG. 2A is a sectional view showing a plasma processing method, and FIG. 2B is a sectional view after bonding.

【図３】従来のＬＯＣ型半導体装置を示す図で、図
（ａ）は接合前の断面図、図（ｂ）は接合後の断面図で
ある。3A and 3B are views showing a conventional LOC semiconductor device, wherein FIG. 3A is a cross-sectional view before bonding, and FIG. 3B is a cross-sectional view after bonding.

【符号の説明】[Explanation of symbols]

１ インナーリード ２ 接着剤 ３ 接着剤 ４ ポリイミドフィルム ５ ポリイミド樹脂 ６ 半導体チップ ７ 電極パッド ８ アセトン溶剤 ９ プラズマ DESCRIPTION OF SYMBOLS 1 Inner lead 2 Adhesive 3 Adhesive 4 Polyimide film 5 Polyimide resin 6 Semiconductor chip 7 Electrode pad 8 Acetone solvent 9 Plasma

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 表裏両面に接着剤を付着させた絶縁フィ
ルムを介して、上面に樹脂保護膜を形成した半導体チッ
プとインナーリードとを熱圧着により接合するＬＯＣ型
半導体装置の製造方法において、前記半導体チップ上に
形成された樹脂保護膜と接触する接着剤を、熱圧着前に
軟化処理することを特徴とするＬＯＣ型半導体装置の製
造方法。1. A method of manufacturing a LOC semiconductor device, wherein a semiconductor chip having a resin protective film formed on an upper surface and an inner lead are joined by thermocompression bonding via an insulating film having an adhesive adhered to both front and back surfaces. A method for manufacturing a LOC type semiconductor device, comprising softening an adhesive in contact with a resin protective film formed on a semiconductor chip before thermocompression bonding. 【請求項２】 前記軟化処理が有機溶剤による洗浄処理
であることを特徴とする請求項１記載のＬＯＣ型半導体
装置の製造方法。2. The method according to claim 1, wherein the softening process is a cleaning process using an organic solvent. 【請求項３】 前記有機溶剤がアセトンであることを特
徴とする請求項２記載のＬＯＣ型半導体装置の製造方
法。3. The method according to claim 2, wherein the organic solvent is acetone. 【請求項４】 表裏両面に接着剤を付着させた絶縁フィ
ルムを介して、上面に樹脂保護膜を形成した半導体チッ
プとインナーリードとを熱圧着により接合するＬＯＣ型
半導体装置の製造方法において、前記半導体チップ上に
形成された樹脂保護膜と接触する接着剤の表面を、熱圧
着前に活性化処理することを特徴とするＬＯＣ型半導体
装置の製造方法。4. A method of manufacturing a LOC semiconductor device, wherein a semiconductor chip having a resin protective film formed on an upper surface and an inner lead are joined by thermocompression bonding via an insulating film having an adhesive adhered to both front and back surfaces. A method for manufacturing a LOC semiconductor device, comprising activating a surface of an adhesive in contact with a resin protective film formed on a semiconductor chip before thermocompression bonding. 【請求項５】 前記活性化処理が不活性ガスのプラズマ
洗浄処理であることを特徴とする請求項４記載のＬＯＣ
型半導体装置の製造方法。5. The LOC according to claim 4, wherein the activation processing is a plasma cleaning processing of an inert gas.
Of manufacturing a semiconductor device.
JP9271233A 1997-10-03 1997-10-03 Manufacturing method of LOC semiconductor device Expired - Fee Related JP3012575B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9271233A JP3012575B2 (en) 1997-10-03 1997-10-03 Manufacturing method of LOC semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9271233A JP3012575B2 (en) 1997-10-03 1997-10-03 Manufacturing method of LOC semiconductor device

Publications (2)

Publication Number Publication Date
JPH11111739A JPH11111739A (en) 1999-04-23
JP3012575B2 true JP3012575B2 (en) 2000-02-21

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3169072B2 (en) 1998-05-15 2001-05-21 日本電気株式会社 Semiconductor device
JP4844168B2 (en) * 2006-02-28 2011-12-28 パナソニック株式会社 Component joining method and component stacking method
CN106356321B (en) * 2016-09-26 2019-04-12 昆山工研院新型平板显示技术中心有限公司 The method for removing bubble in flexible base board

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