JP2972653B2 - Power failure detection circuit - Google Patents
Power failure detection circuitInfo
- Publication number
- JP2972653B2 JP2972653B2 JP9151102A JP15110297A JP2972653B2 JP 2972653 B2 JP2972653 B2 JP 2972653B2 JP 9151102 A JP9151102 A JP 9151102A JP 15110297 A JP15110297 A JP 15110297A JP 2972653 B2 JP2972653 B2 JP 2972653B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- transformer
- failure
- dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Dc-Dc Converters (AREA)
- Power Conversion In General (AREA)
- Measurement Of Current Or Voltage (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電源故障検出回路
に関し、特にトランスを用いたスイッチング電源の故障
検出回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply failure detection circuit, and more particularly, to a switching power supply failure detection circuit using a transformer.
【０００２】[0002]
【従来の技術】各別に電力が入力される複数のスイッチ
ング電源の出力を並列接続して大出力を得るようにした
並列接続運転の電源において、いずれかのスイッチング
電源のみが故障して動作しなくなったことを完全に検出
することは、従来困難であった。このようなスイッチン
グ電源の故障検出回路が特開平３−１５９５６６号公報
に開示されている図４は従来の電源故障検出回路の図で
ある。直流の入力電圧ＶINをＦＥＴ１により短い周期で
断続させてトランス２の一次側に印加する。トランス２
の二次側には、２次整流ダイオード３，４、チョークコ
イル５、出力平滑コンデンサ６を接続し出力電圧ＶO を
得る。ピーク整流回路７の入力端の一方をトランス２の
二次側の一端に接続し他方を接地し出力端をコンパレー
タ８の−入力に接続する。基準電圧電源１４をコンパレ
ータ８の＋入力に接続し、トランス２の２次側のパルス
電圧が基準電圧より低くなった時にコンパレータ８から
故障を示すアラームを出力してした。2. Description of the Related Art In a power supply of a parallel connection operation in which outputs of a plurality of switching power supplies to which electric powers are individually inputted are connected in parallel to obtain a large output, only one of the switching power supplies fails and stops operating. It has been conventionally difficult to completely detect that. Such a switching power supply failure detection circuit is disclosed in JP-A-3-159566, and FIG. 4 is a diagram of a conventional power supply failure detection circuit. The DC input voltage V IN is intermittently applied in a short cycle by the FET 1 and applied to the primary side of the transformer 2. Transformer 2
Are connected to secondary rectifier diodes 3, 4, choke coil 5, and output smoothing capacitor 6 to obtain output voltage V O. One of the input terminals of the peak rectifier circuit 7 is connected to one end on the secondary side of the transformer 2, the other is grounded, and the output terminal is connected to the negative input of the comparator 8. The reference voltage power supply 14 is connected to the + input of the comparator 8, and when the pulse voltage on the secondary side of the transformer 2 becomes lower than the reference voltage, the comparator 8 outputs an alarm indicating failure.
【０００３】ピーク整流回路７は入力端の一方と出力端
の間に抵抗１５を接続し、入力端の他方と出力端の間に
コンデンサ１７と抵抗１６を配列に接続したものであ
る。The peak rectifier circuit 7 has a resistor 15 connected between one of the input terminals and an output terminal, and a capacitor 17 and a resistor 16 connected in an array between the other input terminal and the output terminal.
【０００４】図４の電源故障検出回路はトランス２の２
次側のパルス電圧を検出し基準電圧と比較し、このパル
ス電圧は、負荷電流が無いと発生しないので、正常動作
をしていてもある規定値より小さい負荷の時には不足電
流によるアラームを出力してしまう。そこで誤検出を防
止する為、常に内部回路電流を流す目的で、ダミー抵抗
１３を出力端子間に接続する必要があった。The power supply failure detection circuit shown in FIG.
The pulse voltage on the secondary side is detected and compared with the reference voltage.This pulse voltage does not occur unless there is a load current.If the load is smaller than a specified value even during normal operation, an alarm due to insufficient current is output. Would. Therefore, in order to prevent erroneous detection, it is necessary to connect the dummy resistor 13 between the output terminals for the purpose of always flowing the internal circuit current.
【０００５】[0005]
【発明が解決しようとする課題】従来の技術においては
出力端間にダミー抵抗を接続する必要があるという欠点
があった。また、ダミー抵抗を接続しなければ電源の負
荷が少ない時、電源が故障していないにも関わらず、不
足電流によるアラームを出力してしまうことである。The prior art has a disadvantage that a dummy resistor must be connected between output terminals. Further, if a dummy resistor is not connected, when the load of the power supply is small, an alarm due to an insufficient current is output even though the power supply is not faulty.
【０００６】その理由は、従来の電源故障検出回路は出
力電流が規定値以下となった場合を検出して故障と判定
する為、負荷電流が規定値以下となったと時、電源が故
障していないにも関わらず不足電流によるアラームを出
力してしまうからである。本発明の目的はダミー抵抗な
しでスイッチング電源において、軽負荷時においても、
故障か正常かを正確に検出することである。The reason is that the conventional power supply failure detection circuit detects a case where the output current is less than a specified value and determines that a failure has occurred. Therefore, when the load current becomes less than the specified value, the power supply fails. This is because an alarm due to insufficient current is output in spite of the absence. An object of the present invention is to provide a switching power supply without a dummy resistor even at a light load.
It is to accurately detect whether it is faulty or normal.
【０００７】[0007]
【課題を解決するための手段】本願発明の電源故障検出
回路は、入力電圧（図１のＶIN）をスイッチング素子に
より周期的に断続させてトランスの（図１の２）の一次
側に印加し前記トランスの二次側から出力電圧を得る電
源回路の故障を検出する回路において、前記スイッチン
グ素子の両端子間の電圧のピーク値を出力するピーク整
流回路（図１の７）と、前記入力電圧が前記ピーク値を
越えた時に故障を示すアラームを出力するコンパレータ
（図１の８）とを備えている。According to the power supply failure detection circuit of the present invention, an input voltage (V IN in FIG. 1) is periodically intermittently switched by a switching element and applied to a primary side of a transformer (2 in FIG. 1). A circuit for detecting a failure of a power supply circuit that obtains an output voltage from the secondary side of the transformer, wherein a peak rectifier circuit (7 in FIG. 1) for outputting a peak value of a voltage between both terminals of the switching element; A comparator (8 in FIG. 1) for outputting an alarm indicating a failure when the voltage exceeds the peak value.
【０００８】本願発明の電源故障検出回路は、入力電圧
（図３のＶIN）をスイッチング素子により周期的に断続
させてトランス（図３の２）の一次側に印加し前記トラ
ンスの二次側から出力電圧を得る電源回路の故障を検出
する回路において、前記入力電圧を分圧する分圧回路
（図３の１１、１２）と、前記スイッチング素子の両端
子間の電圧のピーク値を出力するピーク整流回路（図３
の７）と、前記分圧回路により前記入力電圧を分圧した
分圧電圧が前記ピーク値を越えた時に故障を示すアラー
ムを出力するコンパレータ（図３の８）とを備えてい
る。The power failure detection circuit according to the present invention is configured such that an input voltage (V IN in FIG. 3) is periodically intermittently switched by a switching element and applied to a primary side of a transformer (2 in FIG. 3) to apply a secondary side of the transformer. A voltage dividing circuit (11, 12 in FIG. 3) for dividing the input voltage, and a peak for outputting a peak value of a voltage between both terminals of the switching element. Rectifier circuit (Fig. 3
7), and a comparator (8 in FIG. 3) that outputs an alarm indicating a failure when the divided voltage obtained by dividing the input voltage by the voltage dividing circuit exceeds the peak value.
【０００９】本発明の電源故障検出回路は、入力電圧
（図３のＶIN）をスイッチング素子により周期的に断続
させてトランスの一次側に印加し前記トランスの二次側
から出力電圧を得る電源回路の故障を検出する回路にお
いて、前記入力電圧を分圧する分圧回路（図３の１１、
１２）と、前記スイッチング素子の両端子間の電圧を分
圧したものの分圧ピーク値を出力する分圧ピーク整流回
路（図３の７、９、１０）と、前期分圧回路により前記
入力電圧を分圧した分圧電圧が前記分圧ピーク値を越え
た時に故障を示すアラームを出力するコンパレータ（図
３の８）とを備えている上述の電源故障検出回路のいず
れにおいても、前記スイッチング素子にはＦＥＴ（図１
の１）を、前記スイッチング素子の両端子間の電圧は前
記ＦＥＴのドレイン−ソース電圧を例示することができ
る。A power supply failure detection circuit according to the present invention is a power supply that applies an input voltage (V IN in FIG. 3) periodically to a primary side of a transformer by a switching element and obtains an output voltage from a secondary side of the transformer. In a circuit for detecting a circuit failure, a voltage dividing circuit (11 in FIG. 3) for dividing the input voltage.
12), a voltage dividing peak rectifier circuit (7, 9, 10 in FIG. 3) for outputting a voltage dividing peak value obtained by dividing a voltage between both terminals of the switching element, and the input voltage by the voltage dividing circuit. And a comparator (8 in FIG. 3) for outputting an alarm indicating a failure when the divided voltage obtained by dividing the voltage exceeds the divided voltage peak value. Is an FET (Fig. 1
In 1), the voltage between both terminals of the switching element can be exemplified by the drain-source voltage of the FET.
【００１０】ＦＥＴのドレシン−ソース波形の（スイッ
チング素子の両端子間の電圧波形）のピーク値を観測
し、入力電圧と比較する。ＦＥＴのドレイン−ソース電
圧波形は、トランスのインダクタンス成分ＬとＦＥＴの
内部要領Ｃによって共振を越こし、そのピーク値は無負
荷時においても入力電圧より大きくなる。ＦＥＴのドレ
イン−ソース電圧のピーク値と入力電圧値とを比較する
ことにより、従来不可能であった無負荷時の正常動作の
確認が可能となる。The peak value of the dressing-source waveform (voltage waveform between both terminals of the switching element) of the FET is observed and compared with the input voltage. The drain-source voltage waveform of the FET goes through resonance due to the inductance component L of the transformer and the internal procedure C of the FET, and its peak value becomes larger than the input voltage even when there is no load. By comparing the peak value of the drain-source voltage of the FET with the input voltage value, it is possible to confirm the normal operation at the time of no load, which was impossible in the past.
【００１１】[0011]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して詳細に説明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
【００１２】図１を参照すると、本発明の第１の実施の
形態の電源故障検出回路は、ＦＥＴ１、トランス２、
２、次整流ダイオード３，４、チョークコイル５、出力
平滑コンデンサ６を有するスイッチング電源において、
ＦＥＴ１のドレイン側をピーク整流回路７の入力端の一
方に入力し、ＦＥＴ１のソース側をピーク整流回路７の
入力端の他方に接続し、ピーク整流回路７の出力をコン
パレータ８の一入力に接続する。一方、入力電圧ＶINの
＋側とコンパレータ８の＋入力を接続する。Referring to FIG. 1, a power supply failure detecting circuit according to a first embodiment of the present invention comprises an FET1, a transformer 2,
2. In a switching power supply having secondary rectifier diodes 3 and 4, a choke coil 5, and an output smoothing capacitor 6,
The drain side of the FET1 is input to one of the input terminals of the peak rectifier circuit 7, the source side of the FET1 is connected to the other input terminal of the peak rectifier circuit 7, and the output of the peak rectifier circuit 7 is connected to one input of the comparator 8. I do. On the other hand, the + side of the input voltage V IN and the + input of the comparator 8 are connected.
【００１３】コンパレータ８では、入力電圧ＶINの値
と、ＦＥＴ１のドレイン−ソース電圧ピークを比較し、
入力電圧ＶINのがＦＥＴ１のドレイン−ソース電圧ピー
ク値に対し大きいか等しい時に出力をアラームとする。The comparator 8 compares the value of the input voltage V IN with the drain-source voltage peak of the FET 1,
When the input voltage V IN is greater than or equal to the drain-source voltage peak value of the FET1, the output is set as an alarm.
【００１４】図２（ａ）〜（ｃ）は、ＦＥＴ１のドレイ
ン−ソース電圧ＶDSの波形図でそれぞれぞれＦＥＴ１の
オンオフ動作が停止している時の図、ＦＥＴ１がオンオ
フ動作しているがスイッチング電源の出力側が無負荷で
ある時の図及びＦＥＴ１がオンオフ動作していてスイッ
チング電源の出力側に負荷が接続されている時の図であ
る。FIGS. 2A to 2C are waveform diagrams of the drain-source voltage V DS of the FET 1 when the ON / OFF operation of the FET 1 is stopped. FIG. FIG. 3 is a diagram when the output side of the switching power supply is unloaded and a diagram when the load is connected to the output side of the switching power supply when the FET 1 is performing on / off operation.
【００１５】ＦＥＴ１のドレイン−ソース電圧ＶDS波形
は、図２に示すように、動作している限り無負荷時にお
いてもトランス２のインダクタンス成分ＬとＦＥＴ１の
内部要領Ｃによって共振を起こし、そのピーク値は入力
電圧ＶINより大きくなる。[0015] FET1 drain of - source voltage V DS waveform, as shown in FIG. 2, resonated by the internal procedure C inductance component L and FET1 of the transformer 2 even no load as long as they are operating, the peak The value will be greater than the input voltage V IN .
【００１６】よって、コンパレータ８により、ＦＥＴ１
のドレイン−ソース電圧のピーク値すなわちピーク整流
回路７の出力電圧と入力電圧値ＶINを比較することによ
り、従来不可能であった無負荷時の正常動作の確認が可
能である。Therefore, the comparator 8 controls the FET 1
By comparing the peak value of the drain-source voltage, that is, the output voltage of the peak rectifier circuit 7 with the input voltage value VIN , it is possible to confirm the normal operation at the time of no load, which was conventionally impossible.
【００１７】次に本発明の第２の実施の形態の電源故障
検出回路について図面を参照して詳細に説明する。Next, a power supply failure detection circuit according to a second embodiment of the present invention will be described in detail with reference to the drawings.
【００１８】図３を参照すると、本発明の第２の実施の
形態は、ＦＥＴ１、トランス２、整流ダイオード３，
４、チョークコイル５、出力コンデンサ６を有するスイ
ッチング電源において、ＦＥＴ１のドレイン−ソース間
の電圧を抵抗９と抵抗１０で分圧した値をピーク整流回
路７の入力端の一方に入力し、ＦＥＴ１のソース側をピ
ーク整流回路の７の入力端の他方に接続し、ピーク整流
回路７の出力をコンパレータ８の一入力に接続する。一
方、入力電圧ＶINを抵抗１１と抵抗１２で分圧した値と
コンパレータ８の＋入力を接続する。Referring to FIG. 3, according to a second embodiment of the present invention, an FET 1, a transformer 2, a rectifier diode 3,
4, in the switching power supply having the choke coil 5 and the output capacitor 6, a value obtained by dividing the voltage between the drain and source of the FET 1 by the resistors 9 and 10 is input to one of the input terminals of the peak rectifier circuit 7, and The source side is connected to the other input terminal of the peak rectifier circuit 7, and the output of the peak rectifier circuit 7 is connected to one input of the comparator 8. On the other hand, a value obtained by dividing the input voltage V IN by the resistors 11 and 12 and the + input of the comparator 8 are connected.
【００１９】コンパレータ８では、入力電圧ＶINを抵抗
１１と抵抗１２で分圧した値と、ＦＥＴ１のドレイン−
ソース電圧を抵抗９と抵抗１０で分圧したピーク値を比
較し、前者の値が後者のピーク値に対し大きいか等しい
時に出力を故障を示すアラームとする。In the comparator 8, the value obtained by dividing the input voltage V IN by the resistors 11 and 12 and the drain voltage of the FET 1
The peak values obtained by dividing the source voltage by the resistors 9 and 10 are compared, and when the former value is greater than or equal to the latter peak value, the output is set as an alarm indicating a failure.
【００２０】本実施の態様によれば入力電圧ＶINが大き
いときにもコンパレータ８の入力電圧を小さくし、耐電
圧能力の小さなコンパレータを用いるようにできる。According to this embodiment, the input voltage of the comparator 8 can be reduced even when the input voltage V IN is large, and a comparator having a small withstand voltage can be used.
【００２１】また、抵抗９，１０による分圧の程度より
比較して抵抗１１，１２による分圧の程度を大きくする
ことにより、入力電圧ＶINの変動や温度変化による抵抗
値の変化等によるピーク整流回路７の出力のばらつきに
よる誤動作によるアラームの出力を防止するようにする
こともできる。また、ＦＥＴ１のドレイン−ソース電圧
は分圧せずにコンパレータ８に入力し、入力電圧ＶINの
みを分圧してコンパレータ８に入力するようにしても上
述のような誤動作によるアラームの出力を防止するよう
にもできる。Further, by increasing the degree of voltage division by the resistors 11 and 12 as compared with the degree of voltage division by the resistors 9 and 10, a peak due to a change in the input voltage V IN or a change in the resistance value due to a temperature change or the like is obtained. It is also possible to prevent an alarm output due to a malfunction due to a variation in the output of the rectifier circuit 7. Further, even if the drain-source voltage of the FET 1 is inputted to the comparator 8 without dividing, and only the input voltage V IN is divided and inputted to the comparator 8, the alarm output due to the above-mentioned malfunction is prevented. You can do it.
【００２２】さらに、図３のようにピーク整流回路７の
入力側に抵抗９，１０による分圧回路を設ける代わりに
ピーク整流回路７の出力側に分圧回路を設けてＦＥＴ１
のドレイン−ソース電圧のピーク値を分圧するようにし
ても本発明は実施できる。Further, as shown in FIG. 3, instead of providing a voltage dividing circuit by the resistors 9 and 10 on the input side of the peak rectifying circuit 7, a voltage dividing circuit is provided on the output side of the peak rectifying circuit 7 so that the FET 1
The present invention can be implemented by dividing the peak value of the drain-source voltage.
【００２３】[0023]
【発明の効果】常に内部回路電流を流す為のダミー抵抗
を設けなくても軽負荷時に不足電流によりアラームを誤
検出しないで、無負荷時にもスイッチング電源回路の動
作が正常か故障か正確に判断が可能である。According to the present invention, an alarm is not erroneously detected due to an insufficient current at a light load even if a dummy resistor for constantly flowing an internal circuit current is not provided. Is possible.
【００２４】その理由は、ＦＥＴのドレイシ−ソース電
圧等のスイッチング素子の両端子間の電圧のピーク値と
入力電圧値とを比較することにより、負荷の有無に関わ
らずスイッチング電源回路の動作が正常か故障かを判断
することができるからである。The reason is that, by comparing the peak value of the voltage between both terminals of the switching element, such as the drain-source voltage of the FET, and the input voltage value, the operation of the switching power supply circuit is normal regardless of the presence or absence of the load. This is because it is possible to determine whether the failure has occurred.
【図１】本発明の第１の実施の形態の電源故障検出回路
の回路図である。FIG. 1 is a circuit diagram of a power failure detection circuit according to a first embodiment of the present invention.
【図２】図１の中のＦＥＴ１のドレンシ−ソース電圧Ｖ
DSの波形図である。 FIG. 2 shows a drain-source voltage V of FET1 in FIG.
It is a waveform diagram of DS .
【図３】本発明の第２の実施形態の電源故障検出回路の
回路図である。FIG. 3 is a circuit diagram of a power supply failure detection circuit according to a second embodiment of the present invention.
【図４】従来の技術を示す回路図である。FIG. 4 is a circuit diagram showing a conventional technique.
１ ＦＥＴ ２ トランス ３ 整流ダイオード ４ 整流ダイオード ５ チョークコイル ６ 出力コンデンサ ７ ピーク整流回路 ８ コンパレータ ９，１０，１１，１２ 抵抗 １３ ダミー抵抗 １４ 基準電圧電源 DESCRIPTION OF SYMBOLS 1 FET 2 Transformer 3 Rectifier diode 4 Rectifier diode 5 Choke coil 6 Output capacitor 7 Peak rectifier circuit 8 Comparator 9, 10, 11, 12 Resistance 13 Dummy resistance 14 Reference voltage power supply
Claims (4)
的に断続させてトランスの一次側に印加し前記トランス
の二次側から出力電圧を得る電源回路の故障を検出する
回路において、 前記スイッチング素子の両端子間の電圧のピーク値を出
力するピーク整流回路と、前記入力電圧が前記ピーク値
を越えた時に故障を示すアラームを出力するコンパレー
タとを含むことを特徴とする電源故障検出回路。1. A circuit for detecting a failure of a power supply circuit which periodically applies an input voltage to a primary side of a transformer by applying an input voltage to a primary side of a transformer and obtains an output voltage from a secondary side of the transformer, A power supply failure detection circuit, comprising: a peak rectifier circuit that outputs a peak value of a voltage between terminals, and a comparator that outputs an alarm indicating a failure when the input voltage exceeds the peak value.
的に断続させてトランスの一次側に印加し前記トランス
の二次側から出力電源を得る電源回路の故障を検出する
回路において、 前記入力電圧を分圧する分圧回路と、前記スイッチング
素子の両端子間の電圧のピーク値を出力するピーク整流
回路と、前記分圧回路により前記入力電圧を分圧した分
圧電圧が前記ピーク値を越えた時に故障を示すアラーム
を出力するコンパレータとを含むことを特徴とするで電
圧故障検出回路。2. A circuit for detecting a failure in a power supply circuit that periodically applies and interrupts an input voltage by a switching element and applies the input voltage to a primary side of a transformer to obtain output power from a secondary side of the transformer. A voltage divider circuit, a peak rectifier circuit that outputs a peak value of a voltage between both terminals of the switching element, and a failure when a divided voltage obtained by dividing the input voltage by the voltage divider circuit exceeds the peak value. And a comparator for outputting an alarm indicating the voltage failure.
的に断続させてトランスの一次側に印加し前記トランス
の二次側から出力電圧を得る電源回路の故障を検出する
回路において、 前記入力電圧を分圧する分圧回路と、前記スイッチング
素子の両端子間の電圧を分圧したものの分圧ピーク値を
出力する分圧ピーク整流回路と、前記分圧回路により前
記入力電圧を分圧した分圧電圧が前記分圧ピーク値を越
えた時に故障を示すアラームを出力するコンパレータと
を含むことを特徴とする電源故障検出回路。3. A circuit for detecting a failure in a power supply circuit that periodically applies and interrupts an input voltage by a switching element and applies the input voltage to a primary side of a transformer to obtain an output voltage from a secondary side of the transformer. A voltage dividing circuit that divides the input voltage by the voltage dividing circuit, a voltage dividing peak rectifying circuit that outputs a divided voltage peak value of a voltage obtained by dividing the voltage between both terminals of the switching element, and a divided voltage that is obtained by dividing the input voltage by the voltage dividing circuit. And a comparator for outputting an alarm indicating a failure when the partial pressure peak value is exceeded.
スイッチング素子の両端子側の電圧は前記ＦＥＴのドレ
イン−ソース電圧であることを特徴とする請求項１、２
または３記載の電源故障検出回路。4. The FET according to claim 1, wherein the switching element is an FET, and a voltage between both terminals of the switching element is a drain-source voltage of the FET.
Or the power supply failure detection circuit according to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9151102A JP2972653B2 (en) | 1997-06-09 | 1997-06-09 | Power failure detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9151102A JP2972653B2 (en) | 1997-06-09 | 1997-06-09 | Power failure detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10341570A JPH10341570A (en) | 1998-12-22 |
| JP2972653B2 true JP2972653B2 (en) | 1999-11-08 |
Family
ID=15511396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9151102A Expired - Fee Related JP2972653B2 (en) | 1997-06-09 | 1997-06-09 | Power failure detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2972653B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001268899A (en) * | 2000-03-17 | 2001-09-28 | Fujitsu Ltd | Power source controller, power source circuit and method for controlling power source as well as electronic equipment |
| CN102338823B (en) * | 2010-07-27 | 2015-08-26 | 深圳长城开发科技股份有限公司 | The power failure detection method of electric meter system and circuit |
| DE102011103409A1 (en) * | 2011-06-06 | 2012-12-06 | Tridonic Gmbh & Co. Kg | Method for heating a filament of a luminous means and corresponding heating circuit |
| CN103941216B (en) * | 2014-05-19 | 2016-06-08 | 国家电网公司 | Voltage transformer scene Automatic Check-out And Readiness Equipment |
| KR102040888B1 (en) * | 2017-06-27 | 2019-11-06 | 국민대학교 산학협력단 | High voltage power supply having single switch and control circuit device for the same |
| CN116400123B (en) * | 2023-06-07 | 2023-09-08 | 捷蒽迪电子科技(上海)有限公司 | Primary side input voltage detection circuit |
-
1997
- 1997-06-09 JP JP9151102A patent/JP2972653B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10341570A (en) | 1998-12-22 |
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