JP2965638B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2965638B2 JP2965638B2 JP21460990A JP21460990A JP2965638B2 JP 2965638 B2 JP2965638 B2 JP 2965638B2 JP 21460990 A JP21460990 A JP 21460990A JP 21460990 A JP21460990 A JP 21460990A JP 2965638 B2 JP2965638 B2 JP 2965638B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric film
- upper electrode
- semiconductor device
- mim capacitor
- lower electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） この発明は、化合物半導体を用いた特にモノリシック
型マイクロ波集積回路からなる半導体装置に関する。The present invention relates to a semiconductor device using a compound semiconductor, particularly, a monolithic microwave integrated circuit.
（従来の技術） GaAsFETを能動素子とするモノリシック型マイクロ波
集積回路（MMIC）は、ディスクリートのFET素子を用い
るハイブリッドICに比べ、小形化が可能なこと、量産に
よる低価格化が見込めることなどの理由により近年精力
的に開発が進められていると同時に、特性仕様の多様化
も求められている。しかしながら、要求される仕様が異
なっても、MMICの素子構成が同じ場合が多い。(Prior art) Monolithic microwave integrated circuits (MMICs) that use GaAsFETs as active elements can be made smaller and more cost-effective due to mass production compared to hybrid ICs that use discrete FET elements. For the reason, development has been energetically advanced in recent years, and diversification of characteristic specifications is also required. However, even if the required specifications are different, the element configuration of the MMIC is often the same.
例えば、広帯域増幅用MMICにおいては素子構成が同じ
でも、内部に組み込まれるFETの電流値、動作電圧、利
得、帯域、及び効率などの異なる仕様を要求される場合
が多い。そこで、この仕様を満足するためには、MMICを
構成するFET、容量、抵抗等の半導体素子個々の特性の
一部を変更する必要が出てくる。For example, in a broadband amplification MMIC, different specifications such as a current value, an operating voltage, a gain, a band, and an efficiency of an FET incorporated therein are often required even if the element configuration is the same. Therefore, in order to satisfy this specification, it is necessary to change a part of the characteristics of the individual semiconductor elements such as the FET, the capacitance, the resistance, and the like that constitute the MMIC.
これに関し、まず、FETの電流値や抵抗値は動作層や
抵抗層を形成する際のイオン注入条件を変更することに
よって、所望の特性を得ることができる。In this regard, first, desired characteristics of the current value and the resistance value of the FET can be obtained by changing the ion implantation conditions when forming the operation layer and the resistance layer.
しかし、容量値の変更に際しては、次に例示する問題
点がある。However, when changing the capacitance value, there are the following problems.
第４図に、容量を実現する方法として一般にMMICで用
いられているMIMキャパシタの構造の従来例を斜視図で
示す。第４図に示すMIMキャパシタは、GaAs基板101の上
面に形成された下部電極102と、この下部電極102上を被
覆し堆積された誘電体膜103と、この誘電体膜103上に形
成された上部電極104から構成されている。なお、上記
上部電極104は下部電極102とは非接触にGaAs基板101上
面に延在された引出し部114を備えた構造になってい
る。FIG. 4 is a perspective view showing a conventional example of the structure of a MIM capacitor generally used in an MMIC as a method of realizing a capacitance. The MIM capacitor shown in FIG. 4 has a lower electrode 102 formed on an upper surface of a GaAs substrate 101, a dielectric film 103 covering and depositing the lower electrode 102, and a MIM capacitor formed on the dielectric film 103. It is composed of an upper electrode 104. The upper electrode 104 has a structure provided with a lead-out portion 114 extending on the upper surface of the GaAs substrate 101 without contact with the lower electrode 102.
（発明が解決しようとする課題） 上記構造によると、例えばMMICの一部のMIMキャパシ
タの容量値の変更は、該誘電体膜103の膜厚や材質の変
更を行うことにより可能であるが、そうすると、MMIC内
すべてのMIMキャパシタの容量値が変化してしまうとい
う欠点がある。更に、一般に、誘電体膜はFETの保護膜
や電極間の層間絶縁膜として同時に利用している場合が
多く、その場合、他のFETの容量値までもが設計値とず
れてしまうという欠点がある。(Problems to be Solved by the Invention) According to the above structure, for example, the capacitance value of some MIM capacitors of the MMIC can be changed by changing the film thickness or material of the dielectric film 103. Then, there is a disadvantage that the capacitance values of all the MIM capacitors in the MMIC change. Further, in general, the dielectric film is often used simultaneously as a protective film of the FET and an interlayer insulating film between the electrodes, and in this case, there is a disadvantage that even the capacitance values of other FETs are different from the design values. is there.
以上により、誘電体膜の膜厚や材質の変更を行うこと
では、MMIC内の一部のMIMキャパシタのみの特性の変更
を行うことは困難であった。As described above, it is difficult to change the characteristics of only some of the MIM capacitors in the MMIC by changing the thickness or the material of the dielectric film.
また、トリミングによる容量値の調整も行えなかった
ために、容量に関し所望の特性を実現するためには、仕
様毎にマスクを作りかえなければならないという欠点が
あった。In addition, since the capacitance value could not be adjusted by trimming, there was a drawback that a mask had to be recreated for each specification in order to achieve desired characteristics regarding the capacitance.
本発明は上記の欠点を除去するものであり、MMICを構
成する個々のMIMキャパシタの容量値の補正が可能な構
造の半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device having a structure capable of correcting capacitance values of individual MIM capacitors constituting an MMIC.
（課題を解決するための手段） 本発明に係る半導体装置は、相互の間に誘電体膜を介
した上部電極および下部電極が半導体基板に取付けされ
てなるMIMキャパシタを備えた半導体装置において、MIM
キャパシタはその上部電極が半導体基板に取付けされた
引出し部と下部電極上の誘電体膜上に空気層を介した分
岐部とを備え、該分岐部は誘電体膜に接触可能に形成さ
れて該MIMキャパシタを所望の電気容量にすることを特
徴とする。(Means for Solving the Problems) A semiconductor device according to the present invention includes a MIM capacitor including an MIM capacitor having an upper electrode and a lower electrode attached to a semiconductor substrate with a dielectric film interposed therebetween.
The capacitor has a lead portion whose upper electrode is attached to the semiconductor substrate and a branch portion via an air layer on the dielectric film on the lower electrode, and the branch portion is formed so as to be able to contact the dielectric film. It is characterized in that the MIM capacitor has a desired capacitance.
（作 用） 本発明に係る半導体装置は上記構造上の特徴、すなわ
ち、分岐された上部電極の内の適当な部分を、仕様に応
じて、直接誘電体膜に接触させることにより、所望の容
量を得ることができる半導体装置を提供する。(Operation) The semiconductor device according to the present invention has the above-mentioned structural feature, that is, a desired capacitance is obtained by directly contacting an appropriate portion of the branched upper electrode with a dielectric film according to specifications. And a semiconductor device capable of obtaining the above.
（実施例） 以下、本発明の実施例について第１図ないし第３図を
参照して説明する。Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
第１図に本発明の一実施例のMIMIキャパシタを斜視図
で示す。FIG. 1 is a perspective view showing a MIMI capacitor according to an embodiment of the present invention.
第２図に示すMIMキャパシタは、GaAs基板11の上面に
形成された下部電極12と、この下部電極12上を被覆し堆
積された誘電体膜13と、前記GaAs基板11に上部電極14が
その引出し部14pで取付けされ、前記誘電体膜13上にこ
れと空気層15（第３図（ｆ））を介して延在し複数に分
岐した上部電極分岐部14a、14b、14c、14dを備え、かつ
この電極分岐部の少くとも一部は、仕様に応じて第１図
に示すように曲げなどの変形を施して誘電体膜13に接触
させ所望の容量を得るように構成されている。なお、第
１図には一部の上部電極分岐部14aが曲げ加工されて形
成された上部電極分岐部14aaが示されている。The MIM capacitor shown in FIG. 2 has a lower electrode 12 formed on the upper surface of a GaAs substrate 11, a dielectric film 13 covering and depositing the lower electrode 12, and an upper electrode 14 on the GaAs substrate 11. An upper electrode branch portion 14a, 14b, 14c, 14d is attached by a lead portion 14p, extends over the dielectric film 13 via the air layer 15 (FIG. 3 (f)), and branches into a plurality. In addition, at least a part of the electrode branch portion is configured to be deformed by bending or the like as shown in FIG. 1 according to the specification and to be brought into contact with the dielectric film 13 to obtain a desired capacitance. FIG. 1 shows an upper electrode branch portion 14aa formed by bending a part of the upper electrode branch portion 14a.
次に第３図（ａ）〜（ｆ）は、この構造を実現する方
法を説明するための工程毎の断面図であり、製造工程は
FETのソース電極形成等の時に使用されるエアブリッジ
形成工程を利用したものである。Next, FIGS. 3 (a) to 3 (f) are cross-sectional views for each step for explaining a method for realizing this structure.
This utilizes an air bridge forming process used when forming a source electrode of a FET or the like.
まず第３図（ａ）に示すように、GaAs基板11の上面
に、例えばTi/Al/Tiを夫々500Å/5000Å/1000Å厚に蒸
着し、リフトオフを施すことにより下部電極12を形成す
る。次に第３図（ｂ）に示すように、誘電体膜13とし
て、プラズマCVD法により、Si3N4膜を2000Å堆積させ、
選択エッチングを施し必要部分以外を除去する。そして
第３図（ｃ）に示すように、エアブリッジ用アンダーレ
ジスト層16を形成し、続いて、配線用電極としてAu層17
を800Å厚に蒸着させる（第３図（ｄ））。First, as shown in FIG. 3A, for example, Ti / Al / Ti is vapor-deposited on the upper surface of the GaAs substrate 11 to a thickness of 500/5000/1000, respectively, and the lower electrode 12 is formed by performing lift-off. Next, as shown in FIG. 3 (b), a Si 3 N 4 film is deposited as a dielectric film 13 by a plasma CVD method to a thickness of 2000 °.
Selective etching is performed to remove portions other than necessary portions. Then, as shown in FIG. 3 (c), an under-resist layer 16 for air bridge is formed.
Is deposited to a thickness of 800 ° (FIG. 3 (d)).
次に上部電極14として、該上部電極を複数個の互いに
導通された部分14a〜14d（上部電極分岐部）に分岐する
ように、フォトレジスト18を用いて該上部電極部のパタ
ーンを形成し、この後、該上部電極の厚さが４μｍにな
るようAuめっきを施す（第３図（ｅ））。そして、該フ
ォトレジスト層18を除去し、ウエハ全面のAu層に対し
て、800Åエッチバックを施し、該アンダーレジスト18
を除去する（第３図（ｆ））ことにより14a〜14dの分離
がはかられ、第２図に示す構造を完成する。Next, as the upper electrode 14, a pattern of the upper electrode portion is formed using a photoresist 18 so as to branch the upper electrode into a plurality of mutually conducting portions 14a to 14d (upper electrode branch portions), Thereafter, Au plating is applied so that the thickness of the upper electrode becomes 4 μm (FIG. 3E). Then, the photoresist layer 18 is removed, and the Au layer on the entire surface of the wafer is etched back by 800 ° to remove the under resist 18.
Is removed (FIG. 3 (f)) to separate the layers 14a to 14d, thereby completing the structure shown in FIG.
上記構造とすることにより、該上部電極の分岐された
部分14a〜14dの内の適当な数個を選択し、例えば、ワイ
ヤボンダの圧着端子を用いて直接誘電体膜に接触させる
ことにより、所望の容量の変更が可能である半導体装置
を提供することができる（第１図参照）。By adopting the above structure, an appropriate number of the branched portions 14a to 14d of the upper electrode is selected and, for example, by directly contacting the dielectric film using a crimp terminal of a wire bonder, a desired one is obtained. A semiconductor device whose capacity can be changed can be provided (see FIG. 1).
また、上記の例における、上部電極の分岐形状は一例
であり、これに限定されない。Further, the branch shape of the upper electrode in the above example is an example, and the present invention is not limited to this.
以上述べたように本発明によれば、誘電体膜における
誘電率や膜厚を変更すること無く、MIMキャパシタの容
量値を個々に変更できる。これにより、他の構成要素に
影響を及ぼすことなく同一マスクにより、基本構造を同
じにして、少量品種でも多種の仕様要求にきめ細かに対
応できるMMICの製造が可能になった。As described above, according to the present invention, the capacitance values of the MIM capacitors can be individually changed without changing the dielectric constant or the film thickness of the dielectric film. As a result, it has become possible to manufacture an MMIC that can respond to a variety of specification requirements even in a small number of products with the same basic structure using the same mask without affecting other components.
第１図は本発明の一実施例のMIMキャパシタを示す斜視
図、第２図は本発明の一実施例を説明するためのMIMキ
ャパシタの斜視図、第３図（ａ）〜（ｆ）は本発明のMI
Mキャパシタの製造を説明するための工程毎の断面図、
第４図は従来例のMIMキャパシタの斜視図である。 12……下部電極、13……誘電体膜、14……上部電極、 14aa,14b〜ｄ……上部電極分岐部、 15……（上部電極分岐部−誘電体膜間の）空気層。FIG. 1 is a perspective view showing an MIM capacitor according to one embodiment of the present invention, FIG. 2 is a perspective view of the MIM capacitor for explaining one embodiment of the present invention, and FIGS. MI of the present invention
Sectional view for each process for explaining the manufacture of the M capacitor,
FIG. 4 is a perspective view of a conventional MIM capacitor. 12 ... lower electrode, 13 ... dielectric film, 14 ... upper electrode, 14 aa, 14 b-d ... upper electrode branch, 15 ... air layer (between upper electrode branch and dielectric film).
Claims (1)
び下部電極が半導体基板に取付けされてなるMIMキャパ
シタを備えた半導体装置において、MIMキャパシタはそ
の上部電極が半導体基板に取付けされた引出し部と下部
電極上の誘電体膜上に空気層を介した分岐部とを備え、
該分岐部は誘電体膜に接触可能に形成されて該MIMキャ
パシタを所望の電気容量にすることを特徴とする半導体
装置。1. A semiconductor device having an MIM capacitor having an upper electrode and a lower electrode mounted on a semiconductor substrate with a dielectric film interposed therebetween, wherein the MIM capacitor has the upper electrode mounted on the semiconductor substrate. It has a lead portion and a branch portion via an air layer on the dielectric film on the lower electrode,
The semiconductor device, wherein the branch portion is formed so as to be in contact with a dielectric film to make the MIM capacitor have a desired capacitance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21460990A JP2965638B2 (en) | 1990-08-14 | 1990-08-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21460990A JP2965638B2 (en) | 1990-08-14 | 1990-08-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0496359A JPH0496359A (en) | 1992-03-27 |
| JP2965638B2 true JP2965638B2 (en) | 1999-10-18 |
Family
ID=16658554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21460990A Expired - Lifetime JP2965638B2 (en) | 1990-08-14 | 1990-08-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2965638B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6880134B2 (en) | 2003-04-09 | 2005-04-12 | Freescale Semiconductor, Inc. | Method for improving capacitor noise and mismatch constraints in a semiconductor device |
-
1990
- 1990-08-14 JP JP21460990A patent/JP2965638B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0496359A (en) | 1992-03-27 |
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