JP2963012B2 - Superconducting transistor - Google Patents
Superconducting transistorInfo
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- JP2963012B2 JP2963012B2 JP6229305A JP22930594A JP2963012B2 JP 2963012 B2 JP2963012 B2 JP 2963012B2 JP 6229305 A JP6229305 A JP 6229305A JP 22930594 A JP22930594 A JP 22930594A JP 2963012 B2 JP2963012 B2 JP 2963012B2
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- substrate
- superconductor
- region
- insulating layer
- protrusion
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Description
【０００１】[0001]
【産業上の利用分野】この発明は、異方性を有する酸化
物超電導体を用いた超電導トランジスタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting transistor using an oxide superconductor having anisotropy.
【０００２】[0002]
【従来の技術】転移温度Ｔｃの高いビスマス系酸化物超
電導体、イットリウム系酸化物超電導体、タリウム系酸
化物超電導体等を用いた酸化物超電導トランジスタにお
いては、一定の動作電圧を有し、回路動作の安定性に優
れたトンネル接合が用いられる。このトンネル接合は、
ＳＩＳ又はＳＩＮ（ここで、Ｓは超電導体層、Ｉは絶縁
層、Ｎは常伝導体層）からなる積層構造となっている。2. Description of the Related Art An oxide superconducting transistor using a bismuth-based oxide superconductor, a yttrium-based oxide superconductor, a thallium-based oxide superconductor or the like having a high transition temperature Tc has a certain operating voltage. A tunnel junction having excellent operation stability is used. This tunnel junction
It has a laminated structure composed of SIS or SIN (here, S is a superconductor layer, I is an insulating layer, and N is a normal conductor layer).
【０００３】酸化物超電導体の中で、ＢｉＳｒＣａＣｕ
酸化物（以下、ＢＳＣＣＯと略記する。）、ＹＢａＣｕ
酸化物（以下、ＹＢＣＯと略記する。）やＴｌＢａＣａ
Ｃｕ酸化物（以下、ＴＢＣＣＯと略記する。）組成の超
電導体は、ｃ軸或いはａ（又はｂ）軸に層状の積層構造
からなる異方性特性を有する。例えば、ＢＳＣＣＯにお
いては、ｃ軸方向に、ＢｉＯ、ＳｉＯ、Ｃｕ−ＯとＣａ
の積層構造をなしており、各層の中でＣｕ−Ｏ層が超電
導特性を備える。すなわち、ＢＳＣＣＯ膜はＮ／Ｓ／Ｓ
／Ｎの積層構造をとる。[0003] Among oxide superconductors, BiSrCaCu
Oxide (hereinafter abbreviated as BSCCO), YBaCu
Oxide (hereinafter abbreviated as YBCO) or TlBaCa
A superconductor having a composition of Cu oxide (hereinafter, abbreviated as TBCCO) has anisotropic characteristics having a layered laminated structure on the c-axis or a (or b) axis. For example, in BSCCO, BiO, SiO, Cu-O and Ca
And a Cu—O layer among the layers has superconducting properties. That is, the BSCCO film is N / S / S
/ N.
【０００４】従来のトンネル接合を用いた超電導トラン
ジスタは、図５に示すように、Ｎｂを０．０２〜０．０
５ｗｔ％ドープしたＳｒＴｉＯ3からなる半導体基板１
０上にＢＳＣＣＯ、ＹＢＣＯやＴＢＣＣＯ組成の超電導
体からなるベース領域１１が設けられ、このベース領域
１１上に膜厚２０〜６０ÅのＭｇＯ、ＳｒＴｉＯ3等か
らなる酸化物絶縁層１２を介してＡｕ電極又は超電導体
からなるエミッタ領域１３を設けている。In a conventional superconducting transistor using a tunnel junction, as shown in FIG.
Semiconductor substrate 1 made of SrTiO 3 doped with 5 wt%
A base region 11 made of a superconductor having a composition of BSCCO, YBCO or TBCCO is provided on the base region 11, and an Au electrode is formed on the base region 11 via an oxide insulating layer 12 made of MgO, SrTiO 3 or the like having a thickness of 20 to 60 °. Alternatively, an emitter region 13 made of a superconductor is provided.
【０００５】ところで、トンネル接合を形成する場合に
は、超電導薄膜表面は平坦性が良好である方が好まし
い。上述した異方性を有する超電導体の場合、ａ−ｂ軸
方向に配向した膜より、ｃ軸方向に配向した膜の方が平
坦性は良好である。しかしながら、エネルギーギャップ
では、ｃ軸に配向した膜より、ａ−ｂ軸に配向した膜の
方が大きい。When a tunnel junction is formed, the surface of the superconducting thin film preferably has good flatness. In the case of a superconductor having the above-described anisotropy, a film oriented in the c-axis direction has better flatness than a film oriented in the a-b axis direction. However, in the energy gap, a film oriented in the ab axis is larger than a film oriented in the c axis.
【０００６】従って、従来のトンネル接合を用いた超電
導トランジスタは、トンネル接合の構造上図５に示すよ
うに、ｃ軸方向に積層した超電導体が用いられている。
そして、エミッタ領域からの準粒子の透過率を向上させ
るために、超電導体層、絶縁層の膜厚を小さくしてい
る。Therefore, a conventional superconducting transistor using a tunnel junction uses a superconductor laminated in the c-axis direction as shown in FIG. 5 due to the structure of the tunnel junction.
Then, in order to improve the transmittance of the quasiparticles from the emitter region, the thicknesses of the superconductor layer and the insulating layer are reduced.
【０００７】[0007]
【発明が解決しようとする課題】上述したように、図５
に示した従来のトンネル接合を用いた超電導トランジス
タにおいては、超電導体層、絶縁層をできるだけ薄くす
る必要がある。しかしながら、超電導体層、絶縁層を薄
くすると超電導層、絶縁層にピンホールが発生し、エミ
ッタとベース領域或いはエミッタとコレクタ領域との間
に短絡が生じ、リーク電流が発生し、理想的な電流・電
圧特性が得られないという問題があった。As described above, FIG.
In the conventional superconducting transistor using a tunnel junction shown in (1), it is necessary to make the superconductor layer and the insulating layer as thin as possible. However, when the superconductor layer and the insulating layer are thinned, pinholes are generated in the superconducting layer and the insulating layer, a short circuit occurs between the emitter and the base region or between the emitter and the collector region, and a leak current is generated. -There was a problem that voltage characteristics could not be obtained.
【０００８】この発明は、上述した従来の問題点を解決
するためになされたものにして、リーク電流を抑制する
と共に、準粒子の透過率を向上させトランジスタ特性を
向上させることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has as its object to suppress leakage current, improve the transmittance of quasiparticles, and improve the transistor characteristics.
【０００９】[0009]
【課題を解決するための手段】この発明の超電導トラン
ジスタは、表面に凸部が形成されたＳｒＴｉＯ3基板
と、前記凸部の上面部を除いて凸部の側面部及び基板表
面に所定量のＮｂをドープすることにより形成されたコ
レクタ領域と、前記凸部の上面部に一部が延在し且つ上
面部上に結晶面が露出するように基板表面上に設けられ
た異方性を有する酸化物超電導体からなるベース領域
と、上記凸部の上面部及び少なくともベース領域の結晶
面を被覆するように設けられた絶縁層と、この絶縁層を
介して設けられた超電導体又は常伝導体からなるエミッ
タ領域と、を備えてなる。A superconducting transistor according to the present invention comprises an SrTiO 3 substrate having a convex portion formed on the surface thereof, and a predetermined amount of the SrTiO 3 substrate formed on the side surface portion of the convex portion and the substrate surface except for the upper surface portion of the convex portion. A collector region formed by doping with Nb, and anisotropy provided on the substrate surface such that a part thereof extends to the upper surface of the protrusion and a crystal plane is exposed on the upper surface. A base region made of an oxide superconductor, an insulating layer provided so as to cover an upper surface portion of the convex portion and at least a crystal plane of the base region, and a superconductor or a normal conductor provided through the insulating layer. And an emitter region comprising:
【００１０】[0010]
【作用】ＳｒＴｉＯ3基板に設けた凸部の上面部を除い
て凸部の側面部及び基板表面に所定量のＮｂをドープす
ることでコレクタ領域を形成しているので、全体の膜厚
が薄くなる凸部の上面部は絶縁体であるＳｒＴｉＯ3基
板のままであり、エミッタ領域、コレクタ領域へのダイ
レクトのリーク電流が軽減できる。The collector region is formed by doping a predetermined amount of Nb on the side surface of the protrusion and the substrate surface except for the upper surface of the protrusion provided on the SrTiO 3 substrate. The upper surface of the convex portion remains the SrTiO 3 substrate, which is an insulator, so that direct leakage current to the emitter region and the collector region can be reduced.
【００１１】また、凸部の側面部の全域でエミッタとベ
ース、ベースとコレクタの接合が形成されるので、異方
性超電導体のａ−ｂ軸方向の輸送特性が利用でき、準粒
子の透過率が向上し、トランジスタ特性を向上させるこ
とができる。In addition, since the junction between the emitter and the base and the junction between the base and the collector are formed over the entire area of the side surface of the projection, the transport characteristics of the anisotropic superconductor in the a-b axis direction can be utilized, and the transmission of the quasiparticles can be achieved. Thus, the transistor characteristics can be improved.
【００１２】[0012]
【実施例】以下この発明の一実施例を図面を参照して説
明する。図１は、この発明に係る超電導トランジスタを
示す模式的断面図である。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view showing a superconducting transistor according to the present invention.
【００１３】この図１に示すように、ＳｒＴｉＯ3（以
下、ＳＴＯと略記する）基板１の表面部には、凸部２が
イオンミリング又は収束性イオンビーム法などにより形
成されている。この凸部２は例えば、円柱状に形成され
ている。As shown in FIG. 1, a projection 2 is formed on the surface of a SrTiO 3 (hereinafter abbreviated as STO) substrate 1 by ion milling or a convergent ion beam method. The protrusion 2 is formed, for example, in a columnar shape.
【００１４】凸部２の上面部２ａを除いて凸部２の側面
部及び基板１表面には、Ｎｂを０．０２〜０．０５ｗｔ
％選択的にドープすることによりＳＴＯを半導体化させ
たコレクタ領域４が形成される。Except for the upper surface 2a of the protrusion 2, the side surface of the protrusion 2 and the surface of the substrate 1 are coated with 0.02 to 0.05 wt.
The collector region 4 in which the STO is converted into a semiconductor is formed by selectively doping%.
【００１５】そして、凸部２の上面部２ａに一部が延在
し且つ上面部２ａ上に結晶面（へき界面）が露出するよ
うに、ＢＳＣＣＯ、ＹＢＣＯやＴＢＣＣＯ組成の異方性
を有する超電導体からなるベース領域４が基板１表面上
に設けられている。A superconducting material having BSCCO, YBCO or TBCCO composition anisotropy so that a part thereof extends to the upper surface 2a of the convex portion 2 and a crystal plane (a cleavage interface) is exposed on the upper surface 2a. A base region 4 made of a body is provided on the surface of the substrate 1.
【００１６】凸部２の上面部２ａとベース領域４の結晶
面を含めベース領域４の上面に膜厚は１０〜３０Å程度
のＭｇＯ、ＳｒＴｉＯ3からなる絶縁層５が設けられ、
この絶縁層５を介して超電導体又はＡｕなどの金属から
なるエミッタ領域６が設けられている。On the upper surface of the base region 4 including the upper surface 2a of the convex portion 2 and the crystal plane of the base region 4, an insulating layer 5 made of MgO or SrTiO 3 having a thickness of about 10 to 30 ° is provided.
An emitter region 6 made of a metal such as a superconductor or Au is provided via the insulating layer 5.
【００１７】ところで、上記凸部２の高さをｄ、ベース
領域４の膜厚をｔとすると、エミッタ領域６からコレク
タ領域３に電流が流れるためには、ｔ＞ｄになるように
凸部２の高さ及びベース領域３の膜厚を調整する必要が
ある。すなわち、凸部２の高さよりベース領域３の膜厚
を厚くしている。更に表面及び界面からのダメージを考
慮するとｔ−ｄ、すなわち、凸部２の高さよりベース領
域の膜厚を３００Å以上にする方がよく、このように、
凸部２の高さ及びベース領域３の膜厚が制御されてい
る。この結果、従来の積層タイプに比してベース領域３
の膜厚が厚くなる。When the height of the convex portion 2 is d and the thickness of the base region 4 is t, a current flows from the emitter region 6 to the collector region 3 so that t> d. 2 and the thickness of the base region 3 need to be adjusted. That is, the film thickness of the base region 3 is larger than the height of the convex portion 2. Further, considering the damage from the surface and the interface, it is better to set the thickness of the base region to 300 ° or more than t−d, that is, the height of the convex portion 2.
The height of the protrusion 2 and the thickness of the base region 3 are controlled. As a result, as compared with the conventional lamination type, the base region 3
Becomes thicker.
【００１８】このように、この発明の超電導トランジス
タは、凸部２の上面部の下にはＮｂがドープされていな
いので、この部分はＳＴＯの絶縁体のままである。この
上に薄い絶縁層を介してエミッタ領域が設けられている
が、基板の絶縁性のために図１の破断矢印で示すエミッ
タ領域からコレクタ領域へのダイレクトのリーク電流は
軽減される。その結果、図４に示すように、図５に示す
従来の構造の超電導トランジスタに比べこの発明の超電
導トランジスタにおいては、Ｉ−Ｖ特性が改善される。As described above, in the superconducting transistor of the present invention, since Nb is not doped under the upper surface of the projection 2, this portion remains an STO insulator. An emitter region is provided on this via a thin insulating layer. Due to the insulating property of the substrate, a direct leak current from the emitter region to the collector region indicated by a broken arrow in FIG. 1 is reduced. As a result, as shown in FIG. 4, the IV characteristic of the superconducting transistor of the present invention is improved as compared with the conventional superconducting transistor shown in FIG.
【００１９】また、凸部２の側面部の全域でエミッタと
ベース、ベースとコレクタの接合が形成されるので、そ
の接合面積も凸部２の周囲全域となる。そして、図１の
矢印で示す方向に準粒子が輸送され、異方性を有する超
電導体のａ−ｂ軸方向の輸送特性を大きく利用すること
ができ、準粒子の透過率を向上させることができる。す
なわち、図３に示すように、図５に示す従来の構造の超
電導トランジスタに比べこの発明の超電導トランジスタ
においては、ベース接地電流増幅率が２０％以上向上す
る。Further, since the junction between the emitter and the base and between the base and the collector is formed over the entire area of the side surface of the projection 2, the junction area is also the entire area around the projection 2. Then, the quasiparticles are transported in the direction indicated by the arrow in FIG. 1, and the transport characteristics of the superconductor having anisotropy in the ab axis direction can be greatly utilized, and the transmittance of the quasiparticles can be improved. it can. That is, as shown in FIG. 3, in the superconducting transistor of the present invention, the grounded base current amplification factor is improved by 20% or more as compared with the superconducting transistor having the conventional structure shown in FIG.
【００２０】次に、この発明の超電導トランジスタの製
造例を図２に従い説明する。Next, an example of manufacturing the superconducting transistor of the present invention will be described with reference to FIG.
【００２１】まず、図２（ａ）に示すように、ＳＴＯ基
板１の表面部にレジスト６でマスクをして、収束性イオ
ンビーム法により基板１表面を加工して円柱状の凸部２
を形成する。この時の加工条件は、加速電圧５００〜１
０００Ｖ、電流密度０．５〜１ｍＡ／ｃｍ2とした。First, as shown in FIG. 2A, the surface of the STO substrate 1 is masked with a resist 6 and the surface of the substrate 1 is processed by a convergent ion beam method to form a columnar convex portion 2.
To form The processing conditions at this time are as follows:
000 V and the current density was 0.5 to 1 mA / cm 2 .
【００２２】続いて、図２（ｂ）に示すように、凸部２
の上面部２ａにレジスト７でマスクをし、イオン注入法
により凸部２の側面部及び基板１表面に、Ｎｂを０．０
２〜０．０５ｗｔ％選択的にドープし、ＳＴＯを半導体
化させコレクタ領域４を形成する。この時の加工条件
は、加速電圧５００〜１０００Ｖ、電流密度０．５〜１
ｍＡ／ｃｍ2とした。Subsequently, as shown in FIG.
Is masked with a resist 7 on the upper surface 2a of the substrate, and Nb is applied to the side surface of the convex portion 2 and the surface of the substrate 1 by ion implantation.
The collector region 4 is formed by selectively doping 2 to 0.05 wt% to make the STO semiconductor. The processing conditions at this time are: acceleration voltage 500 to 1000 V, current density 0.5 to 1
mA / cm 2 .
【００２３】そして、図２（ｃ）に示すように、凸部２
の上面部２ａの中央部にレジストを残し、スパッタリン
グ法によりがＢＳＣＣＯ、ＹＢＣＯやＴＢＣＣＯ組成の
異方性を有する超電導体薄膜をＭＢＥ法により形成す
る。このとき、超電導体薄膜の膜厚を凸部２の高さより
３００Å以上厚くなるように制御する。そして、リフト
オフにより上面部２ａの超電導薄膜を除去し、凸部２の
上面部２ａに一部が延在し且つ上面部２ａ上に結晶面が
露出するように、ＢＳＣＣＯ、ＹＢＣＯやＴＢＣＣＯ組
成の異方性を有する超電導体からなるベース領域４を基
板１の表面上に形成する。Then, as shown in FIG.
A superconducting thin film having anisotropy of the composition of BSCCO, YBCO or TBCCO is formed by the MBE method by leaving the resist in the central part of the upper surface part 2a. At this time, the thickness of the superconductor thin film is controlled so as to be 300 ° or more greater than the height of the projection 2. Then, the superconducting thin film on the upper surface portion 2a is removed by lift-off, and the difference in BSCCO, YBCO or TBCCO composition is changed so that a part of the superconducting thin film extends on the upper surface portion 2a of the convex portion 2 and a crystal plane is exposed on the upper surface portion 2a. A base region 4 made of an isotropic superconductor is formed on the surface of the substrate 1.
【００２４】その後、図２（ｄ）に示すように、凸部２
の上面部２ａとベース領域４の結晶面を含めベース領域
４の上面にＭｇＯ、ＳｒＴｉＯ3からなる絶縁層５をＭ
ＢＥ法により形成する。この加工条件は基板温度を２０
０℃以下、成膜速度を０．１ｎｍ／ｍｉｎ、真空度を１
０-8Ｔｏｒｒとした。Thereafter, as shown in FIG.
An insulating layer 5 made of MgO or SrTiO 3 is formed on the upper surface of the base region 4 including the upper surface portion 2a of the
It is formed by the BE method. The processing conditions are such that the substrate temperature is 20
0 ° C. or less, deposition rate 0.1 nm / min, vacuum degree 1
It was set to 0 -8 Torr.
【００２５】最後に、この絶縁層５上にＡｕを電子ビー
ム蒸着により設け、エミッタ領域６を形成することによ
り、この発明の超電導トランジスタが形成される。Finally, Au is provided on the insulating layer 5 by electron beam evaporation to form the emitter region 6, whereby the superconducting transistor of the present invention is formed.
【００２６】[0026]
【発明の効果】以上説明したように、この発明は、ＳＴ
Ｏ基板に設けた凸部の上面部を除いて凸部の側面部及び
基板表面に所定量のＮｂをドープすることでコレクタ領
域を形成しているので、エミッタ領域からコレクタ領域
へのダイレクトのリーク電流が軽減できる。As described above, according to the present invention, the ST
Since the collector region is formed by doping a predetermined amount of Nb on the side surface of the protrusion and the surface of the substrate except for the upper surface of the protrusion provided on the O substrate, direct leakage from the emitter region to the collector region is performed. The current can be reduced.
【００２７】また、凸部の側面部の全域でエミッタ領域
とベース領域、ベース領域とコレクタ領域の接合が形成
されるので、異方性を有する超電導体のａ−ｂ軸方向の
輸送特性が大きく利用でき、準粒子の透過率が向上し、
トランジスタ特性を向上させることができる。Further, since the junction of the emitter region and the base region and the junction of the base region and the collector region are formed in the entire region of the side surface of the projection, the superconductor having anisotropy has large transport characteristics in the a-b axis direction. Available, the quasiparticle transmission is improved,
The transistor characteristics can be improved.
【図１】この発明に係る超電導トランジスタを示す模式
的断面図である。FIG. 1 is a schematic sectional view showing a superconducting transistor according to the present invention.
【図２】この発明に係る超電導トランジスタの製造例を
工程別に示す模式的断面図である。FIG. 2 is a schematic cross-sectional view showing an example of manufacturing a superconducting transistor according to the present invention in each step.
【図３】この発明と従来の超電導トランジスタのＩ−Ｖ
特性図である。FIG. 3 shows the IV of the present invention and a conventional superconducting transistor.
It is a characteristic diagram.
【図４】この発明と従来の超電導トランジスタのベース
接地電流増幅率を示す特性図である。FIG. 4 is a characteristic diagram showing a common base current amplification factor of the superconducting transistor of the present invention and a conventional superconducting transistor.
【図５】従来の超電導トランジスタを示す模式的断面図
である。FIG. 5 is a schematic sectional view showing a conventional superconducting transistor.
１ 基板 ２ 凸部 ３ コレクタ領域 ４ ベース領域 ５ 絶縁層 ６ エミッタ領域 DESCRIPTION OF SYMBOLS 1 Substrate 2 Convex part 3 Collector region 4 Base region 5 Insulating layer 6 Emitter region
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 39/00 H01L 39/24 H01L 39/22 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 39/00 H01L 39/24 H01L 39/22
Claims (1)
前記凸部の上面部を除いて凸部の側面部及び基板表面に
所定量の不純物をドープすることにより半導体化させた
コレクタ領域と、前記凸部の上面部に一部が延在し且つ
上面部上に結晶面が露出するように基板表面上に設けら
れた異方性を有する酸化物超電導体からなるベース領域
と、上記凸部の上面部及び少なくともベース領域の結晶
面を被覆するように設けられた絶縁層と、この絶縁層を
介して設けられた超電導体又は常伝導体からなるエミッ
タ領域と、からなる超電導トランジスタ。An insulating substrate having a convex portion formed on a surface thereof;
A collector region formed into a semiconductor by doping a side surface portion of the protrusion and the substrate surface with a predetermined amount of impurities except for an upper surface of the protrusion, and a collector region partially extending on the upper surface of the protrusion and having an upper surface A base region made of an anisotropic oxide superconductor provided on the substrate surface such that a crystal surface is exposed on the portion, and an upper surface portion of the convex portion and at least a crystal surface of the base region are covered. A superconducting transistor comprising: an insulating layer provided; and an emitter region made of a superconductor or a normal conductor provided via the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6229305A JP2963012B2 (en) | 1994-09-26 | 1994-09-26 | Superconducting transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6229305A JP2963012B2 (en) | 1994-09-26 | 1994-09-26 | Superconducting transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0897477A JPH0897477A (en) | 1996-04-12 |
| JP2963012B2 true JP2963012B2 (en) | 1999-10-12 |
Family
ID=16890063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6229305A Expired - Fee Related JP2963012B2 (en) | 1994-09-26 | 1994-09-26 | Superconducting transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2963012B2 (en) |
-
1994
- 1994-09-26 JP JP6229305A patent/JP2963012B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0897477A (en) | 1996-04-12 |
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