JP2924741B2 - Semiconductor device with current detector - Google Patents

Semiconductor device with current detector

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Publication number
JP2924741B2
JP2924741B2 JP7282948A JP28294895A JP2924741B2 JP 2924741 B2 JP2924741 B2 JP 2924741B2 JP 7282948 A JP7282948 A JP 7282948A JP 28294895 A JP28294895 A JP 28294895A JP 2924741 B2 JP2924741 B2 JP 2924741B2
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JP
Japan
Prior art keywords
current
semiconductor device
film
semiconductor
magnetoresistive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7282948A
Other languages
Japanese (ja)
Other versions
JPH09127161A (en
Inventor
裕治 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
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Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7282948A priority Critical patent/JP2924741B2/en
Publication of JPH09127161A publication Critical patent/JPH09127161A/en
Application granted granted Critical
Publication of JP2924741B2 publication Critical patent/JP2924741B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/14—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
    • G01R15/20—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices, i.e. measuring a magnetic field via the interaction between a current and a magnetic field, e.g. magneto resistive or Hall effect devices
    • G01R15/205—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices, i.e. measuring a magnetic field via the interaction between a current and a magnetic field, e.g. magneto resistive or Hall effect devices using magneto-resistance devices, e.g. field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Hall/Mr Elements (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は負荷を電流駆動する
半導体素子と同一ペレット上に形成された電流検出素子
とを有する電流検出器付き半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device with a current detector having a semiconductor element for driving a load with a current and a current detection element formed on the same pellet.

【０００２】[0002]

【従来の技術】負荷を電流駆動する半導体素子に流れる
電流値を検出する電流検出素子の従来例としてホール素
子を利用した電流検出器付き半導体装置が知られている
が、図５にそのブロック図を示す。バイポーラトランジ
スタまたはＭＯＳＦＥＴ２１などから成り負荷を電流駆
動する半導体素子は負荷などに接続される出力端子ＯＵ
Ｔおよび半導体素子の基準電位となる接地端子ＧＮＤに
接続され、出力端子ＯＵＴおよび接地端子ＧＮＤの間の
電流路３６近傍にホール素子２６が設けられている。半
導体装置２５の入力端子ＩＮには定電流回路２４と制御
回路２２が接続され、定電流回路２４からはホール素子
２６に定電流が供給されている。電流路３６に流れる電
流に従いホール素子２６にて発生する電圧は制御回路２
２に入力するよう接続され、制御回路２２はＭＯＳＦＥ
Ｔ２１の入力信号を制御する構成になっている。2. Description of the Related Art A semiconductor device with a current detector using a Hall element is known as a conventional example of a current detecting element for detecting a current value flowing in a semiconductor element for driving a load with a current. FIG. Is shown. A semiconductor element composed of a bipolar transistor or a MOSFET 21 for driving a load current is connected to an output terminal OU connected to the load or the like.
The Hall element 26 is provided near the current path 36 between the output terminal OUT and the ground terminal GND, and is connected to T and the ground terminal GND serving as a reference potential of the semiconductor element. A constant current circuit 24 and a control circuit 22 are connected to an input terminal IN of the semiconductor device 25, and a constant current is supplied to the Hall element 26 from the constant current circuit 24. The voltage generated by the Hall element 26 according to the current flowing through the current path 36 is controlled by the control circuit 2
2 and the control circuit 22
It is configured to control the input signal of T21.

【０００３】ホール素子２６近傍のペレット構成につい
ては、特開昭６１−９７５７４号公報にあるが、それに
ついて図６（ａ），（ｂ）に示す。出力端子ＯＵＴと接
地端子ＧＮＤの間の電流路３６を図６に示すようにペレ
ット表面の絶縁膜３５上に数１０μｍ厚のＡｇ層により
Ｃ字状に形成してある。Ｃ字状に形成した電流路３６で
囲まれた領域にはエミッタ電極３３ｂおよびコレクタ電
極３４ｂが形成され、エミッタ電極３３ｂとコレクタ電
極３４ｂを結ぶ線の両側にｎ+ 拡散領域から成る一対の
ホール領域にそれぞれ接続されるホール電極３７−１，
３７−２が形成してある。ここで、コレクタ電極３４ｂ
は定電流回路２４に、エミッタ電極３３ｂは接地端子Ｇ
ＮＤに接続され、一対のホール電極３７−１，３７−２
の他端は制御回路２２に接続されている。The configuration of the pellet in the vicinity of the Hall element 26 is disclosed in Japanese Patent Application Laid-Open No. 61-97574, which is shown in FIGS. 6 (a) and 6 (b). As shown in FIG. 6, a current path 36 between the output terminal OUT and the ground terminal GND is formed in a C-shape by an Ag layer having a thickness of several tens of μm on the insulating film 35 on the surface of the pellet. An emitter electrode 33b and a collector electrode 34b are formed in a region surrounded by the C-shaped current path 36, and a pair of hole regions formed of n + diffusion regions are provided on both sides of a line connecting the emitter electrode 33b and the collector electrode 34b. , The hole electrodes 37-1, which are respectively connected to
37-2 are formed. Here, the collector electrode 34b
Is the constant current circuit 24, and the emitter electrode 33b is the ground terminal G.
ND, and a pair of hole electrodes 37-1, 37-2.
Is connected to the control circuit 22.

【０００４】同一ペレット上のＭＯＳＦＥＴ２１から電
気的に分離された約１０μｍ厚のＮ- 型エピタキシャル
層３１にはＰ型拡散領域から成るベース領域３２ａが形
成され、ベース領域３２ａにはＮ+ 型拡散領域から成る
エミッタ領域３３ａが形成されている。また、Ｎ- 型エ
ピタキシャル層３１にはＮ+ 型拡散領域から成るコレク
タ領域３４ｂも形成されている。A base region 32a composed of a P-type diffusion region is formed in an approximately 10 μm thick N − -type epitaxial layer 31 electrically separated from the MOSFET 21 on the same pellet, and an N + -type diffusion region is formed in the base region 32a. Is formed. The N − type epitaxial layer 31 also has a collector region 34b formed of an N + type diffusion region.

【０００５】この構成の電流検出器付き半導体装置に例
えば数Ａの電流を電流方向３９で電流路３６に流したと
き、Ｃ字状の電流路３６の内側では数１０5 ／４π（Ａ
／ｍ）の磁界が磁界方向３８に発生しており、Ｃ字状の
電流路３６で囲まれた領域のさし渡し寸法を例えば５０
μｍとするとコレクタ領域３４ａからエミッタ領域３３
ａに数ｍＡの定電流を流しているときホール電極間には
数１０ｍＶの電圧が出力される。電流路３６を流れる電
流値に相当するホール電圧は制御回路２２に入力され、
検出した電流値によりＭＯＳＦＥＴ２１の入力電圧を制
御したりＰＷＭ制御を行ったりすることで駆動電流を制
御する。When a current of several A, for example, is passed through the current path 36 in the current direction 39 through the semiconductor device with the current detector having the above-described configuration, a voltage of several 10 5 / 4π (A) is formed inside the C-shaped current path 36.
/ M) is generated in the direction of the magnetic field 38, and the span of the region surrounded by the C-shaped current path 36 is set to, for example, 50
μm, the collector region 34a to the emitter region 33
When a constant current of several mA flows through a, a voltage of several tens mV is output between the Hall electrodes. The Hall voltage corresponding to the current value flowing through the current path 36 is input to the control circuit 22,
The drive current is controlled by controlling the input voltage of the MOSFET 21 or performing PWM control based on the detected current value.

【０００６】[0006]

【発明が解決しようとする課題】図６に示す従来例では
ホール素子のコレクタ領域３４ａからエミッタ領域３３
ａに流れる定電流の方向と一対のホール電極３７−１，
３７−２を結ぶ方向およびホール素子への印加磁界の磁
界方向３８は互いに直交する方向に配置するとき最も効
率よくホール電圧が得られるため、ホール素子をペレッ
ト表面に形成しホール素子の周囲にＣ字状の電流路３６
を形成していた。In the conventional example shown in FIG. 6, the collector region 34a of the Hall element is shifted from the emitter region 33.
a and a pair of hole electrodes 37-1,
Since the Hall voltage can be obtained most efficiently when the direction connecting 37-2 and the magnetic field direction 38 of the magnetic field applied to the Hall element are arranged in directions orthogonal to each other, the Hall element is formed on the surface of the pellet, and C is formed around the Hall element. Current path 36
Had formed.

【０００７】ところが、電流路３６を引き回すことによ
り半導体装置の出力端子ＯＵＴと接地端子ＧＮＤの間の
抵抗を増加させる原因になりオン時にＭＯＳＦＥＴ２１
に発生する抵抗または電圧を低減しても半導体装置全体
として低オン抵抗または低電圧にすることが難しくなる
と同時に発熱による温度の増大も生じる問題があった。
また、駆動電流によるＭＯＳＦＥＴ２１とその周辺の発
熱およびホール素子へ流す定電流などによる発熱により
温度の上昇が生じ、検出すべき電流値をあらわすホール
電圧が不安定になる問題もあった。However, routing the current path 36 causes an increase in the resistance between the output terminal OUT and the ground terminal GND of the semiconductor device.
However, even if the resistance or voltage generated in the semiconductor device is reduced, it is difficult to reduce the on-resistance or the voltage as a whole of the semiconductor device, and at the same time, there is a problem that the temperature is increased by heat generation.
In addition, there is also a problem that the temperature rises due to the heat generated by the MOSFET 21 and its surroundings due to the drive current and the heat generated by the constant current flowing to the Hall element, and the Hall voltage representing the current value to be detected becomes unstable.

【０００８】従って本発明の第１の目的は温度上昇を殆
ど伴わずに集積できる電流検出素子を有する電流検出器
付き半導体装置を提供することにある。更に本発明の第
２の目的は電流検出機能の温度依存性の少ない電流検出
器付き半導体装置を提供することにある。Accordingly, a first object of the present invention is to provide a semiconductor device with a current detector having a current detection element that can be integrated with almost no rise in temperature. A second object of the present invention is to provide a semiconductor device with a current detector having a small temperature dependency of a current detection function.

【０００９】[0009]

【課題を解決するための手段】本発明の電流検出器付き
半導体装置は、負荷を電流駆動する半導体素子及び前記
半導体素子に流れる駆動電流を検出する電流検出素子が
同一半導体ペレットに集積されてなる電流検出器付き半
導体装置において、磁性体膜及び導電膜の２層膜からな
る磁気抵抗効果素子とこれに定電流を供給する手段とを
有し、前記駆動電流による磁界に依存する抵抗値を有す
る前記磁気抵抗効果素子が前記電流検出素子として前記
半導体素子上に縦積みされているというものである。A semiconductor device with a current detector according to the present invention comprises a semiconductor element for driving a load with a current and a current detection element for detecting a drive current flowing through the semiconductor element, which are integrated on the same semiconductor pellet. In a semiconductor device with a current detector, a two-layer film of a magnetic film and a conductive film is used.
That a magnetoresistive element and means for supplying it to the constant current, the magnetoresistance effect element having a resistance value that depends on the magnetic field due to the drive current is stacked vertically on the semiconductor device as the current detecting element It is that.

【００１０】この場合、半導体素子から駆動電流を取り
出すボンディング線に接続するパッドの近傍に２層膜を
配置することができる。更に、ボンディング線を囲んで
配置された磁気誘導体で形成され一部にギャップを有す
る磁路と、前記ギャップ部に磁気抵抗効果素子を配置す
ることもできる。磁気誘導体としては、Ｎｉ−Ｆｅ膜を
含んでなるものが１例としてあげられる。 In this case, a two-layer film can be arranged near a pad connected to a bonding line for extracting a drive current from the semiconductor element. Furthermore, it is also possible to arrange a magnetic path formed of a magnetic derivative and surrounding the bonding line and having a gap in a part, and a magnetoresistive element in the gap. As a magnetic derivative, a Ni-Fe film is used.
One example is the one comprising.

【００１１】更に又、駆動電流による磁界依存性が互い
に逆極性の一対の磁気抵抗効果素子と、これらの抵抗値
の差を検出する差動増幅器とを設けることもできる。こ
の場合、一対の磁気抵抗効果素子は、磁性体膜と導電膜
の積層順序が互いに逆で、同一方向にそれぞれ定電流を
流すようにすることができる。あるいは、磁性体膜と導
電膜の積層順序が同じで、互いに逆方向にそれぞれ定電
流を流すようにしてもよい。[0011] Furthermore, it a pair of magneto-resistive element field dependence opposite polarities to each other by the drive current, also be provided a differential amplifier for detecting the difference between these resistance values. In this case, the order of lamination of the magnetic film and the conductive film in the pair of magnetoresistive elements is opposite to each other, and a constant current can flow in the same direction. Alternatively, the magnetic material film and the conductive film may be stacked in the same order, and a constant current may flow in opposite directions.

【００１２】半導体素子としては、半導体基板の表面に
接続されるソース電極及び裏面に形成されるドレイン電
極を有する縦型ＩＧＦＥＴを使用することができる。As the semiconductor element, a vertical IGFET having a source electrode connected to the front surface of the semiconductor substrate and a drain electrode formed on the back surface can be used.

【００１３】半導体素子と電流検出素子とが同一半導体
ペレットに縦積みされているので、従来例のように駆動
電流を検出するための電流路を引き回す必要がない。Since the semiconductor element and the current detecting element are vertically stacked on the same semiconductor pellet, there is no need to route a current path for detecting a drive current as in the conventional example.

【００１４】逆極性の一対の磁気抵抗効果素子と差動増
幅器とを用いれば、温度による変化を消去できる。If a pair of magnetoresistive elements having opposite polarities and a differential amplifier are used, a change due to temperature can be eliminated.

【００１５】[0015]

【発明の実施の形態】図１は本発明の第１の実施の形態
の構成を示すブロック図である。FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

【００１６】本実施の形態は、バイポーラトランジスタ
またはＭＯＳＦＥＴ２１などの半導体素子は負荷などに
接続される出力端子ＯＵＴおよび基準電位となる接地端
子ＧＮＤに接続され、出力端子ＯＵＴおよび接地端子Ｇ
ＮＤの間の電流路３６近傍に一対の磁気抵抗効果素子１
２−１，１２−２が設けられている。入力端子ＩＮには
一対の定電流回路２４−１，２４−２と制御回路２２が
接続され、一対の定電流回路２４−１，２４−２からは
それぞれの磁気抵抗効果素子１２−１，１２−２に定電
流が供給されている。電流路３６に流れる電流に従い磁
気抵抗効果素子１２−１，１２−２にて発生する電圧は
差動増幅器２３に入力され差動演算された信号が制御回
路２２に入力するよう接続され、制御増幅器２２は負荷
を電流駆動する半導体素子（ＭＯＳＦＥＴ２１）の入力
信号を制御する構成になっている。In this embodiment, a semiconductor element such as a bipolar transistor or MOSFET 21 is connected to an output terminal OUT connected to a load or the like and a ground terminal GND serving as a reference potential.
A pair of magnetoresistive effect elements 1 is provided near the current path 36 between ND.
2-1 and 12-2 are provided. A pair of constant current circuits 24-1 and 24-2 and the control circuit 22 are connected to the input terminal IN, and the pair of constant current circuits 24-1 and 24-2 respectively output the magnetoresistive elements 12-1 and 12-1. -2 is supplied with a constant current. Voltages generated in the magnetoresistive elements 12-1 and 12-2 according to the current flowing through the current path 36 are input to the differential amplifier 23 and connected to input the differentially operated signal to the control circuit 22. Reference numeral 22 denotes a configuration for controlling an input signal of a semiconductor element (MOSFET 21) for driving a load with current.

【００１７】図２（ａ）は磁気抵抗効果素子近傍の半導
体ペレットの平面図、図２（ｂ），（ｃ）はそれぞれ図
２（ａ）のＡ−Ａ線断面図及びＢ−Ｂ線拡大断面図であ
る。Ｎ型シリコン基板（Ｎ+ 型ドレイン領域１，Ｎ型ド
レイン領域２よりなる）に周知の縦型ＩＧＦＥＴ（ＤＭ
ＯＳトランジスタ）が形成されている。すなわち、４は
Ｐ型ベース領域、５はＮ+ 型ソース領域、６はゲート酸
化膜、７はゲート電極、３はフィールド酸化膜、８は層
間絶縁膜、９はソース電極、１７はメッシュ状のゲート
電極７の周囲に接続されるゲートパッドである。ただ
し、図２（ｂ）にはＤＭＯＳトランジスタのセル構造の
概要を示し、セルの寸法は実際のものを示してはいな
い。縦型ＩＧＦＥＴの表面（アルミニウム膜などでなる
ソース電極９の表面）を被覆する酸化シリコン膜１１に
窓を設け、そこに露出したソース電極９にボンディング
線１６がボンディングされている。ボンディング線１６
の他端は接地端子ＧＮＤに接続される。又、ドレイン電
極１０は図示しないリードフレームなどを経由して出力
端子ＯＵＴに接続される。FIG. 2A is a plan view of a semiconductor pellet near the magnetoresistive element, and FIGS. 2B and 2C are cross-sectional views taken along line AA and line BB of FIG. 2A, respectively. It is sectional drawing. A well-known vertical IGFET (DM) is formed on an N-type silicon substrate (consisting of an N + -type drain region 1 and an N-type drain region 2).
OS transistor). That is, 4 is a P-type base region, 5 is an N + -type source region, 6 is a gate oxide film, 7 is a gate electrode, 3 is a field oxide film, 8 is an interlayer insulating film, 9 is a source electrode, and 17 is a mesh-shaped film. The gate pad is connected around the gate electrode 7. However, FIG. 2B shows the outline of the cell structure of the DMOS transistor, and the actual dimensions of the cell are not shown. A window is provided in the silicon oxide film 11 covering the surface of the vertical IGFET (the surface of the source electrode 9 made of an aluminum film or the like), and a bonding wire 16 is bonded to the source electrode 9 exposed there. Bonding wire 16
Is connected to a ground terminal GND. The drain electrode 10 is connected to the output terminal OUT via a lead frame (not shown).

【００１８】磁気抵抗効果素子１２−１，１２−２及び
磁気誘導体１３の配置を図２（ａ），（ｂ）に示し、具
体的構造を図２（ｃ）に示す。この半導体ペレットのボ
ンディング線１６の周囲の絶縁膜（１１）上にＮｉ−Ｆ
ｅ膜を含む磁気誘導体１３がＣ字状に形成され、Ｃ字状
の磁気誘導体１３の切り欠き部（ギャップ）には一対の
磁気抵抗効果素子１２−１，１２−２が形成されてい
る。一対の磁気抵抗効果素子１２−１，１２−２の一端
はソース電極９に接続され、他端は差動増幅器２３に接
続されている。FIGS. 2A and 2B show the arrangement of the magnetoresistive elements 12-1 and 12-2 and the magnetic derivative 13, and FIG. 2C shows a specific structure. Ni-F is formed on the insulating film (11) around the bonding wire 16 of the semiconductor pellet.
A magnetic derivative 13 including an e-film is formed in a C shape, and a pair of magnetoresistive elements 12-1 and 12-2 are formed in a cutout (gap) of the C shape magnetic derivative 13. One end of the pair of magnetoresistive elements 12-1 and 12-2 is connected to the source electrode 9, and the other end is connected to the differential amplifier 23.

【００１９】磁気抵抗効果素子１２−１は０．１５μｍ
厚のＴｉ膜１４ａからなるシャントバイアス膜と０．０
４μｍ厚のＮｉ−Ｆｅ膜（パーマロイ膜）１５ａでなる
磁気抵抗効果膜との幅数μｍのストライプ状の２層膜で
なる。１８は０．１５μｍ厚の酸化シリコン膜でなる。
磁気抵抗効果素子１２−２は、０．０４μｍ厚のＮｉ−
Ｆｅ膜１５ｂでなる磁気抵抗効果膜と０．０１５μｍ膜
のＴｉ膜１４ｂからなるシャントバイアス膜との幅数μ
ｍのストライプ状の２層膜でなる。磁気誘導体１３はＴ
ｉ膜１４ａ／Ｎｉ−Ｆｅ膜１５ａ／酸化シリコン膜１８
／Ｎｉ−Ｆｅ膜１５ｂ／Ｔｉ膜１４ｂの積層構造を有し
ているが、この上に更に酸化シリコン膜を堆積し、Ｎｉ
−Ｆｅ膜を堆積し、パターニングすることによりＮｉ−
Ｆｅ膜の合計厚さを大きくしてもよい。The magnetoresistive element 12-1 has a thickness of 0.15 μm.
A shunt bias film made of a thick Ti film 14a and 0.0
It is a stripe-shaped two-layer film having a width of several μm with a magnetoresistive effect film composed of a Ni—Fe film (permalloy film) 15 a having a thickness of 4 μm. Reference numeral 18 is a silicon oxide film having a thickness of 0.15 μm.
The magnetoresistive element 12-2 is made of a 0.04 μm thick Ni-
A width μ between the magnetoresistive effect film made of the Fe film 15b and the shunt bias film made of the 0.015 μm Ti film 14b.
It is composed of a m-stripe two-layer film. The magnetic derivative 13 is T
i film 14a / Ni-Fe film 15a / silicon oxide film 18
/ Ni-Fe film 15b / Ti film 14b, and a silicon oxide film is further deposited thereon to form a Ni
-Fe film is deposited and patterned to obtain Ni-
The total thickness of the Fe film may be increased.

【００２０】一対の磁気抵抗効果素子１２−１，１２−
２には定電流回路２４−１，２４−２から同一方向に一
定の電流が流れており、シャントバイアス膜１４ａ，１
４ｂを流れる電流が隣接する磁気抵抗効果膜１５ａ，１
５ｂに磁気バイアスを印加する。A pair of magnetoresistive elements 12-1, 12-
2, a constant current flows from the constant current circuits 24-1 and 24-2 in the same direction, and the shunt bias films 14a and 1
4b is applied to adjacent magnetoresistive films 15a, 15a.
A magnetic bias is applied to 5b.

【００２１】磁気抵抗効果素子１２−１，１２−２の磁
気抵抗特性を図３に示す。一対の磁気抵抗効果素子１２
−１，１２−２は磁気抵抗効果膜とシャントバイアス膜
の相対位置が逆のため磁気抵抗効果素子１２−１，１２
−２に数１０ｍＡの電流を流すことにより数１０5 ／４
π（Ａ／ｍ）の互いに逆バイアス磁界の状態４１ａ，４
１ｂがバイアス点となる。ＭＯＳＦＥＴ２１に流れる電
流３９の作る磁界は一対の磁気抵抗効果素子１２−１，
１２−２の両者に同じ磁界方向３８に印加されるため、
一対の磁気抵抗効果素子１２−１，１２−２は動作点４
２ａ，４２ｂのように、片方の抵抗値は減少し他方は増
大する。状態４２ａ，４２ｂの抵抗差による電圧差を差
動増幅器２３で差動演算することによりＭＯＳＦＥＴ２
１を流れる電流値が得られる。例えばＭＯＳＦＥＴ２１
に数Ａの電流３９が流れるとき電流の作る磁界は磁界方
向３８に数１０5 ／４π（Ａ／ｍ）となり、一対の磁気
抵抗効果素子１２−１，１２−２のストライプ方向の長
さが約１００μｍのとき差動演算により数１０ｍＶの出
力電圧が得られる。ＭＯＳＦＥＴ２１を流れる電流値に
従い得られる電圧は制御回路２２に入力することで駆動
電流を制御する。FIG. 3 shows the magnetoresistance characteristics of the magnetoresistance effect elements 12-1 and 12-2. A pair of magnetoresistive elements 12
-1 and 12-2 are magnetoresistive elements 12-1 and 12-2 because the relative positions of the magnetoresistive film and the shunt bias film are opposite.
-2 by applying a current of several tens of mA to several tens of 5
states 41a, 4 of mutually reverse bias magnetic fields of π (A / m)
1b is the bias point. The magnetic field generated by the current 39 flowing through the MOSFET 21 is a pair of magnetoresistive elements 12-1, 12-1,
12-2 are applied in the same magnetic field direction 38,
The pair of magnetoresistive elements 12-1 and 12-2 have an operating point of 4
As in 2a and 42b, one of the resistance values decreases and the other increases. The voltage difference due to the resistance difference between the states 42a and 42b is differentially calculated by the differential amplifier 23, so that the MOSFET 2
The current value flowing through 1 is obtained. For example, MOSFET 21
When a current 39 of several A flows in the magnetic field direction, the magnetic field generated by the current becomes several 10 5 / 4π (A / m) in the magnetic field direction 38, and the length of the pair of magnetoresistive elements 12-1 and 12-2 in the stripe direction is reduced. When it is about 100 μm, an output voltage of several tens mV can be obtained by differential operation. A voltage obtained according to a current value flowing through the MOSFET 21 is input to a control circuit 22 to control a drive current.

【００２２】なお、制御回路２２，差動増幅器２３，定
電流回路２４−１，２４−２は通常のｎＭＯＳＦＥＴな
どで構成され、同一の半導体ペレットに集積されている
ものとする。It is assumed that the control circuit 22, the differential amplifier 23, and the constant current circuits 24-1 and 24-2 are composed of ordinary nMOSFETs and the like, and are integrated on the same semiconductor pellet.

【００２３】縦型ＩＧＦＥＴを形成した半導体ペレット
上に電流検出素子を縦積みして設けるので、従来例のよ
うに電流路を引き回す必要がない分オン抵抗を少なくで
き、その分温度上昇を抑えることが可能となる。又、駆
動電流による磁界依存性が逆極性の一対の磁気抵抗効果
素子と差動増幅器とを用いることにより、検出機能の温
度依存性を少なくできる。Since the current detecting elements are vertically stacked on the semiconductor pellet on which the vertical IGFET is formed, the on-resistance can be reduced because the current path does not need to be routed as in the conventional example, and the temperature rise can be suppressed accordingly. Becomes possible. Further, the temperature dependency of the detection function can be reduced by using a pair of magnetoresistive elements and a differential amplifier whose magnetic field dependence due to the driving current is opposite in polarity.

【００２４】図４（ａ）は本発明の第２の実施の形態を
示す平面図、図４（ｂ）は図４（ａ）のＡ−Ａ線断面図
である。FIG. 4A is a plan view showing a second embodiment of the present invention, and FIG. 4B is a sectional view taken along line AA of FIG. 4A.

【００２５】一対の磁気抵抗効果素子はいずれも磁気抵
抗効果膜（Ｎｉ−Ｆｅ膜１５）とシャント膜（Ｔｉ膜１
４）の積層順序が同一の２層膜でなっているが、電流の
向きが互いに逆になるように形状を工夫してある。第１
の磁気抵抗効果素子は幅広の電極部１９−１１，１９−
１２が幅数μｍの細いストライプ状の検出部１２−１Ａ
の両端に連結され、電極部１９−１２の先端２０−１で
ソース電極９に接続される。第２の磁気抵抗効果素子は
幅広の電極部１９−２１の先端に細いストライプ状の検
出部１２−２Ａが逆平行に連結されている。検出部１２
−２Ａの一端２０−２はソース電極９に接続される。電
極部１９−１１，１９−２１はそれぞれ定電流回路２４
−１，２４−２と差動増幅器２３に接続される。従っ
て、検出部１２−１Ａと１２−２Ａには互いに逆方向に
電流が流れる。電極部１９−１１，１９−１２，１９−
２１は検出部の幅（数μｍ）の１０倍前後の幅にしてお
けば磁界を実効的に検出するのは検出部１２−１Ａ，１
２−２Ａと考えられる。よって一対の磁気抵抗効果素子
の構成は実効的に同じであるが、流れる定電流の方向が
逆になるため互いに逆バイアスの磁界の動作点になる。
なお、磁気誘導体１３ＡはＮｉ−Ｆｅ膜１５，Ｔｉ膜１
４の２層膜で構成されている。Each of the pair of magnetoresistive elements has a magnetoresistive film (Ni—Fe film 15) and a shunt film (Ti film 1).
4) Although the two layers are formed in the same lamination order, the shapes are devised so that the directions of the currents are opposite to each other. First
The magnetoresistive effect element of the first embodiment has wide electrode portions 19-11 and 19-.
Reference numeral 12 denotes a thin stripe-shaped detection unit 12-1A having a width of several μm.
Are connected to the source electrode 9 at the tip 20-1 of the electrode portion 19-12. In the second magnetoresistive element, a thin stripe-shaped detecting portion 12-2A is connected to the tip of a wide electrode portion 19-21 in an anti-parallel manner. Detector 12
-2A is connected to the source electrode 9 at one end 20-2. The electrode portions 19-11 and 19-21 are respectively provided with a constant current circuit 24.
-1, 24-2 and the differential amplifier 23. Therefore, currents flow in the detection units 12-1A and 12-2A in opposite directions. Electrode portions 19-11, 19-12, 19-
If the width of the detection unit 21 is about 10 times the width of the detection unit (several μm), the detection unit 12-1A, 1 can effectively detect the magnetic field.
2-2A. Therefore, although the configuration of the pair of magnetoresistive elements is effectively the same, the directions of the flowing constant currents are opposite, so that the operating points of the magnetic fields are oppositely biased.
The magnetic derivative 13A includes the Ni—Fe film 15, the Ti film 1
4 is formed of a two-layer film.

【００２６】半導体チップ下部の構造は第１の実施の形
態と同じである。本実施の形態は磁気誘導体１３Ａ，一
対の磁気抵抗効果素子をいずれも同じ２層膜で形成でき
るので製造工程が簡単でよい利点がある。The structure below the semiconductor chip is the same as in the first embodiment. In the present embodiment, the magnetic derivative 13A and the pair of magnetoresistive elements can be formed of the same two-layer film, so that there is an advantage that the manufacturing process is simple and good.

【００２７】以上、一対の磁気抵抗効果素子と差動増幅
回路を用いる例について説明したが単一の磁気抵抗効果
素子とバッファ回路を使用しても駆動電流を検出でき
る。ただ、電流検出機能の温度依存性は少なくできな
い。In the above, an example in which a pair of magnetoresistive elements and a differential amplifier circuit are used has been described. However, a drive current can be detected by using a single magnetoresistive element and a buffer circuit. However, the temperature dependency of the current detection function cannot be reduced.

【００２８】又、負荷を駆動する半導体素子として縦型
ＩＧＦＥＴを例にあげて説明したが横型ＩＧＦＥＴを使
用することもでき、バイポーラトランジスタを使用する
こともできる。更にＮチャネルＩＧＦＥＴやＮＰＮトラ
ンジスタばかりでなくＰチャネルＩＧＦＥＴやＰＮＰト
ランジスタを使用することもできる。更に又、電流路で
あるボンディング線の近傍に多数の磁気抵抗効果素子を
並列に配置して磁気誘導体を省略することも可能であ
る。Although a vertical IGFET has been described as an example of a semiconductor element for driving a load, a horizontal IGFET can be used, and a bipolar transistor can also be used. Further, not only N-channel IGFETs and NPN transistors but also P-channel IGFETs and PNP transistors can be used. Furthermore, it is also possible to dispose a large number of magnetoresistive elements in parallel near the bonding line, which is a current path, and omit the magnetic derivative.

【００２９】[0029]

【発明の効果】以上説明したように本発明は、磁性体膜
と導電膜の２層膜でなる磁気抵抗効果素子を、負荷を電
流駆動する半導体素子を形成した半導体ペレット状に縦
積みすることにより、駆動電流の電流路を従来例のよう
に引き回す必要がないので、電流検出素子を設けること
によるオン抵抗の増大などそれによる温度上昇を防止で
きる。又、オン時に発生する電圧が増加しないので、負
荷短絡時のような非常時にも破壊され難い。また互いに
逆極性の一対の電流検出素子と差動増幅器を用いれば、
半導体装置自身の発熱などによる温度の影響を少なくで
き、精度よく電流制御を行うことが可能となるばかりで
なく、安全性の高い１チップの電流検出器付き半導体装
置を実現できる。As described above, according to the present invention, a magnetoresistive effect element comprising a two-layer film of a magnetic film and a conductive film is vertically stacked in a semiconductor pellet shape on which a semiconductor element for driving a load with current is formed. Thus, the current path of the drive current does not need to be routed as in the conventional example, so that it is possible to prevent an increase in the on-resistance due to the provision of the current detecting element and a rise in temperature due to this. Further, since the voltage generated at the time of turning on does not increase, it is hard to be destroyed even in an emergency such as a load short circuit. If a pair of current detecting elements and a differential amplifier having opposite polarities are used,
The influence of temperature due to heat generation of the semiconductor device itself can be reduced, and current control can be performed with high accuracy, and a highly safe one-chip semiconductor device with a current detector can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態を示すブロック図で
ある。FIG. 1 is a block diagram showing a first embodiment of the present invention.

【図２】第１の実施の形態の主要部を示す半導体ペレッ
トの平面図（図２（ａ））、図２（ａ）のＡ−Ａ線断面
図（図２（ｂ））、Ｂ−Ｂ線拡大断面図（図２（ｃ））
である。FIG. 2 is a plan view (FIG. 2 (a)) of a semiconductor pellet showing a main part of the first embodiment, a cross-sectional view taken along line AA of FIG. 2 (a) (FIG. 2 (b)), and FIG. B line enlarged sectional view (FIG. 2 (c))
It is.

【図３】磁気抵抗効果素子の説明に使用するグラフであ
る。FIG. 3 is a graph used to describe a magnetoresistive element.

【図４】本発明の第２の実施の形態の主要部を示す半導
体ペレットの平面図（図４（ａ））、図４（ａ）のＡ−
Ａ線断面図（図４（ｂ））である。FIG. 4 is a plan view (FIG. 4 (a)) of a semiconductor pellet showing a main part of a second embodiment of the present invention, and FIG.
FIG. 5 is a sectional view taken along the line A (FIG. 4B).

【図５】従来例を示すブロック図である。FIG. 5 is a block diagram showing a conventional example.

【図６】従来例の主要部を示す半導体ペレットの平面図
（図６（ａ））、図６（ａ）のＡ−Ａ線断面図（図６
（ｂ））である。FIG. 6 is a plan view of a semiconductor pellet showing a main part of a conventional example (FIG. 6A), and a sectional view taken along line AA of FIG.
(B)).

【符号の説明】[Explanation of symbols]

１ Ｎ+ 型ドレイン領域（シリコン基体） ２ Ｎ型ドレイン領域（エピタキシャル層） ３ フィールド酸化膜 ４ Ｐ型ベース領域 ５ Ｎ+ 型ソース領域 ６ ゲート酸化膜 ７ ゲート電極 ８ 層間絶縁膜 ９ ソース電極 １０ ドレイン電極 １１ 酸化シリコン膜 １２−１，１２−２ 磁気抵抗効果素子 １２−１Ａ，１２−２Ａ 磁気抵抗効果素子の検出部 １３ 磁気誘導体 １４ａ，１４ｂ Ｎｉ−Ｆｅ膜（磁性体膜） １５ａ，１５ｂ Ｔｉ膜（導電膜） １６ ボンディング線 １７ ゲートパッド １８ 酸化シリコン膜 １９−１１，１９−１２，１９−２１ 電極部 ２０−１ １９−１２の先端 ２０−２ １２−２Ａの先端 ２１ ＭＯＳＦＥＴ ２２ 制御回路 ２３ 差動増幅器 ２４，２４−１，２４−２ 定電流回路 ２５ 電流検出器付き半導体装置 ２６ ホール素子 ３１ Ｎ- 型エピタキシャル層 ３２ａ ベース領域 ３２ｂ ベース電極 ３３ａ エミッタ領域 ３３ｂ エミッタ電極 ３４ａ コレクタ領域 ３４ｂ コレクタ電極 ３５ 絶縁膜 ３６ 電流路 ３７−１，３７−２ ホール電極 ３８ 磁界方向 ４１ａ，４１ｂ バイアス点 ４２ａ，４２ｂ 動作点Reference Signs List 1 N + type drain region (silicon base) 2 N type drain region (epitaxial layer) 3 Field oxide film 4 P type base region 5 N + type source region 6 Gate oxide film 7 Gate electrode 8 Interlayer insulating film 9 Source electrode 10 Drain Electrode 11 Silicon oxide film 12-1, 12-2 Magnetoresistance effect element 12-1A, 12-2A Detection part of magnetoresistance effect element 13 Magnetic derivative 14a, 14b Ni-Fe film (magnetic material film) 15a, 15b Ti film (Conductive film) 16 Bonding line 17 Gate pad 18 Silicon oxide film 19-11, 19-12, 19-21 Electrode section 20-1 Tip of 19-12 20-2 Tip of 12-2A 21 MOSFET 22 Control circuit 23 Difference Dynamic amplifier 24, 24-1, 24-2 Constant current circuit 25 Semiconductor device with current detector 26 Hall element Reference Signs List 1 N- type epitaxial layer 32a Base region 32b Base electrode 33a Emitter region 33b Emitter electrode 34a Collector region 34b Collector electrode 35 Insulating film 36 Current path 37-1, 37-2 Hall electrode 38 Magnetic field direction 41a, 41b Bias point 42a, 42b Operating point

Claims (8)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 負荷を電流駆動する半導体素子及び前記
半導体素子に流れる駆動電流を検出する電流検出素子が
同一半導体ペレットに集積されてなる電流検出器付き半
導体装置において、磁性体膜及び導電膜の２層膜からな
る磁気抵抗効果素子とこれに定電流を供給する手段とを
有し、前記駆動電流による磁界に依存する抵抗値を有す
る前記磁気抵抗効果素子が前記電流検出素子として前記
半導体素子上に縦積みされていることを特徴とする電流
検出器付き半導体装置。1. A semiconductor device with a current detector in which a semiconductor element for driving a load with current and a current detection element for detecting a drive current flowing through the semiconductor element are integrated on the same semiconductor pellet. 2-layer film Tona
That a magnetoresistive element and means for supplying it to the constant current, the magnetoresistance effect element having a resistance value that depends on the magnetic field due to the drive current is stacked vertically on the semiconductor device as the current detecting element A semiconductor device with a current detector. 【請求項２】 半導体素子から駆動電流を取り出すボン
ディング線に接続するパッドの近傍に磁気抵抗効果素子
が配置される請求項１記載の電流検出器付き半導体装
置。2. The semiconductor device with a current detector according to claim 1, wherein the magnetoresistive element is arranged near a pad connected to a bonding line for extracting a drive current from the semiconductor element. 【請求項３】 ボンディング線を囲んで配置された磁気
誘導体で形成され一部にギャップを有する磁路と、前記
ギャップ部に磁気抵抗効果素子が配置される請求項２記
載の電流検出器付き半導体装置。3. The semiconductor with a current detector according to claim 2, wherein a magnetic path formed of a magnetic derivative and surrounding the bonding line and having a gap in a part thereof, and a magnetoresistive element in the gap are disposed. apparatus. 【請求項４】 駆動電流による磁界依存性が互いに逆極
性の一対の磁気抵抗効果素子と、これらの抵抗値の差を
検出する差動増幅器とを有する請求項１，２又は３記載
の電流検出器付き半導体装置。4. The current detecting device according to claim 1, further comprising a pair of magnetoresistive effect elements whose magnetic field dependence by the driving current is opposite to each other, and a differential amplifier for detecting a difference between these resistance values. Semiconductor device with container. 【請求項５】 一対の磁気抵抗効果素子が、磁性体膜と
導電膜の積層順序が互いに逆で、同一方向にそれぞれ定
電流が流れる請求項４記載の電流検出器付き半導体装
置。5. The semiconductor device with a current detector according to claim 4, wherein the pair of magnetoresistive elements has a stacking order of the magnetic film and the conductive film opposite to each other, and a constant current flows in the same direction. 【請求項６】 一対の磁気抵抗効果素子が、磁性体膜と
導電膜の積層順序が同じで、互いに逆方向にそれぞれ定
電流が流れる請求項４記載の電流検出器付き半導体装
置。6. The semiconductor device with a current detector according to claim 4, wherein the pair of magnetoresistive elements have the same lamination order of the magnetic film and the conductive film, and a constant current flows in opposite directions. 【請求項７】 半導体素子が半導体基板の表面に接続さ
れるソース電極及び裏面に形成されるドレイン電極を有
する縦型ＩＧＦＥＴである請求項１乃至６いずれか１項
に記載の電流検出器付き半導体装置。7. A semiconductor device a vertical IGFET is claims 1 to 6 any one having a drain electrode formed on the source electrode and the rear surface is connected to the surface of the semiconductor substrate
Current detector with a semiconductor device according to. 【請求項８】 磁気誘導体がＮｉ−Ｆｅ膜を含んでなる
請求項３記載の電流検出器付き半導体装置。8. A magnetic derivative Ni-Fe film comprising Claim 3 Symbol placement of the current detector with a semiconductor device.
JP7282948A 1995-10-31 1995-10-31 Semiconductor device with current detector Expired - Fee Related JP2924741B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7282948A JP2924741B2 (en) 1995-10-31 1995-10-31 Semiconductor device with current detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7282948A JP2924741B2 (en) 1995-10-31 1995-10-31 Semiconductor device with current detector

Publications (2)

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JPH09127161A JPH09127161A (en) 1997-05-16
JP2924741B2 true JP2924741B2 (en) 1999-07-26

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7259545B2 (en) * 2003-02-11 2007-08-21 Allegro Microsystems, Inc. Integrated sensor
WO2005064356A2 (en) * 2003-12-23 2005-07-14 Koninklijke Philips Electronics N.V. High sensitivity magnetic built-in current sensor
JP4360998B2 (en) 2004-10-01 2009-11-11 Ｔｄｋ株式会社 Current sensor
JP5794777B2 (en) 2010-12-22 2015-10-14 三菱電機株式会社 Semiconductor device

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