JP2000174357A - Semiconductor device containing hall-effect element - Google Patents
Semiconductor device containing hall-effect elementInfo
- Publication number
- JP2000174357A JP2000174357A JP11281745A JP28174599A JP2000174357A JP 2000174357 A JP2000174357 A JP 2000174357A JP 11281745 A JP11281745 A JP 11281745A JP 28174599 A JP28174599 A JP 28174599A JP 2000174357 A JP2000174357 A JP 2000174357A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- hall effect
- current
- hall
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電流を検出するため
のホール効果素子を有する半導体装置に関する。The present invention relates to a semiconductor device having a Hall effect element for detecting a current.
【０００２】[0002]
【従来の技術】半導体のホール電圧が印加磁界に正比例
することを利用したホール効果素子とこのホール効果素
子のための増幅器とを単一の半導体基体に形成した半導
体集積回路は公知である。2. Description of the Related Art A semiconductor integrated circuit in which a Hall effect element utilizing the fact that the Hall voltage of a semiconductor is directly proportional to an applied magnetic field and an amplifier for the Hall effect element are formed on a single semiconductor substrate is known.
【０００３】[0003]
【発明が解決しようとする課題】ところで、従来のホ−
ル効果素子を含む集積回路は、外部磁界（集積回路の外
から加わる磁界）の検出にのみ使用され、半導体集積回
路内の他の半導体素子の入力電流や出力電流を検出する
ようには構成されていない。また、従来のホール効果素
子を含む集積回路は、集積回路内において流れる比較的
小さい電流を十分に検出できる程度の感度を有していな
い。また、従来のホ−ル効果素子を含む集積回路は不要
な外部磁界の影響を除くようには構成されていない。By the way, the conventional ho
The integrated circuit including the effect element is used only for detecting an external magnetic field (a magnetic field applied from outside the integrated circuit), and is configured to detect an input current and an output current of another semiconductor element in the semiconductor integrated circuit. Not. Further, an integrated circuit including a conventional Hall effect element does not have such a sensitivity that a relatively small current flowing in the integrated circuit can be sufficiently detected. Further, the integrated circuit including the conventional ball effect element is not configured to eliminate the influence of an unnecessary external magnetic field.
【０００４】そこで、本発明の目的はホール効果素子に
よって、電気回路の電流の検出を正確且つ容易に行うこ
とができる半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device which can accurately and easily detect the current of an electric circuit by using a Hall effect element.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための本発明に従う半導体装置は、ホー
ル効果素子を有する半導体基体と、前記半導体基体の表
面に配置された絶縁膜と、平面的に見て前記ホール効果
素子に沿うように前記絶縁膜の上に配置され且つ電気回
路の電流を流すことができるように形成された導体層と
を備えている。According to the present invention, there is provided a semiconductor device having a Hall effect element, an insulating film disposed on a surface of the semiconductor substrate, and a semiconductor device. A conductor layer disposed on the insulating film so as to be along the Hall effect element when viewed in a plan view and formed so as to allow a current of an electric circuit to flow.
【０００６】なお、ホール効果素子に加える磁束量を増
大させるために、前記導体層をホール効果素子を囲むよ
うに配置することが望ましい。また、電流の検出感度の
向上及びノイズの抑制のために、第１及び第２のホール
効果素子を設け、第１及び第２のホール効果素子に互い
に逆向きの磁界が作用するように導体層を配置すること
が望ましい。また、ホール効果素子を有する半導体装置
を小型且つ低コストにするために、別の回路素子とホー
ル効果素子とを同一の半導体基体に設けることが望まし
い。また、導体層の電流によって発生した磁束をホール
効果素子に有効に作用させるために集磁体を設けること
が望ましい。In order to increase the amount of magnetic flux applied to the Hall effect element, it is desirable to arrange the conductor layer so as to surround the Hall effect element. Further, in order to improve current detection sensitivity and to suppress noise, first and second Hall effect elements are provided, and the conductor layers are arranged so that mutually opposite magnetic fields act on the first and second Hall effect elements. It is desirable to arrange. Further, in order to reduce the size and cost of the semiconductor device having the Hall effect element, it is desirable to provide another circuit element and the Hall effect element on the same semiconductor substrate. In addition, it is desirable to provide a magnetic collector in order to make the magnetic flux generated by the current in the conductor layer effectively act on the Hall effect element.
【０００７】[0007]
【発明の効果】各請求項の発明によれば、検出するため
の電流を流す導体層をホール効果素子に接近させて配置
することができる。この結果、ホール効果素子によって
電流を正確に検出することができる。また、ホール効果
素子と導体層との相互の位置関係を正確且つ容易に設定
することができる。これにより、電流検出値のバラツキ
を抑えることができる。According to the invention of each claim, the conductor layer through which the current for detection flows can be arranged close to the Hall effect element. As a result, the current can be accurately detected by the Hall effect element. Further, the mutual positional relationship between the Hall effect element and the conductor layer can be set accurately and easily. As a result, variations in the current detection value can be suppressed.
【０００８】[0008]
【実施形態】次に、本発明に係る実施形態を図１〜図１
１を参照して説明する．Next, an embodiment according to the present invention will be described with reference to FIGS.
This is explained with reference to 1.
【０００９】[0009]
【第１の実施形態】まず、本発明の第１の実施形態を図
１〜図６を参照して説明する。図１から明らかなよう
に、第１の実施形態の半導体装置としての集積回路１
は、第１及び第２のホ−ル効果素子（以下、ホ−ル素子
と言う）２、３と、半導体素子４と、被測定電流通路用
の導体層５と、第1及び第2のホ−ル素子２、３に制御電
流を供給するための制御電流供給回路６４と、ホ−ル素
子２、３の出力を処理するための出力回路２１と、半導
体素子４のための制御回路６０と、第１、第２及び第３
の端子６１、６２、６３とを有する。なお、図１には、
集積回路装置１に含まれる複数の素子及び複数の回路が
ブロック的に示され、複数の素子及び回路の詳細は示さ
れていない。本願ではホ−ル素子のための半導体領域と
ここに設けられた複数の電極から成るホ−ル効果素子の
主要部分をホール効果素子又はホ−ル素子と呼ぶことに
する。First Embodiment First, a first embodiment of the present invention will be described with reference to FIGS. As is clear from FIG. 1, an integrated circuit 1 as a semiconductor device of the first embodiment
Are a first and a second Hall effect element (hereinafter, referred to as a Hall element) 2, 3; a semiconductor element 4; a conductor layer 5 for a current path to be measured; A control current supply circuit 64 for supplying a control current to the ball elements 2 and 3; an output circuit 21 for processing the output of the ball elements 2 and 3; and a control circuit 60 for the semiconductor element 4 And the first, second and third
Terminals 61, 62 and 63. In FIG. 1,
A plurality of elements and a plurality of circuits included in the integrated circuit device 1 are shown as blocks, and details of the plurality of elements and circuits are not shown. In the present application, a main portion of a semiconductor region for a ball element and a ball effect element including a plurality of electrodes provided therein will be referred to as a hall effect element or a ball element.
【００１０】図２は図１の集積回路１の電気回路の詳細
及びこれを使用したＤＣ−ＤＣコンバ−タを示す。集積
回路１の中の回路素子としての半導体素子４はトランジ
スタから成り、ＤＣ−ＤＣコンバ−タのスイッチング素
子として使用されている。この半導体素子４の一端（コ
レクタ）はトランス６４の１次巻線６５を介して直流電
源６６の一方の端子に接続されている。半導体素子４の
他端(エミッタ)は本発明に従う被測定電流の通路用の導
体層５から成るラインを介して直流電源６６の他方の端
子に接続されている。半導体素子４の制御端子(ベ−ス)
は制御回路６０に接続されている。制御回路６０は半導
体素子４をオン・オフ制御するための制御信号を形成す
る。トランス６４の２次巻線６７には整流ダイオ−ド６
８を介して平滑用コンデンサ６９が接続されている。平
滑用コンデンサ６９に接続された対の出力端子７０、７
１は負荷(図示せず)を接続するために使用される。対の
出力端子７０、７１間の出力直流電圧は制御回路６０に
送られ、直流出力電圧を一定に制御するために使用され
る。FIG. 2 shows details of an electric circuit of the integrated circuit 1 of FIG. 1 and a DC-DC converter using the same. The semiconductor element 4 as a circuit element in the integrated circuit 1 is composed of a transistor and is used as a switching element of a DC-DC converter. One end (collector) of the semiconductor element 4 is connected to one terminal of a DC power supply 66 via a primary winding 65 of a transformer 64. The other end (emitter) of the semiconductor element 4 is connected to the other terminal of the DC power supply 66 via a line composed of the conductor layer 5 for passing a measured current according to the present invention. Control terminal of semiconductor element 4 (base)
Is connected to the control circuit 60. The control circuit 60 forms a control signal for controlling on / off of the semiconductor element 4. A rectifying diode 6 is connected to the secondary winding 67 of the transformer 64.
8, a smoothing capacitor 69 is connected. A pair of output terminals 70 and 7 connected to a smoothing capacitor 69
1 is used to connect a load (not shown). The output DC voltage between the pair of output terminals 70 and 71 is sent to the control circuit 60 and used to control the DC output voltage to be constant.
【００１１】第１及び第２のホ−ル素子２、３は、半導
体素子４を通って流れる電流Isを検出するために電流通
路用の導体層５に沿って配置されている。第１及び第２
のホ−ル素子２、３に周知の制御電流を流すために第１
のホ−ル素子２の対の第１の電極１６a、１７ａと第２
のホ−ル素子３の対の第１の電極１６ｂ、１７bとが周
知の制御電流供給回路６４に接続されている。第１及び
第２のホ−ル素子２、３の出力電圧を合成して被測定電
流Isに対応する電圧を得るための出力回路２１は、第
１、第２及び第３の差動増幅器２９、３０、３１から成
る。第１の差動増幅器２９の正入力端子は第１のホ−ル
素子２の一方の第２の電極１８ａに接続され、この負入
力端子は第１のホ−ル素子２の他方の第２の電極１９ａ
に接続されている。第２の差動増幅回路３０の正入力端
子は第２のホ−ル素子３の一方の第２の電極１８ｂに接
続され、この負入力端子は第２のホ−ル素子３の他方の
第２の電極１９ｂに接続されている。従って、第１の差
動増幅器２９から得られる第１のホ−ル電圧Ｖh1と第２
の差動増幅器３０から得られる第２のホ−ル電圧−Ｖh2
は互いに逆の極性を有する。第３の差動増幅器３１の正
入力端子は第１の差動増幅器２９に接続され、この負入
力端子は第２の差動増幅器３０に接続されている。従っ
て、第３の差動増幅器３１からはＶh1−（-Ｖh2）＝Ｖh
1＋Ｖh2の出力が得られる。即ち、演算手段としての第
３の差動増幅器３１からは、第１の差動増幅器２９の出
力Ｖh1の絶対値と第２の差動増幅器３０の出力−Ｖh2の
絶対値との和が得られる。The first and second hole elements 2 and 3 are arranged along a current path conductor layer 5 for detecting a current Is flowing through the semiconductor element 4. First and second
In order to supply a well-known control current to the ball elements 2 and 3, the first
Of the pair of the first and second electrodes 16a, 17a and the second
The pair of first electrodes 16b and 17b of the hole element 3 are connected to a known control current supply circuit 64. An output circuit 21 for synthesizing the output voltages of the first and second hall elements 2 and 3 to obtain a voltage corresponding to the current to be measured Is includes first, second and third differential amplifiers 29. , 30, 31. The positive input terminal of the first differential amplifier 29 is connected to one second electrode 18a of the first hall element 2, and the negative input terminal is connected to the other second electrode 18a of the first hall element 2. Electrode 19a
It is connected to the. The positive input terminal of the second differential amplifier circuit 30 is connected to one second electrode 18b of the second hall element 3, and the negative input terminal is connected to the other end of the second hall element 3. 2 is connected to the second electrode 19b. Therefore, the first hall voltage Vh1 obtained from the first differential amplifier 29 and the second
The second Hall voltage -Vh2 obtained from the differential amplifier 30 of FIG.
Have opposite polarities. The positive input terminal of the third differential amplifier 31 is connected to the first differential amplifier 29, and the negative input terminal is connected to the second differential amplifier 30. Therefore, from the third differential amplifier 31, Vh1 − (− Vh2) = Vh
An output of 1 + Vh2 is obtained. That is, the sum of the absolute value of the output Vh1 of the first differential amplifier 29 and the absolute value of the output −Vh2 of the second differential amplifier 30 is obtained from the third differential amplifier 31 as the calculating means. .
【００１２】なお、第２の差動増幅器３０の出力段に反
転回路を設け、第３の差動増幅器３１の代わりに加算器
を設けることによってＶh1＋Ｖh2を示す出力を得ること
もできる。The output indicating Vh1 + Vh2 can be obtained by providing an inverting circuit at the output stage of the second differential amplifier 30 and providing an adder instead of the third differential amplifier 31.
【００１３】第１及び第２のホール素子２、３及び半導
体素子４等を含む半導体基体６は、例えばシリコン単結
晶板から成るｐ形（第１導電形）の半導体サブストレー
トにｎ形（第２導電形）のシリコンをエピタキシャル成
長させた半導体ウエハに基づいて形成されている。図４
及び図５では半導体基体６の下側のｐ形半導体領域７が
サブストレート領域であり、上側の複数のｎ形の主半導
体領域８ａ、８ｂ、８ｃ及びこれ等の間のｐ形の分離
（アイソレ−ション）領域９がエピタキシャル成長領域
である。ｐ形の分離領域９はｎ形のエピタキシャル成長
層にｐ形の不純物を拡散することによって形成されてい
る。第１及び第２のホール素子２、３を形成するための
ｎ形の第１及び第２の主半導体領域８ａ、８ｂは分離領
域９を介して並置されている。なお、各領域７、８ａ、
８ｂ、９の導電形を実施例と逆にすることができる。The semiconductor substrate 6 including the first and second Hall elements 2 and 3 and the semiconductor element 4 is formed on a p-type (first conductivity type) semiconductor substrate made of, for example, a silicon single crystal plate. It is formed based on a semiconductor wafer obtained by epitaxially growing silicon (two conductivity type). FIG.
5 and FIG. 5, the lower p-type semiconductor region 7 of the semiconductor substrate 6 is a substrate region, and the upper plurality of n-type main semiconductor regions 8a, 8b, 8c and the p-type isolation (isolation) therebetween. Region 9 is an epitaxial growth region. The p-type isolation region 9 is formed by diffusing a p-type impurity into an n-type epitaxial growth layer. The n-type first and second main semiconductor regions 8 a and 8 b for forming the first and second Hall elements 2 and 3 are juxtaposed via an isolation region 9. In addition, each area 7, 8a,
The conductivity types of 8b and 9 can be reversed from the embodiment.
【００１４】第１及び第２のホール素子２、３のホ−ル
効果を得るための第１及び第２のｎ形半導体領域（以
下、ホ−ル半導体領域という）８ａ、８ｂはｐ形の半導
体領域７とｐ形の分離領域９に囲まれた島状領域であっ
て図６に示すように平面的に見て十字状に形成されてい
る。第１のホ−ル半導体領域８ａの中には一対の制御電
流供給用のｎ形半導体領域１０ａ、１１ａと一対のホー
ル電圧検出用のｎ形半導体領域１２ａ、１３ａと一対の
ｐ形の半導体領域１４ａ、１５ａとが設けられている。
第２のホ−ル半導体領域８ｂの中には、第１のホ−ル半
導体領域８ａと同様に、一対の制御電流供給用の半導体
領域１０ｂ、１１ｂと一対のホール電圧検出用のｎ形半
導体領域１２ｂ、１３ｂと一対のｐ形の半導体領域１４
ｂ、１５ｂとが設けられている。なお、第１及び第２の
ホール素子２、３は実質的に同一の構成を有するので、
実質的に同一の部分には同一の参照数字を付し、両者を
区別するために一方に添字ａ、他方に添字ｂを付し、一
方のホール素子２の構成を詳しく説明し、他方のホール
素子３の構成の詳しい説明を省略する。The first and second n-type semiconductor regions (hereinafter referred to as "hole semiconductor regions") 8a and 8b for obtaining the Hall effect of the first and second Hall elements 2 and 3 are p-type. This is an island-shaped region surrounded by the semiconductor region 7 and the p-type isolation region 9, and is formed in a cross shape as viewed in plan as shown in FIG. The first hole semiconductor region 8a includes a pair of n-type semiconductor regions 10a and 11a for supplying a control current, a pair of n-type semiconductor regions 12a and 13a for detecting a hole voltage, and a pair of p-type semiconductor regions. 14a and 15a are provided.
Like the first hole semiconductor region 8a, the second hole semiconductor region 8b includes a pair of semiconductor regions 10b and 11b for supplying a control current and a pair of n-type semiconductors for detecting a hole voltage. Regions 12b and 13b and a pair of p-type semiconductor regions 14
b and 15b. Since the first and second Hall elements 2 and 3 have substantially the same configuration,
Substantially the same parts are denoted by the same reference numerals, one is denoted by a suffix a and the other is denoted by a suffix b to distinguish them, and the structure of one Hall element 2 is described in detail, Detailed description of the configuration of the element 3 is omitted.
【００１５】第１のホール素子２において、このホール
素子２の主要部をなすホ−ル半導体領域８ａの長手方向
即ち図６のＹ軸方向における両端近傍にｎ形不純物の拡
散によって一対の制御電流供給用の半導体領域１０ａ、
１１ａが形成されている。この対の制御電流供給用の半
導体領域１０ａ、１１ａはホ−ル半導体領域８ａよりも
高い不純物濃度を有している。この対の半導体領域１０
ａ、１１ａには対の第１の電極１６ａ、１７ａがオーミ
ック接触されている。ホ−ル半導体領域８ａの図６のＹ
軸方向の中央の両端近傍に一対のｐ形半導体領域１４
ａ、１５ａがｐ形の不純物の拡散によって形成されてい
る。この対のｐ形半導体領域１４ａ、１５ａは対のホ−
ル電圧検出用のｎ形半導体領域１２ａ、１３ａのホ−ル
半導体領域８ａに対する接触面積を制限するためのもの
である。一対のホール電圧検出用の半導体領域１２ａ、
１３ａはｎ形の不純物の拡散によって形成されたもので
あって、ｐ形半導体領域１４ａ、１５ａに制限されてホ
−ル半導体領域８ａに隣接配置されている。この対のホ
ール電圧検出用のｎ形半導体領域１２ａ、１３ａはホ−
ル半導体領域８ａよりも高い不純物濃度を有する。この
対のｎ形半導体領域１２ａ、１３ａには、対の第２の電
極１８ａ、１９ａがオーミック接触されている。ホ−ル
半導体領域８ａにおける一対のホール電圧検出用の半導
体領域１２ａ、１３ａの相互間領域は一対の制御電流供
給用の半導体領域１０ａ、１１ａの相互間領域に直交し
ている。In the first Hall element 2, a pair of control currents are diffused in the longitudinal direction of the hole semiconductor region 8a constituting the main part of the Hall element 2, that is, in the vicinity of both ends in the Y-axis direction of FIG. Supply semiconductor region 10a,
11a is formed. The semiconductor regions 10a and 11a for supplying the control current have a higher impurity concentration than the hole semiconductor region 8a. This pair of semiconductor regions 10
A pair of first electrodes 16a and 17a are in ohmic contact with a and 11a. 6 of the hole semiconductor region 8a in FIG.
A pair of p-type semiconductor regions 14 are provided near both ends at the center in the axial direction.
a and 15a are formed by diffusion of p-type impurities. The pair of p-type semiconductor regions 14a and 15a are
This is for limiting the contact area of the n-type semiconductor regions 12a and 13a for detecting the voltage to the hole semiconductor region 8a. A pair of semiconductor regions 12a for Hall voltage detection,
Reference numeral 13a is formed by diffusion of an n-type impurity, and is limited to the p-type semiconductor regions 14a and 15a and is disposed adjacent to the hole semiconductor region 8a. The n-type semiconductor regions 12a and 13a for detecting the pair of hole voltages are
Impurity concentration higher than that of the semiconductor region 8a. The pair of second electrodes 18a, 19a are in ohmic contact with the pair of n-type semiconductor regions 12a, 13a. The region between the pair of hole voltage detecting semiconductor regions 12a and 13a in the hole semiconductor region 8a is orthogonal to the region between the pair of control current supplying semiconductor regions 10a and 11a.
【００１６】半導体基体６の一方の主面上には図４及び
図５に示すように絶縁膜２０が設けられている。この絶
縁膜２０に形成された開口を通して一対の第１の電極１
６ａ、１７ａがｎ形の一対の制御電流供給用半導体領域
１０ａ、１１ａにオーミック接触し、また一対の第２の
電極１８ａ、１９ａがｎ形のホール電圧検出用半導体領
域１２ａ、１３ａにオーミック接触している。第１及び
第２のホール素子２、３の対の第１の電極１６ａ、１７
ａ及び１６ｂ、１７ｂは図２に示す制御電流供給回路６
４に接続されている。また、第１及び第２のホール素子
２、３の対の第２の電極１８ａ、１９ａ及び１８ｂ、１
９ｂは図２に示すようにホール電圧検出手段としての出
力回路２１に接続されている。On one main surface of the semiconductor substrate 6, an insulating film 20 is provided as shown in FIGS. A pair of first electrodes 1 pass through an opening formed in the insulating film 20.
6a and 17a make ohmic contact with a pair of n-type control current supply semiconductor regions 10a and 11a, and a pair of second electrodes 18a and 19a make ohmic contact with n-type hole voltage detection semiconductor regions 12a and 13a. ing. First electrodes 16a, 17 of a pair of first and second Hall elements 2, 3
a and 16b and 17b are control current supply circuits 6 shown in FIG.
4 is connected. Further, a pair of second electrodes 18a, 19a and 18b, 1 of the first and second Hall elements 2, 3 are provided.
9b is connected to an output circuit 21 as a Hall voltage detecting means as shown in FIG.
【００１７】第１及び第２のホール素子２、３の組合せ
によって電流検出器を構成するために、被測定電流通路
としての導体層５が絶縁膜２０の上に配置されている。
この被測定電流通路用の導体層５は、図３に示すように
半導体基体６の一方の主面に対して垂直の方向から見
て、即ち平面的に見て第１及び第２のホール素子２、３
の第１及び第２のホ−ル半導体領域８ａ、８ｂをそれぞ
れほぼ囲み且つ第１及び第２のホ−ル半導体領域８ａ、
８ｂの相互間を通るように配置されている。更に詳細に
説明すると、導体層５は、第１のホ−ル半導体領域８ａ
をコ字状に包囲する第１の部分５ａと、第２のホ−ル半
導体領域８ｂをコ字状に包囲する第２の部分５ｂと、第
１及び第２の部分５ａ、５ｂを連結する第３の部分５ｃ
と、第１及び第２の部分５ａ、５ｂから導出されている
第４及び第５の部分５ｄ、５ｅから成る。なお、第１、
第２及び第３の部分５ａ、５ｂ、５ｃは全体としてＳ字
状に形成されている。また、図１に示すように導体層５
は半導体路素子４に接続されている。従って、導体層５
には半導体素子４を通る電流Isが流れる。In order to constitute a current detector by combining the first and second Hall elements 2 and 3, a conductor layer 5 as a current path to be measured is disposed on the insulating film 20.
As shown in FIG. 3, the conductor layer 5 for the current path to be measured is formed of first and second Hall elements when viewed from a direction perpendicular to one main surface of the semiconductor substrate 6, that is, when viewed in plan. Two, three
Of the first and second hole semiconductor regions 8a and 8b, respectively, and substantially surround the first and second hole semiconductor regions 8a and 8b, respectively.
8b. More specifically, the conductor layer 5 includes a first hole semiconductor region 8a.
Are connected in a U-shape, the second portion 5b surrounding the second hole semiconductor region 8b in a U-shape, and the first and second portions 5a and 5b are connected. Third part 5c
And fourth and fifth portions 5d and 5e derived from the first and second portions 5a and 5b. The first,
The second and third portions 5a, 5b, 5c are formed in an S-shape as a whole. Also, as shown in FIG.
Are connected to the semiconductor path element 4. Therefore, the conductor layer 5
, A current Is passing through the semiconductor element 4 flows.
【００１８】半導体素子４は図３、図５及び図６に概略
的に示すように第１及び第２のホール素子２、３と同一
の半導体基体６に設けられている。即ち、図３、図５及
び図６には半導体素子４としてｎ形エミッタ領域２２、
ｐ形ベース領域２３、ｎ形コレクタ領域２４、ｎ+形コ
レクタ領域２５、エミッタ電極２６、ベース電極２７、
及びコレクタ電極２８から成る周知のトランジスタが設
けられている。図１及び図２に示されている周知の制御
電流供給回路６４、出力回路２１、及び制御回路６０も
半導体基体６に周知の技術で形成されている。第１及び
第２のホール素子２，３に沿って配置された導体層５
は、絶縁膜２０上の図示されていない別の配線用の導体
層と同時に形成された金属層から成る。The semiconductor element 4 is provided on the same semiconductor substrate 6 as the first and second Hall elements 2 and 3, as schematically shown in FIGS. That is, in FIGS. 3, 5 and 6, the n-type emitter region 22,
a p-type base region 23, an n-type collector region 24, an n + -type collector region 25, an emitter electrode 26, a base electrode 27,
And a well-known transistor comprising a collector electrode 28. The known control current supply circuit 64, the output circuit 21, and the control circuit 60 shown in FIGS. 1 and 2 are also formed on the semiconductor substrate 6 by a known technique. Conductive layer 5 arranged along first and second Hall elements 2 and 3
Is formed of a metal layer formed simultaneously with another wiring conductor layer (not shown) on the insulating film 20.
【００１９】半導体素子４の電流Ｉs は導体層５に例え
ば図３で矢印に示すように流れる。即ち電流Isは、導体
層５の第４の部分５ｄから第５の部分５ｅに向うように
流れる。これにより、アンペアの右ネジの法則に従って
図４で矢印で示す方向の磁力線Ｈ即ち磁束が生じる。図
２の磁力線Ｈの方向から明らかなように第１のホール素
子２のホ−ル半導体領域８ａに作用する磁力線Ｈの方向
とホール素子３の第２のホ−ル半導体領域８ｂに作用す
る磁力線Ｈの方向とは互いに逆向きになる。また、電流
測定時には第１及び第２のホール素子２、３の対の第１
の電極１６ａ、１７ａ及び１６ｂ、１７ｂ間に周知の方
法によって制御電流Ｉc をそれぞれ流す。磁力線Ｈは制
御電流Ｉc に直交する方向性を有するので、第１及び第
２のホール素子２、３の対の第２の電極１８ａ、１９ａ
間及び１８ｂ、１９ｂ間に第１及び第２のホール電圧Ｖ
h1、−Ｖh2がそれぞれ発生する。第１及び第２のホール
電圧Ｖh1、−Ｖh2の絶対値は配線導体層５に流れる電流
Ｉs の大きさに比例する。第１及び第２の差動増幅器２
９、３０からは互いに逆の極性の第１及び第２のホール
電圧Ｖh1、−Ｖh2が得られるので、第３の差動増幅器３
１からは、Ｖh1＋Ｖh2の合成出力が得られる。即ち、第
３の差動増幅器３１によって第１及び第２のホール素子
２、３の出力電圧の絶対値の加算値に対応した出力を得
ることができる。なお、第１及び第２のホール素子２，
３は同一パターンに形成されているので、第１及び第２
のホール電圧Ｖh1、Ｖh2は互いに実質的に等しい。従っ
て、第３の差動増幅器３１の出力は２Ｖh1になり、１つ
のホール素子の２倍の出力を得ることができる。The current Is of the semiconductor element 4 flows through the conductor layer 5 as shown by an arrow in FIG. 3, for example. That is, the current Is flows from the fourth portion 5d of the conductor layer 5 to the fifth portion 5e. As a result, a magnetic field line H, that is, a magnetic flux is generated in the direction indicated by the arrow in FIG. 4 according to the right-hand screw rule of ampere. As is apparent from the direction of the magnetic field line H in FIG. 2, the direction of the magnetic field line H acting on the hole semiconductor region 8a of the first Hall element 2 and the magnetic field line acting on the second hole semiconductor region 8b of the Hall element 3 The directions of H are opposite to each other. Also, at the time of current measurement, the first and second Hall elements 2 and 3 have the first pair.
A control current Ic is applied between the electrodes 16a, 17a and 16b, 17b by a known method. Since the line of magnetic force H has a direction perpendicular to the control current Ic, the pair of second electrodes 18a, 19a of the first and second Hall elements 2, 3 is provided.
And the first and second Hall voltages V between
h1 and −Vh2 are generated respectively. The absolute values of the first and second Hall voltages Vh1, -Vh2 are proportional to the magnitude of the current Is flowing through the wiring conductor layer 5. First and second differential amplifier 2
Since the first and second Hall voltages Vh1 and -Vh2 having polarities opposite to each other are obtained from the third and third differential amplifiers 3 and 9, respectively.
From 1, a composite output of Vh1 + Vh2 is obtained. That is, an output corresponding to the sum of the absolute values of the output voltages of the first and second Hall elements 2 and 3 can be obtained by the third differential amplifier 31. Note that the first and second Hall elements 2,
3 are formed in the same pattern, so that the first and second
Are substantially equal to each other. Therefore, the output of the third differential amplifier 31 becomes 2Vh1, and an output twice as large as that of one Hall element can be obtained.
【００２０】本実施形態は次の利点を有する。 （１） 第１及び第２のホール素子２、３が形成されて
いる半導体基体６の表面の絶縁膜２０の上に被測定電流
通路としての導体層５を設け、この導体層５をホール素
子２、３に隣接配置したので、被測定電流通路をホール
素子２、３に対して近接配置することが可能になり、電
流Isの検出感度の向上を達成することができる。 （２） 被測定電流通路としての導体層５をホール素子
２、３の全周の約９０％を囲むように配置したので、平
面的に見て略四角形の第１及び第２のホール素子半導体
領域８ａ、８ｂの４つの辺の全ての方向から磁界即ち磁
力線Ｈを第１及び第２のホ−ル半導体領域８ａ、８ｂに
作用させることができ、第１及び第２のホ−ル半導体領
域８ａ、８ｂに有効に作用する磁束の量が大きくなり、
電流Isの検出感度の向上を図ることができる。 （３） 第１及び第２のホール素子２、３出力の絶対値
の加算値が得られるので、電流検出感度が大きくなる。 （４） 導体層５の第３の部分５ｃを第１及び第２のホ
ール素子２、３で共用しているので、集積回路１のスペ
ースの増大が抑えられている。 （５） 第１及び第２のホール素子２、３を並置し、こ
の合成出力を得る構成であり、且つ第１及び第２のホー
ル素子２、３に対する導体層５の巻き方向が互いに逆に
なっているので、不要な外部磁界（ノイズ）が第１及び
第２のホール素子２、３に加わった場合にこれ等の相殺
が生じ、外部磁界の影響の少ない電流検出を行うことが
できる。即ち不要外部磁界に基づくホール電圧をＶ0 と
すると、第１の差動増幅器２９の出力はＶh1＋Ｖ0 、第
２の差動増幅器３０の出力は−Ｖh2＋Ｖ0 となり、第３
の差動増幅器３１の出力はＶh1＋Ｖ0 −（−Ｖh2＋Ｖ0
）＝Ｖh1＋Ｖh2となり、不要外部磁界の影響の少ない
出力を得ることができ、電流Isの検出精度が向上する。 （６） 被測定電流通路としての導体層５は、集積回路
１の他の配線用の導体層の形成工程を共用して同時に作
ることができるので、集積回路１のコストの上昇が抑え
られる。従って、ホール素子の代りにＧＭＲ（巨大磁気
抵抗効果）素子を用いた従来の集積回路等に比べてコス
ト等の点で有利になる。This embodiment has the following advantages. (1) A conductor layer 5 as a current path to be measured is provided on the insulating film 20 on the surface of the semiconductor substrate 6 on which the first and second Hall elements 2 and 3 are formed. Since the current paths to be measured are disposed adjacent to the Hall elements 2 and 3, the current paths to be measured can be disposed close to the Hall elements 2 and 3, and the detection sensitivity of the current Is can be improved. (2) Since the conductor layer 5 as the current path to be measured is disposed so as to surround about 90% of the entire circumference of the Hall elements 2 and 3, the first and second Hall element semiconductors are substantially square in plan view. Magnetic fields, that is, lines of magnetic force H can be applied to the first and second hole semiconductor regions 8a and 8b from all directions of the four sides of the regions 8a and 8b, and the first and second hole semiconductor regions can be applied. 8a and 8b, the amount of magnetic flux effectively acting increases,
The detection sensitivity of the current Is can be improved. (3) Since the sum of the absolute values of the first and second Hall elements 2 and 3 is obtained, the current detection sensitivity is increased. (4) Since the third portion 5c of the conductor layer 5 is shared by the first and second Hall elements 2, 3, an increase in the space of the integrated circuit 1 is suppressed. (5) The first and second Hall elements 2 and 3 are juxtaposed to obtain a combined output, and the winding directions of the conductor layer 5 around the first and second Hall elements 2 and 3 are opposite to each other. Therefore, when an unnecessary external magnetic field (noise) is applied to the first and second Hall elements 2 and 3, these cancel each other out, and current detection with little influence of the external magnetic field can be performed. That is, if the Hall voltage based on the unnecessary external magnetic field is V0, the output of the first differential amplifier 29 is Vh1 + V0, the output of the second differential amplifier 30 is -Vh2 + V0,
Output of the differential amplifier 31 is Vh1 + V0-(-Vh2 + V0
) = Vh1 + Vh2, an output less affected by an unnecessary external magnetic field can be obtained, and the detection accuracy of the current Is is improved. (6) Since the conductor layer 5 as the current path to be measured can be simultaneously formed by sharing the process of forming the conductor layer for other wirings of the integrated circuit 1, an increase in the cost of the integrated circuit 1 can be suppressed. Therefore, it is advantageous in terms of cost and the like as compared with a conventional integrated circuit or the like using a GMR (giant magnetoresistance effect) element instead of the Hall element.
【００２１】[0021]
【第２の実施形態】次に図７及び図８を参照して第２の
実施形態のホール素子を含む集積回路１ａを説明する。
但し、図７及び図８において図１〜図６と実質的に同一
の部分には同一の符号を付してその説明を省略する。図
７及び図８の集積回路１ａは、新たに絶縁層４０と、Ｆ
ｅ、又はＮｉ、又はＦｅとＮｉの合金等の透磁率の高い
材料から成る集磁板４１とを設け、この他は図１〜図６
の集積回路１と同様に構成したものである。図８から明
らかなように、絶縁層４０は、電極１６ａ、１６ｂ、１
７ａ、１７ｂ、１８ａ、１８ｂ、１９ａ、１９ｂ、絶縁
膜２０、及び導体層５を覆うように形成されている。集
磁板４１は絶縁層４０の上に配置されている。この集磁
板４１は空気よりも透磁率が高いので、導体層５を流れ
る電流に基づいて生じた磁束をホール半導体領域８ａ、
８ｂに良好に導き、ホール素子２、３の感度の向上に寄
与する。この集磁板４１は、電流通路としての導体層５
から生じる磁束の全てを集磁できるように、第１及び第
２のホ−ル素子２、３及び導体層５を十分に覆うように
配置することが望ましい。Second Embodiment Next, an integrated circuit 1a including a Hall element according to a second embodiment will be described with reference to FIGS.
However, in FIGS. 7 and 8, portions substantially the same as those in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof is omitted. The integrated circuit 1a of FIG. 7 and FIG.
e or Ni, or a magnetic flux collecting plate 41 made of a material having high magnetic permeability such as an alloy of Fe and Ni.
And the same configuration as the integrated circuit 1. As is clear from FIG. 8, the insulating layer 40 includes the electrodes 16a, 16b, 1
7a, 17b, 18a, 18b, 19a, 19b, the insulating film 20, and the conductor layer 5 are formed so as to cover them. The magnetic flux collecting plate 41 is disposed on the insulating layer 40. Since the magnetic flux collecting plate 41 has higher magnetic permeability than air, the magnetic flux generated based on the current flowing through the conductor layer 5 is transferred to the hole semiconductor region 8a,
8b, which contributes to the improvement of the sensitivity of the Hall elements 2 and 3. This magnetic flux collecting plate 41 is provided with a conductor layer 5 as a current path.
It is desirable to arrange the first and second hole elements 2 and 3 and the conductor layer 5 so as to sufficiently cover all the magnetic fluxes generated from the magnetic field.
【００２２】[0022]
【第３の実施形態】図９は第３の実施形態の集積回路１
ｂを図１と同様に示す平面図である。この図９の集積回
路１ｂは、図１の集積回路１から半導体素子４及び制御
回路６０を省き、この他は図１と同様に構成したもので
ある。従って、図９において図１〜図６と共通する部分
には同一の符号を付してその説明を省略する。図９の集
積回路１ｂは、第１及び第２のホ−ル素子２、３と、被
測定電流通路用の導体層５と、制御電流供給回路６４
と、出力回路２１とを共通の半導体基体６ａに基づいて
集積化したものである。図９において、第１及び第２の
ホ−ル素子２、３と導体層５との関係は図１のこれ等の
関係と同一であるので、図９の集積回路１ｂは図１の集
積回路１と同一の利点を有する。Third Embodiment FIG. 9 shows an integrated circuit 1 according to a third embodiment.
FIG. 2b is a plan view showing the same as FIG. 1. The integrated circuit 1b of FIG. 9 has the same configuration as that of FIG. 1 except that the semiconductor element 4 and the control circuit 60 are omitted from the integrated circuit 1 of FIG. Therefore, in FIG. 9, portions common to FIGS. 1 to 6 are denoted by the same reference numerals and description thereof is omitted. The integrated circuit 1b of FIG. 9 includes first and second hole elements 2, 3, a conductor layer 5 for a current path to be measured, and a control current supply circuit 64.
And the output circuit 21 are integrated based on a common semiconductor substrate 6a. In FIG. 9, since the relationship between the first and second hole elements 2, 3 and the conductor layer 5 is the same as these relationships in FIG. 1, the integrated circuit 1b in FIG. It has the same advantages as 1.
【００２３】[0023]
【第４の実施形態】図１０に示す第４の実施形態の第１
及び第２のホ−ル素子２，３を有する集積回路１ｃは、
図６の集積回路１ｂから制御電流供給回路６４と制御回
路２１とを省き、この他は図９と同一に形成したもので
ある。従って、図１０において図９と同一の部分には同
一の符号付してその説明を省略する。なお、図１０には
電極１６ａ、１６ｂ，１７ａ、１７ｂ，１８ａ、１８
ｂ、１９ａ、及び１９ｂが破線で示めされている。図１
０の集積回路１ｃは、図１及び図９と同様に第１及び第
２のホ−ル素子２、３及び導体層５を有するので、図１
及び図９の集積回路１及び１ｂと同一の利点を有する。
また、図１０の集積回路１ｃにおいては、第１のホ−ル
素子２の他方の第２の電極１９ａと第２のホ−ル素子３
の他方の第２の電極１９ｂとを電気的に接続し、第１の
ホ−ル素子２の一方の第２の電極１８ａと第２のホ−ル
素子３の一方の第２の電極１８ｂとの間からホ−ル電圧
検出信号を得ることができる。この場合には、第１及び
第２のホ−ル素子２、３の第１及び第２のホ−ル電圧Ｖ
h1、Ｖh2の加算値Ｖh1＋Ｖh2が電極１８ａと電極１８ｂ
との間に得られる。また、図１０においては、第１のホ
−ル素子２の一方の第２の電極１８ａと第２のホ−ル素
子３の一方の第２の電極１８ｂとを電気的に接続し、第
１のホ−ル素子２の他方の第２の電極１９ａと第２のホ
−ル素子３の他方の第２の電極１９ｂとの間から第１及
び第２のホ−ル電圧Ｖh1、Ｖh2の加算値Ｖh1＋Ｖh2を得
ることができる。Fourth Embodiment A first embodiment of the fourth embodiment shown in FIG.
And an integrated circuit 1c having the second ball elements 2 and 3
The control current supply circuit 64 and the control circuit 21 are omitted from the integrated circuit 1b in FIG. 6, and the other components are formed in the same manner as in FIG. Therefore, in FIG. 10, the same portions as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted. FIG. 10 shows the electrodes 16a, 16b, 17a, 17b, 18a, 18
b, 19a and 19b are indicated by dashed lines. FIG.
1 has the first and second hole elements 2, 3 and the conductor layer 5 as in FIGS.
And the same advantages as the integrated circuits 1 and 1b of FIG.
In the integrated circuit 1c of FIG. 10, the other second electrode 19a of the first ball element 2 and the second ball element 3
Is electrically connected to the other second electrode 19b, so that one second electrode 18a of the first hall element 2 and one second electrode 18b of the second hall element 3 are connected to each other. A hall voltage detection signal can be obtained from between the steps. In this case, the first and second ball voltages V of the first and second ball elements 2 and 3 are set.
The added value Vh1 + Vh2 of h1 and Vh2 is the electrode 18a and the electrode 18b.
Obtained between In FIG. 10, one second electrode 18a of the first ball element 2 and one second electrode 18b of the second ball element 3 are electrically connected to each other, Of the first and second hole voltages Vh1, Vh2 from between the other second electrode 19a of the ball element 2 and the other second electrode 19b of the second ball element 3. The value Vh1 + Vh2 can be obtained.
【００２４】[0024]
【第５の実施形態】次に、図１１の第５の実施形態の集
積回路１ｄは、第１及び第２のホ−ル半導体領域８ａ、
８ｂと電流通路としての導体層５とのパターンを変形
し、この他は図７及び図８の集積回路１ａと同一に構成
したものである。従って、図１１において図７及び図８
と実質的に同一の部分には同一の符号を付してその説明
を省略する。図１１においては、第１及び第２のホ−ル
素子２、３の詳細は示されておらず、６角形に変形され
た第１及び第１のホ−ル半導体領域８ａ、８ｂのパタ−
ンのみが示されている。図１１における被測定電流通路
用の導体層５は、幅狭部分５０と対の幅広部分５１、５
２とを有する。２つのホ−ル素子２、３の相互間に幅狭
部分５０が配置され、２つのホ−ル素子２、３から離間
した領域に幅広部分５１、５２が配置されている。第１
及び第２のホ−ル素子２、３及び導体層５の上に図７と
同様に集磁板４１が配置されている。Fifth Embodiment Next, an integrated circuit 1d according to a fifth embodiment shown in FIG. 11 includes first and second hole semiconductor regions 8a,
The pattern of the conductor 8b and the conductor layer 5 as a current path is modified, and the rest is the same as the integrated circuit 1a of FIGS. 7 and 8. 7 and 8 in FIG.
The same reference numerals are given to substantially the same portions as those described above, and the description thereof is omitted. In FIG. 11, the details of the first and second hole elements 2 and 3 are not shown, and the patterns of the first and first hole semiconductor regions 8a and 8b deformed into a hexagon are not shown.
Only one is shown. The conductor layer 5 for the current path to be measured in FIG. 11 includes a narrow portion 50 and a pair of wide portions 51, 5.
And 2. A narrow portion 50 is arranged between the two hall elements 2 and 3, and wide sections 51 and 52 are arranged in a region separated from the two hall elements 2 and 3. First
A magnetic flux collecting plate 41 is arranged on the second hole elements 2, 3 and the conductor layer 5 as in FIG.
【００２５】図１１の集積回路１ｄは第１及び第２の実
施形態と同様な利点を有する他に、次の利点も有する。 （１） 幅狭部分５０において電流密度を増加できるの
で、被測定電流通路としての導体層５の幅狭部分５０を
流れる電流に基づいて生じ磁束第１及び第２のホ−ル素
子２、３に有効に作用させることができ、電流の検出感
度をさらに向上させることができる。 （２） 幅広部分５１、５２は放熱性が良いので、導体
層５ａの放熱性の向上が図られ、比較的大きな被測定電
流の検出が可能になる。 （３） ２つのホ−ル素子２、３の間に共通の被測定電
流通路としての導体層５を配置しているので、集積回路
１ｄの省スペ−ス化が図られる。本発明は上述の実施態
様に限定されるものでなく、例えば次の変形が可能なも
のである。The integrated circuit 1d of FIG. 11 has the following advantages in addition to the same advantages as those of the first and second embodiments. (1) Since the current density can be increased in the narrow portion 50, the magnetic flux generated based on the current flowing through the narrow portion 50 of the conductor layer 5 as the current path to be measured is generated by the first and second hole elements 2, 3 And the current detection sensitivity can be further improved. (2) Since the wide portions 51 and 52 have good heat dissipation, the heat dissipation of the conductor layer 5a is improved, and a relatively large current to be measured can be detected. (3) Since the conductor layer 5 as a common current path to be measured is disposed between the two hall elements 2 and 3, the space of the integrated circuit 1d can be saved. The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible.
【００２６】[0026]
【変形例】（１） 図１〜図１１の各実施態様におい
て、第１及び第２のホール素子２、３のいずれか一方を
省いて１つのホール素子で電流検出を行うように構成す
ることができる。なお、図１〜図１０の集積回路１、１
ａ、１ｂ及び１ｃにおいて、第１のホール素子２のみを
設ける場合には、導体層５の第１及び第３の部分５ａ、
５ｃを被測定電流通路とすることが望ましい。また、ホ
ール素子を３個以上設けて、これ等の合成出力を得るこ
ともできる。 （２） 図１〜図１０において導体層５を第１及び第２
のホール素子２、３の間の第３の部分５ｃのみのパター
ンとし、第１及び第２の部分５ａ、５ｂを省くことがで
きる。この様に構成しても不要外部磁界（ノイズ）の影
響を低減できる。なお、導体層５を第１及び第２のホー
ル素子２、３のそれぞれの全周の半分以上を囲むように
設けることが望ましい。 （３） 集磁体としての集磁板４１を対のホ−ル半導体
領域８ａ、８ｂの上方の特定された領域のみに配置する
ことができる。 （４） 集磁板４１の代りにフェライト入り樹脂層から
成る集磁体をホール素子２、３の上方に設けることがで
きる。 （５） 導体層５を周知の多層化の技術によってコイル
状に形成し、コイル状導体層で第１及び第２のホール素
子２、３をそれぞれ囲むことができる。[Modification] (1) In each of the embodiments shown in FIGS. 1 to 11, one of the first and second Hall elements 2 and 3 is omitted, and current detection is performed by one Hall element. Can be. The integrated circuits 1 and 1 shown in FIGS.
a, 1b and 1c, when only the first Hall element 2 is provided, the first and third portions 5a,
It is desirable that 5c be a current path to be measured. Alternatively, three or more Hall elements may be provided to obtain a combined output of these. (2) In FIG. 1 to FIG.
The first and second portions 5a and 5b can be omitted by forming a pattern of only the third portion 5c between the Hall elements 2 and 3. Even with such a configuration, the influence of an unnecessary external magnetic field (noise) can be reduced. Preferably, the conductor layer 5 is provided so as to surround at least half of the entire circumference of each of the first and second Hall elements 2 and 3. (3) The magnetic flux collecting plate 41 as a magnetic collector can be arranged only in a specified region above the pair of hole semiconductor regions 8a and 8b. (4) A magnetic collector made of a resin layer containing ferrite can be provided above the Hall elements 2 and 3 instead of the magnetic collector 41. (5) The conductor layer 5 can be formed in a coil shape by a known multi-layering technique, and the first and second Hall elements 2 and 3 can be surrounded by the coil-shaped conductor layer, respectively.
【図１】本発明の第１の実施形態のホール効果素子を含
む集積回路を概略的に示す平面図である。FIG. 1 is a plan view schematically showing an integrated circuit including a Hall effect element according to a first embodiment of the present invention.
【図２】図１の集積回路を適用したＤＣ−ＤＣコンバ−
タの回路図である。2 is a DC-DC converter to which the integrated circuit of FIG. 1 is applied.
FIG.
【図３】図１の集積回路の一部を詳しく示す平面図であ
る。FIG. 3 is a plan view showing a part of the integrated circuit of FIG. 1 in detail.
【図４】第１の実施形態の集積回路を図３のＡ−Ａ線で
示す断面図である。FIG. 4 is a sectional view of the integrated circuit according to the first embodiment, taken along line AA of FIG. 3;
【図５】第１の実施形態の集積回路を図３のＢ−Ｂ線で
示す断面図である。FIG. 5 is a sectional view of the integrated circuit according to the first embodiment, taken along line BB of FIG. 3;
【図６】図４の半導体基体の表面を示す平面図である。FIG. 6 is a plan view showing the surface of the semiconductor substrate of FIG. 4;
【図７】第２の実施形態の集積回路の一部を示す平面図
である。FIG. 7 is a plan view showing a part of an integrated circuit according to a second embodiment.
【図８】図７の集積回路のＣ−Ｃ線断面図である。8 is a cross-sectional view of the integrated circuit of FIG. 7 taken along line CC.
【図９】第３の実施形態の集積回路を図１と同様に概略
的に示す平面図である。FIG. 9 is a plan view schematically showing an integrated circuit according to a third embodiment, similarly to FIG. 1;
【図１０】第４の実施形態の対のホ−ル効果素子を有す
る集積回路を図１と同様に概略的に示す平面図である。FIG. 10 is a plan view schematically showing an integrated circuit having a pair of hole effect elements according to the fourth embodiment, similarly to FIG. 1;
【図１１】第５の実施形態の集積回路の一部を図７と同
様に示す平面図である。FIG. 11 is a plan view showing a part of an integrated circuit according to a fifth embodiment, similarly to FIG. 7;
２，３ ホール素子 ４ 半導体素子 ５ 導体層 2,3 Hall element 4 Semiconductor element 5 Conductive layer
Claims (9)
装置であって、ホール効果素子を有する半導体基体と、 前記半導体基体の表面に配置された絶縁膜と、 平面的に見て前記ホール効果素子に沿うように前記絶縁
膜の上に配置され且つ前記電気回路の電流を流すことが
できるように形成された導体層とを備えていることを特
徴とする半導体装置。1. A semiconductor device for measuring a current of an electric circuit, comprising: a semiconductor substrate having a Hall effect element; an insulating film disposed on a surface of the semiconductor substrate; A conductor layer disposed on the insulating film so as to extend along the element and formed so as to allow a current of the electric circuit to flow.
囲の半分以上を囲むように配置されていることを特徴と
する請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said conductor layer is disposed so as to surround at least half of the entire periphery of said Hall effect element.
し、前記導体層は前記別の回路素子を通って流れた電流
がこの導体層を通って流れるように前記別の回路素子に
接続されていることを特徴とする請求項１又は２記載の
半導体装置。3. The semiconductor substrate further includes another circuit element, and the conductor layer is connected to the another circuit element so that a current flowing through the another circuit element flows through the conductor layer. The semiconductor device according to claim 1, wherein:
導体層の電流に基づいて生じた磁束を前記ホール効果素
子に導くように配置されていることを特徴とする請求項
１又は２又は３記載の半導体装置。4. The device according to claim 1, further comprising a magnetic collector, wherein the magnetic collector is arranged to guide a magnetic flux generated based on a current in the conductor layer to the Hall effect element. 4. The semiconductor device according to 2 or 3.
装置であって、第１及び第２のホール効果素子を有する
半導体基体と、 前記半導体基体の表面に配置された絶縁膜と、 前記第１のホール効果素子に対しては第１の方向性を有
する磁界を与え、前記第２のホール効果素子に対しては
前記第１の方向と反対の第２の方向性を有する磁界を与
えるように前記絶縁膜の上に配置され且つ前記電気回路
の電流を流すことができるように形成された導体層と、 前記第１及び第２のホール効果素子の出力電圧の絶対値
の加算値に対応する出力を得るために前記第１及び第２
のホール効果素子に接続された出力手段とを備えている
ことを特徴とする半導体装置。5. A semiconductor device for measuring a current of an electric circuit, comprising: a semiconductor substrate having first and second Hall effect elements; an insulating film disposed on a surface of the semiconductor substrate; A magnetic field having a first direction is applied to one Hall effect element, and a magnetic field having a second direction opposite to the first direction is applied to the second Hall effect element. A conductive layer disposed on the insulating film and formed so as to allow a current of the electric circuit to flow therethrough; and a conductor layer corresponding to an added value of absolute values of output voltages of the first and second Hall effect elements. The first and second
And an output means connected to the Hall effect element.
子をコ字状に囲む第１の部分と、前記第２のホール効果
素子をコ字状に囲む第２の部分と、前記第１及び第２の
ホール効果素子の間に配置され且つ前記第１及び第２の
部分を連結している第３の部分とを有していることを特
徴とする請求項５記載の半導体装置。6. The conductor layer includes a first portion surrounding the first Hall effect element in a U shape, a second portion surrounding the second Hall effect element in a U shape, and 6. The semiconductor device according to claim 5, further comprising a third portion disposed between the first and second Hall effect elements and connecting the first and second portions.
と、 前記第２のホール効果素子に接続された第２の増幅器
と、 前記第１及び第２の増幅器の出力の絶対値の加算値を得
るために前記第１及び第２の増幅器に接続された演算手
段とから成ることを特徴とする請求項５又は６記載の半
導体装置。7. The output means includes: a first amplifier connected to the first Hall effect element; a second amplifier connected to the second Hall effect element; and the first and second amplifiers. 7. The semiconductor device according to claim 5, further comprising: arithmetic means connected to said first and second amplifiers to obtain an added value of the absolute value of the output of said amplifier.
し、前記導体層は前記別の回路素子を通って流れた電流
がこの導体層を通って流れるように前記別の回路素子に
接続されていることを特徴とする請求項５又は６又は７
記載の半導体装置。8. The semiconductor substrate further includes another circuit element, and the conductor layer is connected to the another circuit element so that a current flowing through the another circuit element flows through the conductor layer. 9. The method according to claim 5, wherein
13. The semiconductor device according to claim 1.
導体層の電流に基づいて生じた磁束を前記ホール効果素
子に導くように配置されていることを特徴とする請求項
５又は６又は７又は８記載の半導体装置。9. The magnetic head according to claim 5, further comprising a magnetic collector, wherein the magnetic collector is arranged to guide a magnetic flux generated based on a current in the conductor layer to the Hall effect element. 9. The semiconductor device according to 6, 7, or 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11281745A JP2000174357A (en) | 1998-10-02 | 1999-10-01 | Semiconductor device containing hall-effect element |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10-296022 | 1998-10-02 | ||
| JP29602298 | 1998-10-02 | ||
| JP11281745A JP2000174357A (en) | 1998-10-02 | 1999-10-01 | Semiconductor device containing hall-effect element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000174357A true JP2000174357A (en) | 2000-06-23 |
Family
ID=26554307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11281745A Pending JP2000174357A (en) | 1998-10-02 | 1999-10-01 | Semiconductor device containing hall-effect element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000174357A (en) |
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