JP2910397B2 - Solder connection method - Google Patents
Solder connection methodInfo
- Publication number
- JP2910397B2 JP2910397B2 JP4102571A JP10257192A JP2910397B2 JP 2910397 B2 JP2910397 B2 JP 2910397B2 JP 4102571 A JP4102571 A JP 4102571A JP 10257192 A JP10257192 A JP 10257192A JP 2910397 B2 JP2910397 B2 JP 2910397B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- substrate
- punch
- electrode
- flux
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Description
【０００１】[0001]
【産業上の利用分野】本発明は半田接続方法に関し、特
に、半導体素子のフリップチップ実装用の半田接続方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder connection method, and more particularly to a solder connection method for flip chip mounting of a semiconductor device.
【０００２】[0002]
【従来の技術】従来より、半導体素子の高密度接続方式
として、半田バンプを形成して基板間の接続を行うフリ
ップチップ実装法が知られている。この半田バンプの形
成方法としては、メッキや蒸着で半田を供給する方法や
予め球形の半田ボールを用意し電極部に配置する方法が
ある。2. Description of the Related Art Conventionally, as a high-density connection method of semiconductor elements, a flip-chip mounting method in which solder bumps are formed to connect between substrates has been known. As a method of forming the solder bump, there is a method of supplying solder by plating or vapor deposition, or a method of preparing a spherical solder ball in advance and arranging it on the electrode portion.
【０００３】図４（ａ）〜（ｅ）は、メッキ法で半導体
素子上に半田バンプを形成する方法を示す工程断面図で
ある。まず、半導体素子の全面にスパッタなどでＣｒ等
の１１接着層、Ｎｉ等の１０拡散防止層を順次積層す
る。〔図４（ａ）〕次いで、レジスト層１２を全面に塗
布し露光、現像して電極部分のレジスト層１２を除去す
る。その後、メッキにより厚い半田を電極部に形成す
る。〔図４（ｂ）〕メッキ後は、レジスト層１２を除去
し半田メッキ層１３をマスクとして電極部以外のメッキ
下地層１４、拡散防止層１０、接着層１１をエッチング
除去し、半田供給工程が完了する。〔図４（ｃ）〕蒸着
で半田を供給する場合は、接着層１１、拡散防止層１０
はレジスト層１２を形成して電極部以外を予め除去して
おき、メッキに代わる蒸着工程では、電極部のみ穴を明
けた金属板を取付け電極部のみに半田層を形成する。通
常、半導体素子上の半田層は加熱溶融され球面状の半田
バンプに成形される。〔図４（ｄ）〕次いで、半導体素
子は基板上に位置決めされフリップチップ実装される。
〔図４（ｅ）〕 図５（ａ），（ｂ）は特願平０２ー１７８８５４で提案
した、金属シートをポンチ、ダイスを用いて所定の径と
厚みで打ち抜き、ポンチを使って直接電極上に金属片を
圧着する方法を示す。基板９上の所定の位置にポンチ１
とダイス３を位置決めする。〔図５（ａ）〕シート状の
金属材料２をポンチ１で打ち抜き、打ち抜かれた金属片
４をポンチ１先端で基板９上へ圧着する。〔図５
（ｂ）〕この方法は半田供給にも応用できる。FIGS. 4A to 4E are process sectional views showing a method of forming a solder bump on a semiconductor element by a plating method. First, 11 adhesive layers of Cr or the like and 10 diffusion prevention layers of Ni or the like are sequentially laminated on the entire surface of the semiconductor element by sputtering or the like. [FIG. 4 (a)] Next, a resist layer 12 is applied to the entire surface, exposed and developed to remove the resist layer 12 at the electrode portion. Thereafter, a thick solder is formed on the electrode portion by plating. [FIG. 4 (b)] After plating, the resist layer 12 is removed, and the plating base layer 14, the diffusion preventing layer 10, and the adhesive layer 11 other than the electrode portion are removed by etching using the solder plating layer 13 as a mask. Complete. [FIG. 4C] When solder is supplied by vapor deposition, the adhesive layer 11 and the diffusion prevention layer 10 are used.
Is formed in such a way that a resist layer 12 is formed and portions other than the electrode portions are removed in advance, and in a vapor deposition process instead of plating, a metal plate having holes only in the electrode portions is attached, and a solder layer is formed only in the electrode portions. Normally, a solder layer on a semiconductor element is heated and melted to form a spherical solder bump. [FIG. 4D] Next, the semiconductor element is positioned on the substrate and flip-chip mounted.
[FIG. 4 (e)] FIGS. 5 (a) and 5 (b) show a metal sheet punched out at a predetermined diameter and thickness using a punch and a die as proposed in Japanese Patent Application No. 02-178854, and directly using a punch. The method of crimping a metal piece is shown above. Punch 1 at predetermined position on substrate 9
And the die 3 are positioned. [FIG. 5 (a)] A sheet-shaped metal material 2 is punched with a punch 1, and the punched metal piece 4 is pressed onto a substrate 9 at the tip of the punch 1. [FIG.
(B)] This method can also be applied to solder supply.
【０００４】[0004]
【発明が解決しようとする課題】上述したような半田バ
ンプ形成方法を用いる従来の半田接続方法では、以下の
ような問題点があった。すなわち、メッキ法や蒸着法
は、工程が複雑であること、大きい膜厚の半田層を付け
るには処理時間が長くなること、このため、バンプ形成
コストが高くなること、大きな設備投資が必要であるこ
となどの問題があった。さらに、これらの方法では、組
成のずれが起き易く信頼性の高い半田を得にくいこと、
半導体素子などでは歩留を低下させる要因となること、
ウエハー状態で処理する必要があり柔軟性にかけるなど
の問題もある。またメッキ法では均一な膜を得にくいの
で形状の均一なバンプを得られないといった問題もあ
る。半田シートをポンチ、ダイスで打ち抜き、打ち抜き
用ポンチを使って半田片を直接圧着する方法は、上述の
ような欠点がないが、電極部に半田の打ち抜き片を加圧
して供給するので、表面層が機械的強度が弱い半導体素
子の場合ポンチ加圧力の高度の制御が必要となる。ま
た、半田と電極との接着力を得るには、半田と合金化し
やすいＡｕなどを電極表面につけ、基板加熱を行う必要
があり、Ａｕの半田中への拡散など信頼性上の問題があ
った。The conventional solder connection method using the above-described solder bump forming method has the following problems. That is, the plating method and the vapor deposition method require a complicated process, a long processing time is required to apply a solder layer having a large film thickness, and therefore, a bump formation cost is increased and a large capital investment is required. There was a problem such as something. Furthermore, in these methods, it is difficult to obtain a reliable solder that is likely to cause a composition shift,
In semiconductor devices etc., it may be a factor that reduces the yield,
It is necessary to process in a wafer state, and there is a problem that flexibility is required. Further, there is another problem that it is difficult to obtain a uniform film by the plating method, so that a bump having a uniform shape cannot be obtained. The method of punching a solder sheet with a punch and a die and directly pressing the solder pieces using a punch for punching does not have the disadvantages described above. However, in the case of a semiconductor element having a low mechanical strength, it is necessary to control the punch pressure at a high level. In addition, in order to obtain an adhesive force between the solder and the electrode, it is necessary to apply Au or the like, which easily alloys with the solder, to the surface of the electrode and to heat the substrate, which has a problem in reliability such as diffusion of Au into the solder. .
【０００５】[0005]
【課題を解決するための手段】１）ポンチとダイスを用
いて半田材料を打ち抜いて形成した半田片をポンチを用
いて第１の基板上の予め塗布されたフラックス層に接触
させることにより第１の基板の電極に半田片を配置し、
次いで半田片を溶融して球面状のバンプを形成し、その
後第１の基板と第２の基板とを電極間の位置合わせをし
ながら重ね合わせ、しかる後に、半田片を溶融して第１
の基板と第２の基板との電極間を接続する。 ２）ポンチとダイスを用いて半田材料を打ち抜いて形成
した半田片をポンチを用いて第１の基板上の予め形成さ
れたフラックス層に接触させることにより前記第１の基
板の電極に半田片を配置し、次いで第１の基板と第２の
基板とを電極間の位置合わせをしながら重ね合わせ、し
かる後に、半田片を溶融して第１の基板と第２の基板と
の電極間を接続する。Means for Solving the Problems 1) First, a solder piece formed by punching out a solder material using a punch and a die is brought into contact with a previously applied flux layer on a first substrate using a punch. Place solder pieces on the electrodes of the board of
Next, the solder pieces are melted to form spherical bumps. Thereafter, the first substrate and the second substrate are overlapped while positioning the electrodes, and then the solder pieces are melted to form the first bumps.
Between the electrodes of the first substrate and the second substrate. 2) A solder piece formed by punching out a solder material using a punch and a die is brought into contact with a previously formed flux layer on a first substrate using a punch, so that the solder piece is applied to an electrode of the first substrate. And then the first substrate and the second substrate are overlapped while positioning the electrodes, and then the solder pieces are melted to connect the electrodes between the first and second substrates. I do.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【０００７】図１（ａ）〜（ｄ）は、本発明の一実施例
の工程断面図である。バンプを形成すべきＬＳＩ７上に
予め回転塗布機を用いてフラックス５を塗布した。塗布
膜厚はフラックスの粘性、回転塗布機の回転数で制御で
きる。〔図１（ａ）〕次いで、ＬＳＩ７の電極にポンチ
１とダイス３を有する打ち抜き冶具を設置し、シート状
の半田材料１４を打ち抜き半田片１５を形成するととも
にポンチ１をオーバーストロークさせて半田片１５をフ
ラックス５に接触させる。打ち抜かれた半田片１５は、
弱い付着力でポンチ１に付着しているが、フラックス５
の粘着性によりポンチ１より外れ、電極６上に残ること
になる。打ち抜き冶具を電極配置に従い間欠送りさせる
ことにより電極６上に順次半田片１５を供給する。〔図
１（ｂ）〕次いで、ＬＳＩ７を加熱し半田片１５を球面
状に成形するとともに電極６との接合を行う。ここで、
半田片１５を付着させるために形成したフラックス５は
本来の加熱溶融時の半田酸化膜除去、電極濡れ性向上の
働きをするので、改めてフラックス塗布を行うことなく
好ましい形状の半田バンプ８を形成できる。〔図１
（ｃ）〕最後に、球面状の半田バンプ８を形成したＬＳ
Ｉ７を基板９と位置合わせし、再度加熱溶融することに
よりＬＳＩ７と基板９の電極間を接続する。〔図１
（ｄ）〕 本実施例では、ピッチ400μｍで配列された表面層がＣ
ｕの電極に厚さ150μｍ、直径200μｍの錫鉛共晶半田を
供給した。打ち抜き法の場合、打ち抜かれる材料の厚さ
とポンチ、ダイス径により打ち抜き片の体積は高精度の
制御ができる。フラックスは、粘度9.5cpのロジン系フ
ラックスを回転数1500rpmで塗布し、約7μｍのフラック
ス膜を形成した。フラックスがない場合、半田片を安定
して電極にのせるには半田と電極材料間の金属間接合を
得る必要があり、電極の表面層をＡｕのような酸化しに
くい層としても40ｇｆ以上の大きい加圧力を加える必要
があったが、本発明ではフラックスを塗布してあるの
で、本実施例のＣｕ、あるいはＮｉ等の酸化膜を形成す
る電極材料であっても半田片供給の際の基板電極への圧
力は３ｇｆ以下と機械的衝撃をほとんどかけることなく
半田片１５を載せることができる。塗布するフラックス
５の厚さは厚すぎる場合、半田片１６の電極６上への載
りが不安定になり、溶融時の半田片１５の流れ出しによ
るブリッジ等の不良が起きやすくなる。一方、薄すぎる
と半田片１５が電極６上に残らなくなり、また、溶融時
の酸化膜除去等の効果が不足することになる。フラック
ス厚さとしては、半田片厚さの4〜50％が適当である。FIGS. 1A to 1D are sectional views showing the steps of an embodiment of the present invention. The flux 5 was previously applied to the LSI 7 on which the bump was to be formed using a spin coater. The coating film thickness can be controlled by the viscosity of the flux and the number of rotations of the rotary coating machine. [FIG. 1 (a)] Next, a punching jig having a punch 1 and a die 3 is placed on the electrode of the LSI 7, a sheet-like solder material 14 is punched out, and a solder piece 15 is formed. 15 is brought into contact with the flux 5. The punched solder pieces 15
Adhered to punch 1 with weak adhesion, but flux 5
Is detached from the punch 1 and remains on the electrode 6. The solder pieces 15 are sequentially supplied on the electrodes 6 by intermittently feeding the punching jig according to the electrode arrangement. [FIG. 1 (b)] Next, the LSI 7 is heated to form the solder piece 15 into a spherical shape, and is bonded to the electrode 6. here,
Since the flux 5 formed for attaching the solder pieces 15 functions to remove the solder oxide film and improve the electrode wettability at the time of the actual heating and melting, the solder bump 8 having a preferable shape can be formed without re-applying the flux. . [Figure 1
(C)] Finally, the LS on which the spherical solder bumps 8 are formed
I7 is aligned with the substrate 9, and is heated and melted again to connect the LSI 7 and the electrode of the substrate 9. [Figure 1
(D)] In the present embodiment, the surface layer arranged at a pitch of 400 μm is C
A tin-lead eutectic solder having a thickness of 150 μm and a diameter of 200 μm was supplied to the electrode u. In the case of the punching method, the volume of the punched piece can be controlled with high accuracy by the thickness of the punched material and the diameter of the punch and the die. As the flux, a rosin-based flux having a viscosity of 9.5 cp was applied at 1500 rpm to form a flux film of about 7 μm. When there is no flux, it is necessary to obtain a metal-to-metal bond between the solder and the electrode material in order to stably place the solder piece on the electrode. Although it was necessary to apply a large pressing force, in the present invention, since the flux was applied, even if the electrode material for forming an oxide film such as Cu or Ni of the present embodiment was used for supplying the solder pieces to the substrate, The pressure on the electrodes is 3 gf or less, so that the solder pieces 15 can be placed with almost no mechanical impact. If the thickness of the flux 5 to be applied is too thick, the solder piece 16 is not properly placed on the electrode 6, and a defect such as a bridge due to the flow of the solder piece 15 at the time of melting tends to occur. On the other hand, if it is too thin, the solder pieces 15 will not remain on the electrodes 6, and the effect of removing an oxide film at the time of melting will be insufficient. An appropriate flux thickness is 4 to 50% of the thickness of the solder piece.
【０００８】本発明のフラックス層の形成として、スク
リーン印刷法などを用いて図２のように電極部のみにフ
ラックス層を形成してもよい。この場合、フラックスは
電極部のみにあるので、半田片供給後の溶融時に位置ず
れによるブリッジ等の不良が起きにくい。また、半田片
配列後連続して基板との接続を行う場合は、図３
（ａ），（ｂ）のように、半田片１５供給後バンプを加
熱成形することなく基板９と重ね合わせ、加熱溶融して
ＬＳＩ７と基板間の接続を行う。この場合、工程がより
簡略となる。As a method of forming the flux layer of the present invention, a flux layer may be formed only on the electrode portion as shown in FIG. 2 by using a screen printing method or the like. In this case, since the flux is present only in the electrode portion, a defect such as a bridge due to a displacement is unlikely to occur at the time of melting after supplying the solder piece. In the case where the connection with the substrate is continuously made after the solder pieces are arranged, FIG.
As shown in (a) and (b), after the solder pieces 15 are supplied, the bumps are superimposed on the substrate 9 without heat molding, and are heated and melted to perform connection between the LSI 7 and the substrate. In this case, the process is further simplified.
【０００９】以上のように、本発明の方法を用いること
により、ＬＳＩ電極に機械的衝撃を加えることなく、高
密度に配列された電極を持つＬＳＩのフリップチップ実
装が可能となる。なお、本発明に用いる半田は、錫鉛半
田のみではなく、金錫半田、インジウム系半田、錫系半
田等にも適用できる。また本発明は、ＬＳＩだけでなく
機械的衝撃に弱い配線基板に半田バンプ８を形成し接続
を行う場合にも有効である。As described above, by using the method of the present invention, it is possible to flip-chip mount an LSI having electrodes arranged at high density without applying a mechanical shock to the LSI electrode. The solder used in the present invention can be applied not only to tin-lead solder but also to gold-tin solder, indium-based solder, tin-based solder and the like. Further, the present invention is effective not only in the case of the LSI but also in the case where the solder bumps 8 are formed on the wiring board which is vulnerable to mechanical shock and the connection is made.
【００１０】[0010]
【発明の効果】以上説明したように本発明は、打ち抜き
法で形成した半田片を電極に機械的衝撃をかけることな
く供給できるので、均一な体積による半田接続を高信頼
で実現できるという効果がある。また、湿式工程や真空
工程が不要であり工程が簡略であるとともに、供給する
半田材料、電極構造に対しての制約が少なく、信頼性の
高い接合を得やすいという利点がある。As described above, according to the present invention, since the solder piece formed by the punching method can be supplied to the electrode without applying a mechanical shock, the effect that the solder connection with a uniform volume can be realized with high reliability can be realized. is there. In addition, there is an advantage that a wet process or a vacuum process is not required, the process is simplified, and there is little restriction on a supplied solder material and an electrode structure, so that highly reliable bonding is easily obtained.
【図１】（ａ）〜（ｄ）は本発明の一実施例の工程断面
図である。FIGS. 1A to 1D are process cross-sectional views of one embodiment of the present invention.
【図２】本発明の一実施例のフラックス塗布方法を示す
断面図である。FIG. 2 is a cross-sectional view illustrating a flux coating method according to one embodiment of the present invention.
【図３】（ａ），（ｂ）は本発明の一実施例の工程断面
図である。FIGS. 3A and 3B are process cross-sectional views of one embodiment of the present invention.
【図４】（ａ）〜（ｅ）は従来のメッキ法及び蒸着法に
よる半田供給方法を示す工程断面図である。FIGS. 4A to 4E are cross-sectional views showing steps of a conventional soldering method using a plating method and a vapor deposition method.
【図５】（ａ），（ｂ）はポンチとダイスを用いた打ち
抜き法による半田供給方法を示す工程断面図である。FIGS. 5A and 5B are cross-sectional views showing steps of a method of supplying solder by a punching method using a punch and a die.
１ ポンチ ２ 金属材料 ３ ダイス ４ 金属片 ５ フラックス ６ 電極 ７ ＬＳＩ ８ 半田バンプ ９ 基板 １０ 拡散防止層 １１ 接着層 １２ レジスト層 １３ 半田メッキ １４ 半田材料 １５ 半田片 Reference Signs List 1 punch 2 metal material 3 dice 4 metal piece 5 flux 6 electrode 7 LSI 8 solder bump 9 substrate 10 diffusion prevention layer 11 adhesive layer 12 resist layer 13 solder plating 14 solder material 15 solder piece
フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 H05K 3/34 505 Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 H05K 3/34 505
Claims (5)
いて形成した半田片を前記ポンチを用いて第１の基板上
の予め塗布されたフラックス層に接触させることにより
前記第１の基板の電極に前記半田片を配置し、次いで前
記半田片を溶融して球面状のバンプを形成し、その後前
記第１の基板と第２の基板とを電極間の位置合わせをし
ながら重ね合わせ、しかる後に、前記半田片を溶融して
前記第１の基板と第２の基板との電極間を接続すること
を特徴とする半田接続方法。An electrode of the first substrate is formed by bringing a solder piece formed by punching out a solder material using a punch and a die into contact with a previously applied flux layer on a first substrate using the punch. Then, the solder pieces are arranged, and then the solder pieces are melted to form spherical bumps. Thereafter, the first substrate and the second substrate are overlapped while positioning the electrodes, and then Melting the solder pieces and connecting the electrodes of the first and second substrates.
いて形成した半田片を前記ポンチを用いて第１の基板上
の予め形成されたフラックス層に接触させることにより
前記第１の基板の電極に前記半田片を配置し、次いで前
記第１の基板と第２の基板とを電極間の位置合わせをし
ながら重ね合わせ、しかる後に、前記半田片を溶融して
前記第１の基板と第２の基板との電極間を接続する請求
項１記載の半田接続方法。2. An electrode of the first substrate by bringing a solder piece formed by punching out a solder material using a punch and a die into contact with a previously formed flux layer on a first substrate using the punch. Then, the first substrate and the second substrate are overlapped with each other while aligning the electrodes, and then the first and second substrates are melted so that the first substrate and the second substrate are melted. 2. The method according to claim 1, wherein the electrodes are connected to the substrate.
れる請求項１および２記載の半田接続方法。3. The method according to claim 1, wherein the flux is formed by a spin coating method.
請求項１および２記載の半田接続方法。4. The method according to claim 1, wherein the flux is formed only on the electrode portion.
ンジウム系半田、金錫半田、金シリコン半田、金ゲルマ
ニウム半田の中のいずれかの半田である請求項１、２お
よび３記載の半田接続方法。5. The solder piece is made of any one of tin-based solder, tin-lead solder, indium-based solder, gold-tin solder, gold-silicon solder, and gold-germanium solder. The described solder connection method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4102571A JP2910397B2 (en) | 1992-04-22 | 1992-04-22 | Solder connection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4102571A JP2910397B2 (en) | 1992-04-22 | 1992-04-22 | Solder connection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0645740A JPH0645740A (en) | 1994-02-18 |
| JP2910397B2 true JP2910397B2 (en) | 1999-06-23 |
Family
ID=14330918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4102571A Expired - Lifetime JP2910397B2 (en) | 1992-04-22 | 1992-04-22 | Solder connection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2910397B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997019466A1 (en) * | 1995-11-22 | 1997-05-29 | Fry's Metals, Inc. | Method and apparatus for forming solder bumps on a substrate |
| US5829124A (en) * | 1995-12-29 | 1998-11-03 | International Business Machines Corporation | Method for forming metallized patterns on the top surface of a printed circuit board |
| JPH09326552A (en) * | 1996-06-06 | 1997-12-16 | Ueno Seiki Kk | Method and apparatus for applying solder |
| JP3633941B2 (en) * | 1996-08-27 | 2005-03-30 | 新日本製鐵株式会社 | Semiconductor device manufacturing method |
| JP4484648B2 (en) * | 1996-08-27 | 2010-06-16 | 新日鉄マテリアルズ株式会社 | Wafer and semiconductor device manufacturing method, and flip chip bonding method |
| US6441487B2 (en) * | 1997-10-20 | 2002-08-27 | Flip Chip Technologies, L.L.C. | Chip scale package using large ductile solder balls |
| US6929170B2 (en) * | 2003-09-30 | 2005-08-16 | Ted Ju | Solder deposition method |
| JP4576270B2 (en) | 2005-03-29 | 2010-11-04 | 昭和電工株式会社 | Method for manufacturing solder circuit board |
| WO2007007865A1 (en) | 2005-07-11 | 2007-01-18 | Showa Denko K.K. | Method for attachment of solder powder to electronic circuit board and solder-attached electronic circuit board |
| JP2008041867A (en) * | 2006-08-04 | 2008-02-21 | Showa Denko Kk | Manufacturing method of soldered circuit board |
| US20090261148A1 (en) * | 2006-08-03 | 2009-10-22 | Showa Denko K.K. | Production method of solder circuit board |
-
1992
- 1992-04-22 JP JP4102571A patent/JP2910397B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0645740A (en) | 1994-02-18 |
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