JP2874330B2 - Method for manufacturing multilayer printed wiring board - Google Patents
Method for manufacturing multilayer printed wiring boardInfo
- Publication number
- JP2874330B2 JP2874330B2 JP30223490A JP30223490A JP2874330B2 JP 2874330 B2 JP2874330 B2 JP 2874330B2 JP 30223490 A JP30223490 A JP 30223490A JP 30223490 A JP30223490 A JP 30223490A JP 2874330 B2 JP2874330 B2 JP 2874330B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- multilayer printed
- copper
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層印刷配線板の製造方法に関し、特に設備
の一連化が可能な多層印刷配線板の製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly, to a method for manufacturing a multilayer printed wiring board capable of serializing equipment.
一般に、内層ビアホールを有する多層印刷配線板の製
造方法は、銅箔を片面又は両面に設けた銅張り積層板の
所定の個所に穴を穿設し、次に、化学銅めっき処理、又
は、電気銅めっき処理によりスルーホールを形成する。
次に、ホトエッチング法により回路を形成し、回路銅め
っき層の表面に酸化被膜を形成する。Generally, a method of manufacturing a multilayer printed wiring board having an inner layer via hole is to form a hole in a predetermined location of a copper-clad laminate provided with copper foil on one or both sides, and then perform a chemical copper plating process, or Through holes are formed by copper plating.
Next, a circuit is formed by a photoetching method, and an oxide film is formed on the surface of the circuit copper plating layer.
以上の方法により作成した複数の内層用基板をプリプ
レグを介して、銅箔、又は、片面又は両面の外層用回路
基板と重ね合わせ加圧，加熱して多層印刷配線板を形成
する。The plurality of substrates for the inner layer prepared by the above method are overlapped with a copper foil or a circuit substrate for an outer layer on one side or both sides via a prepreg and pressurized and heated to form a multilayer printed wiring board.
上述した従来の多層印刷配線板の製造方法は、銅めっ
き処理工程と回路銅めっき層の表面に酸化被膜を形成す
る工程との中間に回路形成工程が入るので、設備を一連
化できずに分割されているため、工程間の搬送に人手を
介入させなければならず、取り扱いにより基板の折れや
損傷が発生し不良の原因となるという問題点があった。In the above-described conventional method for manufacturing a multilayer printed wiring board, a circuit formation step is inserted between a copper plating step and a step of forming an oxide film on the surface of a circuit copper plating layer. Therefore, there is a problem in that manual operation must be performed during the transportation between processes, and the handling may cause breakage or damage of the substrate, thereby causing a failure.
また、回路銅めっき層の表面に酸化被膜を形成する事
により、表面積を増加し、微細な構造の酸化物を形成す
るため樹脂との密着力を得ているが、次のプリプレグを
介して加圧，加熱して多層印刷配線板を形成する工程ま
での間長時間放置すると、回路銅めっき層の表面状態が
変質し、長期放置した場合、再度同じ処理をする必要が
あるという問題点があった。Also, by forming an oxide film on the surface of the circuit copper plating layer, the surface area is increased, and an adhesive force with the resin is obtained in order to form an oxide having a fine structure, but it is applied through the next prepreg. If left for a long time until the step of forming a multilayer printed wiring board by applying pressure and heat, the surface state of the circuit copper plating layer is altered, and if left for a long time, the same processing must be performed again. Was.
本発明の目的は、設備の一連化が可能で搬送に人手の
介入による基板の折れや損傷の発生がなく、また、長時
間放置による回路銅めっき表面状態の変質のない印刷配
線板の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a printed wiring board in which a series of facilities can be used, the substrate is not broken or damaged due to manual intervention, and the surface state of the circuit copper plating is not deteriorated by leaving it for a long time. Is to provide.
本発明の多層印刷配線板の製造方法は、表面に銅層が
被覆された内層用基板の表面銅層表面上に酸化被膜を形
成する工程と、該酸化被膜を還元処理する工程と、還元
処理された前記銅層表面上に電導性感光性樹脂被膜を用
いたホトエッチング法により回路形成を行う工程とを含
んで構成されている。The method for producing a multilayer printed wiring board according to the present invention includes a step of forming an oxide film on the surface copper layer surface of an inner layer substrate having a surface coated with a copper layer; a step of reducing the oxide film; Forming a circuit by a photo-etching method using a conductive photosensitive resin film on the surface of the copper layer thus formed.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｇ）は本発明の第１の実施例を説明
する工程順に示した断面図である。1 (a) to 1 (g) are cross-sectional views shown in the order of steps for explaining a first embodiment of the present invention.
第１の実施例は、まず第１図（ａ）に示すように、所
定の個所に穴３が穿設され、銅箔２が表面に設けてある
基板１を用意する。In the first embodiment, first, as shown in FIG. 1 (a), a substrate 1 having holes 3 drilled at predetermined locations and a copper foil 2 provided on the surface is prepared.
次に、第１図（ｂ）に示すように、化学銅めっき又は
電気銅めっき処理により銅箔２の表面上及び穴３の内壁
面に銅めっき層４を析出させる。Next, as shown in FIG. 1B, a copper plating layer 4 is deposited on the surface of the copper foil 2 and on the inner wall surface of the hole 3 by chemical copper plating or electrolytic copper plating.
次に、第１図（ｃ）に示すように、めっき層４表面上
に酸化被膜を形成させたのち、還元処理により金属箔に
還元する。Next, as shown in FIG. 1 (c), after an oxide film is formed on the surface of the plating layer 4, it is reduced to a metal foil by a reduction treatment.
次に、第１図（ｄ）に示すように、銅めっき層４表面
上に導電性感光性樹脂（以下EDと記す）被膜５を形成す
る。Next, as shown in FIG. 1 (d), a conductive photosensitive resin (hereinafter referred to as ED) film 5 is formed on the surface of the copper plating layer 4.
次に、第１図（ｅ）に示すように、露光，現像により
ED被膜５のパターン形成を行う。Next, as shown in FIG.
The pattern of the ED film 5 is formed.
次に、第１図（ｆ）に示すように、エッチングにより
銅層のパターン形成を行なう。Next, as shown in FIG. 1 (f), a copper layer pattern is formed by etching.
次に、第１図（ｇ）に示すように、積層工程前にED被
膜５を剥離する事により内層用基板が得られる。Next, as shown in FIG. 1 (g), the ED coating 5 is peeled off before the laminating step to obtain an inner layer substrate.
以上の方法により、第１図（ｂ）の銅めっき処理工程
から第１図（ｄ）のED被膜形成工程まで設備の一連化が
可能となる。According to the above method, it is possible to serialize the equipment from the copper plating process of FIG. 1 (b) to the ED film forming process of FIG. 1 (d).
第２図（ａ）〜（ｆ）は本発明の第２の実施例を説明
する工程順に示した断面図である。2 (a) to 2 (f) are cross-sectional views shown in the order of steps for explaining a second embodiment of the present invention.
第１図（ａ）〜（ｇ）に示した第１の実施例は、スル
ーホールを有する内層用基板の場合であったが、第２の
実施例では、スルーホールのない内層用基板の場合の実
施例である。The first embodiment shown in FIGS. 1 (a) to 1 (g) is a case of an inner layer substrate having a through hole, but the second embodiment is a case of an inner layer substrate having no through hole. This is an embodiment of the invention.
第２の実施例は、第２図（ａ）に示すように、まず、
銅箔２が表面に設けてある基板１を用意する。In the second embodiment, first, as shown in FIG.
A substrate 1 having a copper foil 2 provided on its surface is prepared.
第２図（ｂ）の酸化還元工程以降は、第１図（ｃ）の
工程以降と全く同じ方法で行う事により、内層用基板が
得られる。After the oxidation-reduction step in FIG. 2B, the substrate for the inner layer is obtained by performing the same method as in the step after FIG. 1C.
以上の方法により、第２図（ｂ）の銅層表面上の酸化
被膜処理工程から第２図（ｃ）のED被膜形成工程まで設
備の一連化が可能となる。According to the above-mentioned method, a series of facilities can be provided from the step of treating the oxide film on the copper layer surface in FIG. 2B to the step of forming the ED film in FIG. 2C.
以上説明したように本発明は、銅層表面上に酸化被膜
を形成したあと還元処理を導入し、これらの処理をED被
膜形成による回路形成の前に行う事により、めっき処
理，銅層表面の酸化還元処理,ED被膜による回路形成の
３工程の設備を一連化する事ができ、簡素化された無人
化の合理的なラインにできるという効果がある。As described above, the present invention introduces a reduction treatment after forming an oxide film on a copper layer surface, and performs these treatments before forming a circuit by forming an ED film, thereby performing a plating treatment and a copper layer surface treatment. The equipment of the three steps of the oxidation-reduction treatment and the circuit formation by the ED film can be integrated, and there is an effect that a simplified and unmanned rational line can be obtained.
また、ED被膜が銅層表面上の酸化被膜の保護となるた
め、積層を行う前にED被膜を剥離すれば、長期放置によ
る酸化被膜形成の再処理が不要になるという効果を有す
る。In addition, since the ED film protects the oxide film on the surface of the copper layer, if the ED film is peeled off before lamination, there is an effect that it is not necessary to reprocess the oxide film formation after long-term standing.
第１図（ａ）〜（ｇ）は本発明の第１の実施例を説明す
る工程順に示した断面図、第２図（ａ）〜（ｆ）は本発
明の第２の実施例を説明する工程順に示した断面図であ
る。 １……基板、２……銅箔、３……穴、４……銅めっき
層、５……ED被膜。1 (a) to 1 (g) are cross-sectional views shown in the order of steps for explaining a first embodiment of the present invention, and FIGS. 2 (a) to 2 (f) illustrate a second embodiment of the present invention. FIG. 1 ... substrate, 2 ... copper foil, 3 ... hole, 4 ... copper plating layer, 5 ... ED coating.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H05K 3/46 H05K 3/06 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H05K 3/46 H05K 3/06
Claims (1)
銅層表面上に酸化被膜を形成する工程と、該酸化被膜を
還元処理する工程と、還元処理された前記銅層表面上に
電導性感光性樹脂被膜を用いたホトエッチング法により
回路形成を行う工程とを含む事を特徴とする多層印刷配
線板の製造方法。A step of forming an oxide film on the surface of the copper layer of the inner layer substrate having a surface coated with a copper layer, a step of reducing the oxide film, and a step of reducing the oxide film on the surface of the copper layer. Forming a circuit by a photo-etching method using a conductive photosensitive resin film on the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30223490A JP2874330B2 (en) | 1990-11-07 | 1990-11-07 | Method for manufacturing multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30223490A JP2874330B2 (en) | 1990-11-07 | 1990-11-07 | Method for manufacturing multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04174596A JPH04174596A (en) | 1992-06-22 |
| JP2874330B2 true JP2874330B2 (en) | 1999-03-24 |
Family
ID=17906566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30223490A Expired - Lifetime JP2874330B2 (en) | 1990-11-07 | 1990-11-07 | Method for manufacturing multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2874330B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| MY144574A (en) | 1998-09-14 | 2011-10-14 | Ibiden Co Ltd | Printed circuit board and method for its production |
| CN105517361B (en) * | 2015-12-18 | 2019-03-12 | 景旺电子科技(龙川)有限公司 | The production method of copper billet in a kind of pcb board containing copper billet |
-
1990
- 1990-11-07 JP JP30223490A patent/JP2874330B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04174596A (en) | 1992-06-22 |
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