JP2867896B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2867896B2 JP2867896B2 JP6276057A JP27605794A JP2867896B2 JP 2867896 B2 JP2867896 B2 JP 2867896B2 JP 6276057 A JP6276057 A JP 6276057A JP 27605794 A JP27605794 A JP 27605794A JP 2867896 B2 JP2867896 B2 JP 2867896B2
- Authority
- JP
- Japan
- Prior art keywords
- provisional
- semiconductor device
- circuit
- metallization
- metallization layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特にゲートアレイ等、メタライズ工程にて同一
下地に異なったメタライズパターンを施し、個々の機能
を持たせた半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having different functions by applying different metallization patterns to the same base in a metallization step such as a gate array. .
【０００２】[0002]
【従来の技術】一般に、ゲートアレイ品種は、半導体ウ
エハ上にトランジスタ、抵抗、容量等の基本素子を形成
した段階で一旦中間入庫させる。その後、顧客の個々の
要求に応じたメタライズパターンを適用したメタライズ
工程を経て、所望の回路が半導体ウエハ上に構成され
る。したがって、製品としての基本的機能検査は、この
段階になって初めて行なわれている。また、所望の集積
回路が複数個形成された半導体ウエハ上に複数個のモニ
タ素子を設け、そのモニタ素子の特性を検査することで
所望の集積回路の特性を間接的に確認したり、間接的な
故障、解析手段を持たせるといった公知例もある（特開
昭５７−４０９５１号）。2. Description of the Related Art In general, a gate array product is temporarily stored in an intermediate stage when basic elements such as a transistor, a resistor, and a capacitor are formed on a semiconductor wafer. After that, a desired circuit is formed on the semiconductor wafer through a metallization process in which a metallization pattern according to each customer's request is applied. Therefore, a basic functional test as a product is performed only at this stage. In addition, a plurality of monitor elements are provided on a semiconductor wafer on which a plurality of desired integrated circuits are formed, and the characteristics of the desired integrated circuit are indirectly confirmed by inspecting the characteristics of the monitor elements, or indirectly. There is also a known example of providing a failure and analysis means (Japanese Patent Laid-Open No. 57-40951).
【０００３】[0003]
【発明が解決しようとする課題】トランジスタ、抵抗、
容量等の基本素子の形成が完了したウエハを、その後の
メタライズ工程を経て所望の回路を構成する方法では、
製品としての基本的機能検査は、ウエハが完成する最終
段階になって初めて行なわれる。所望の良品数を得るの
に最小限のウエハをメタライズ投入すれば、資材的に効
率がよいわけであるが、得られる良品数の数はウエハ完
成段階になって判明する。そこで、通常は納期を優先
し、所望の良品数より、多めにメタライズ投入される。
そのため、資材の無駄使いや持たなくてもよい完成在庫
を持つという問題がある。また、後者の公知例の場合、
結晶欠陥やゴミ、キズといった個々の半導体集積回路に
固有の不具合については、検出がまったく不可能であっ
たり、モニタ素子がウエハ上の集積回路素子群のほんの
一部であるため、ウエハ全体レベルでの良否判定を行う
にはあまりに小規模であるという問題がある。SUMMARY OF THE INVENTION A transistor, a resistor,
In a method of forming a desired circuit on a wafer on which formation of basic elements such as capacitors has been completed through a subsequent metallizing step,
The basic functional test of a product is performed only at the final stage of the completion of a wafer. Metallizing a minimum number of wafers to obtain a desired number of non-defective products is efficient in terms of material, but the number of non-defective products to be obtained becomes clear at the wafer completion stage. Therefore, usually, the delivery date is prioritized, and metallization is input more than a desired number of good products.
For this reason, there is a problem that the material is wasted or the finished stock which does not need to be held. In the case of the latter known example,
For defects unique to individual semiconductor integrated circuits such as crystal defects, dust, scratches, etc., it is impossible to detect them at all, or because the monitor elements are only a part of the integrated circuit element group on the wafer, There is a problem that the scale is too small to judge pass / fail.
【０００４】[0004]
【課題を解決するための手段】本発明は、メタライズ工
程にて同一下地ウェハに異なったメタライズパターンを
施し、個々の機能を持たせる半導体装置の製造方法にお
いて、トランジスタ、抵抗、容量等の基本素子を半導体
ウエハ上に形成した段階の半導体装置に、暫定メタライ
ズ層を形成する工程と、前記暫定メタライズ層により形
成された暫定判別回路の機能を検査する暫定判別工程
と、前記暫定メタライズ層を除去する工程とを含み、前
記暫定判別回路は、前記半導体装置の入力回路部の素子
とセル部の一部の素子とで構成された多入力ＮＡＮＤ回
路と、この多入力ＮＡＮＤ回路の出力を受け前記半導体
装置の出力回路部に信号を出力する、前記半導体装置の
セル部に形成された複数のインバータが直列接続された
回路とを含むことを特徴とする半導体装置の製造方法で
ある。また本発明は、コンタクトホールを覆うバリアメ
タル層を形成した後、前記暫定メタライズ層を形成する
ことを特徴とする上記の半導体装置の製造方法である。SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device in which different metallization patterns are formed on the same base wafer in a metallization step so as to have individual functions. Forming a provisional metallization layer on a semiconductor device at the stage where the provisional metallization layer is formed on a semiconductor wafer, a provisional determination step of testing a function of a provisional determination circuit formed by the provisional metallization layer, and removing the provisional metallization layer. The provisional determination circuit includes a multi-input NAND circuit including an element of an input circuit unit of the semiconductor device and a part of an element of a cell unit, and receiving the output of the multi-input NAND circuit. Outputting a signal to an output circuit unit of the device, including a circuit in which a plurality of inverters formed in a cell unit of the semiconductor device are connected in series. It is a manufacturing method of a semiconductor device according to symptoms. Further, the present invention is the method for manufacturing a semiconductor device described above, wherein the provisional metallized layer is formed after forming a barrier metal layer covering the contact hole.
【０００５】[0005]
【作用】本発明においては、機能検査用メタライズパタ
ーンによる暫定メタライズと当該メタライズによる機能
に対応した暫定判別工程と前記暫定メタライズ層を除去
する工程を含むことにより、その後行なわれる本番メタ
ライズでの歩留りを正確に予測できるもので、即ち、ト
ランジスタや抵抗等の基本素子を半導体ウエハ上に形成
した段階でそのウエハの良否判定を行いうことができる
もので、追加ウエハの投入や拡散工程へのフイードバッ
クを迅速に行得るものである。The present invention includes provisional metallization using a function-inspection metallization pattern, a provisional determination step corresponding to the function based on the metallization, and a step of removing the provisional metallization layer, thereby reducing the yield in the subsequent production metallization. It can be predicted accurately, that is, it can judge the quality of the wafer at the stage when the basic elements such as transistors and resistors are formed on the semiconductor wafer, and feeds in additional wafers and feedback to the diffusion process. It can be done quickly.
【０００６】[0006]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１は、本発明による一実施例の半導体チ
ップの断面図である。図１に示すように、半導体装置の
製造方法にあたっては、Ｐ型シリコン基板（１）の上に
酸化膜（２）を形成し、ホトリソグラフイ技術を用いて
形成したコンタクトホールから、熱拡散やイオンインプ
ランテイション技術にてｎ＋拡散層（３）を形成する。
このｎ＋拡散層（３）上に暫定メタライズ層（５）を形
成するものであるが、この実施例では、まずバリアメタ
ル層（４）を形成し、さらに暫定メタライズ層（５）を
形成する。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor chip according to one embodiment of the present invention. As shown in FIG. 1, in a method of manufacturing a semiconductor device, an oxide film (2) is formed on a P-type silicon substrate (1), and heat diffusion or heat diffusion is performed from a contact hole formed using photolithography. An n + diffusion layer (3) is formed by an ion implantation technique.
The provisional metallization layer (5) is formed on the n + diffusion layer (3). In this embodiment, first, the barrier metal layer (4) is formed, and then the provisional metallization layer (5) is formed. .
【０００７】この暫定メタライズ層（５）の形成時に、
検査用の回路を構成し、製造された半導体集積回路の入
力パッドに特定のテストパターンを入力し、出力の期待
値を出力パッドにて確認する。この検査は通常行ってい
るウエハ上の集積回路の良否判断と同じく、ＬＳＩテス
タとウェハブローバを直結して行うウェハテスト技術で
行う。その後、暫定メタライズ層（５）により形成され
たウエハ上の個々の半導体集積回路の歩留りを確認し、
製造技術や設計技術で決まる目標値に達したなら、暫定
メタライズ層（５）を除去し、中間入庫したり、あるい
は目標値に達しない場合、原因究明や追加下地ウェハ投
入を行なう等の処置を行う。At the time of forming the provisional metallized layer (5),
A test circuit is formed, a specific test pattern is input to an input pad of a manufactured semiconductor integrated circuit, and an expected output value is confirmed by an output pad. This inspection is performed by a wafer test technique, which is performed by directly connecting an LSI tester and a wafer blower, similarly to the normal determination of the quality of an integrated circuit on a wafer. Thereafter, the yield of each semiconductor integrated circuit on the wafer formed by the provisional metallization layer (5) is confirmed,
When the target value determined by the manufacturing technology or the design technology is reached, the provisional metallized layer (5) is removed, and if the target value is not reached, take measures such as investigating the cause or inserting an additional base wafer. Do.
【０００８】図２は、本発明による一実施例の半導体装
置の製造工程フローを示す図である。図２の製造工程フ
ローに示すように、基本素子を半導体ウエハ上に形成し
た半導体装置に、暫定メタライズ層形成、次いでＬＳＩ
テスタによる暫定判別工程により個々の半導体集積回路
の判別を行う。目標値に達したものは、ＹＥＳの矢印に
進み、暫定メタライズ層除去し、本番メタライズ工程に
供する。一方、目標値に達したなかったものは、ＮＯの
矢印に進み、故障解析とフィードバックし、追加下地ウ
ェハ投入等処置を行うのである。FIG. 2 is a diagram showing a manufacturing process flow of a semiconductor device according to one embodiment of the present invention. As shown in the manufacturing process flow of FIG. 2, a provisional metallized layer is formed on a semiconductor device in which basic elements are formed on a semiconductor wafer, and then an LSI is formed.
The individual semiconductor integrated circuits are determined by a provisional determination process using a tester. After reaching the target value, the process proceeds to the arrow of YES, the provisional metallized layer is removed, and the metallized layer is provided for the actual metallizing step. On the other hand, if the target value has not been reached, the process proceeds to the arrow of NO, failure analysis and feedback are performed, and processing such as additional base wafer introduction is performed.
【０００９】暫定メタライズ層（５）は、その除去時に
ｎ＋拡散層（３）に悪影響を与えないものなら何でもよ
い。例えば、暫定メタライズ層（５）にアルミニウムを
用いた場合は、ｎ＋拡散層（３）のシリコンが暫定メタ
ライズ層（５）に吸われてしまうので、これを除くた
め、バリアメタル層（４）を用いる。バリアメタル層
（４）がＴｉＷ、ＴｉＮの場合、暫定メタライズ層
（５）のアルミニウムは、Ｈ３ＰＯ４をもちいれば、バ
リアメタル層（４）やｎ＋拡散層（３）に対するダメー
ジなく暫定メタライズ層（５）を除去できる。The provisional metallization layer (5) may be anything as long as it does not adversely affect the n + diffusion layer (3) when it is removed. For example, when aluminum is used for the provisional metallization layer (5), the silicon of the n + diffusion layer (3) is absorbed by the provisional metallization layer (5). Is used. In the case where the barrier metal layer (4) is TiW or TiN, the aluminum of the provisional metallization layer (5) is provisional without damage to the barrier metal layer (4) and the n + diffusion layer (3) by using H 3 PO 4. The metallization layer (5) can be removed.
【００１０】図３は、暫定メタライズ層（５）により構
成する暫定判別回路の一例を示す図である。図３の例で
は、入力回路部（１０）とセル部（１１）の一部の素子
で多入力ＮＡＮＤ回路（１２）を構成する。セル部（１
１）ではセルの使用率がなるべく高くなるように、イン
バータ（１３）を直列接続し、インバータ（１３）の出
力をゲートアレイの持つそれぞれの出力回路部（１４）
に接続する。ＬＳＩテスタによる個々の半導体装置の良
否判定は、このように構成した論理回路の入出力の論理
判定により行なう。FIG. 3 is a diagram showing an example of a provisional determination circuit constituted by a provisional metallization layer (5). In the example of FIG. 3, a multi-input NAND circuit (12) is configured by the input circuit section (10) and some elements of the cell section (11). Cell part (1
In 1), the inverters (13) are connected in series so that the usage rate of cells becomes as high as possible, and the output of the inverter (13) is output to each output circuit section (14) of the gate array.
Connect to The pass / fail judgment of each semiconductor device by the LSI tester is performed by the logical judgment of the input / output of the logic circuit thus configured.
【００１１】[0011]
【発明の効果】以上説明したように、本発明によれば、
ウエハ上に形成された個々の半導体装置に対し、機能検
査用メタライズパタンによる暫定メタライズ層を形成す
ることで、暫定的な判別が行なえる。そのため、その後
行なわれる本番メタライズでの歩留りを正確に予測でき
る。また、歩留りが期待値に達しなかった場合のフイー
ドバックも迅速に行える。これにより、生産性向上に大
きく寄与するという効果を奏するものである。As described above, according to the present invention,
By forming a provisional metallization layer using a function inspection metallization pattern on each semiconductor device formed on the wafer, provisional determination can be made. Therefore, the yield in the subsequent production metallization can be accurately predicted. Further, when the yield does not reach the expected value, feedback can be quickly performed. Thereby, there is an effect that it greatly contributes to the improvement of productivity.
【図面の簡単な説明】[Brief description of the drawings]
【図１】 本発明による一実施例の半導体チップの断面
図。FIG. 1 is a sectional view of a semiconductor chip according to one embodiment of the present invention.
【図２】 本発明による一実施例の半導体装置の製造工
程フローを示す図。FIG. 2 is a view showing a manufacturing process flow of the semiconductor device of one embodiment according to the present invention;
【図３】 暫定判別回路の一例を示す図。FIG. 3 is a diagram illustrating an example of a provisional determination circuit.
１ Ｐ型シリコン基板 ２ 酸化膜 ３ ｎ＋拡散層 ４ バリアメタル層 ５ 暫定メタライズ層 １０ 入力回路部 １１ セル部 １２ 多入力ＮＡＮＤ回路 １３ インバータ １４ 出力回路部DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Oxide film 3 n + diffusion layer 4 Barrier metal layer 5 Temporary metallization layer 10 Input circuit part 11 Cell part 12 Multi-input NAND circuit 13 Inverter 14 Output circuit part
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/82 H01L 21/66 H01L 27/118 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/82 H01L 21/66 H01L 27/118
Claims (2)
なったメタライズパターンを施し、個々の機能を持たせ
る半導体装置の製造方法において、トランジスタ、抵
抗、容量等の基本素子を半導体ウエハ上に形成した段階
の半導体装置に、暫定メタライズ層を形成する工程と、
前記暫定メタライズ層により形成された暫定判別回路の
機能を検査する暫定判別工程と、前記暫定メタライズ層
を除去する工程とを含み、前記暫定判別回路は、前記半
導体装置の入力回路部の素子とセル部の一部の素子とで
構成された多入力ＮＡＮＤ回路と、この多入力ＮＡＮＤ
回路の出力を受け前記半導体装置の出力回路部に信号を
出力する、前記半導体装置のセル部に形成された複数の
インバータが直列接続された回路とを含むことを特徴と
する半導体装置の製造方法。In a method of manufacturing a semiconductor device in which different metallization patterns are applied to the same base wafer in a metallization step and individual functions are provided, a step of forming basic elements such as transistors, resistors and capacitors on the semiconductor wafer. Forming a provisional metallization layer on the semiconductor device of
A provisional determination step of testing the function of a provisional determination circuit formed by the provisional metallization layer, and a step of removing the provisional metallization layer, wherein the provisional determination circuit includes an element and a cell of an input circuit unit of the semiconductor device. Multi-input NAND circuit constituted by some elements of the
A circuit in which a plurality of inverters formed in a cell portion of the semiconductor device are connected in series and receive a circuit output and output a signal to an output circuit portion of the semiconductor device. .
を形成した後、前記暫定メタライズ層を形成することを
特徴とする請求項１に記載の半導体装置の製造方法。2. The method according to claim 1, wherein the provisional metallization layer is formed after forming a barrier metal layer covering the contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6276057A JP2867896B2 (en) | 1994-10-14 | 1994-10-14 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6276057A JP2867896B2 (en) | 1994-10-14 | 1994-10-14 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08115980A JPH08115980A (en) | 1996-05-07 |
| JP2867896B2 true JP2867896B2 (en) | 1999-03-10 |
Family
ID=17564199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6276057A Expired - Fee Related JP2867896B2 (en) | 1994-10-14 | 1994-10-14 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2867896B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5759356A (en) * | 1980-09-29 | 1982-04-09 | Hitachi Ltd | Structure of multilayer wiring |
| JPH079521B2 (en) * | 1988-12-29 | 1995-02-01 | 松下電器産業株式会社 | Method of manufacturing active matrix substrate capable of detecting and repairing point defects |
| JPH04130748A (en) * | 1990-09-21 | 1992-05-01 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
-
1994
- 1994-10-14 JP JP6276057A patent/JP2867896B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08115980A (en) | 1996-05-07 |
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